<topic name='options'>
<text>
 These are the available global options for the simulator.  You can
 set them one of two ways: 1) via the .option statement in the
 netlist, or 2) with the -D command line option.  All option settings
 must be in &quot;name=value&quot; format, including boolean options.
 (e.g. &quot;-D dcnode=yes&quot;)

</text>
<options>
<option name='abstol'>Absolute error tolerance for branch current</option>
<option name='adaptive_extrapolation'>change extrapolation order according to the distance from event</option>
<option name='algdc'>DC convergence algorithms</option>
<option name='allow_dangling_nets'>Auto insertion of gmin on dangling nets</option>
<option name='allow_neg_rlc'>allow negative rlc </option>
<option name='autodc'>Use the automatic dc flow</option>
<option name='cap'>create node capacitance table at each op solution</option>
<option name='capmax'>flag all node caps larger than capmax.</option>
<option name='check_pnjunc'>check forward-biased PN junc</option>
<option name='cmin'>minimum node capacitance</option>
<option name='create_bridge_points'>create two bridge points between each break point</option>
<option name='ctrl_src_limiting'>apply limiting to nonlinear control sources</option>
<option name='ctrl_src_transition'>apply transition to nonlinear control sources   </option>
<option name='curmax'>maximum current allowed </option>
<option name='dangling_devices'>control handling of devices(r/v) </option>
<option name='dcmax_check'>check voltmax/curmax for dc   </option>
<option name='dcnode'>output node voltages at op, tranop, or tpunch points</option>
<option name='dcnode_resist'>output node equivalent resistances at op, tranop, or tpunch points</option>
<option name='device_gmin'>Minimum diode parallel conductance</option>
<option name='diag_damp'>Diagonal damping option</option>
<option name='digital_logicx'>allow x in digital_a2d </option>
<option name='digital_tres'>digital tres option</option>
<option name='dispfreq'>Timepoint display frequency  </option>
<option name='expression_selftesting'>test expression analytical derivatives with its numerical derivatives</option>
<option name='fillctrl'>maximum ratio of matrix fills to nonzeros</option>
<option name='filter'>Filter the output data to reduce output size.</option>
<option name='filter_abstol'>Filter abstol for non voltage signals.</option>
<option name='filter_alg'>Filter algorithm: &quot;abstol&quot; or &quot;deviation&quot;.</option>
<option name='filter_reltol'>Filter reltol for all other signals.</option>
<option name='filter_tol'>Filter tolerance for deviation algorithm.</option>
<option name='filter_vabstol'>Filter abstol for voltage signals.</option>
<option name='fixed_biased_dev'>Replace fixed biased devices</option>
<option name='force_selfheating'>always on during dc </option>
<option name='geq'>Equvalent conductance for holding initial values from isspice</option>
<option name='gmin'>Minimum conductance</option>
<option name='hold_ic'>hold IC during OP  </option>
<option name='iabstol'>Absolute error tolerance for branch current</option>
<option name='ignore_output_lte'>ignore lte check for output nodes   </option>
<option name='init_vbe'>inital Vbe value for BJT</option>
<option name='init_vgs'>inital Vgs value for MOSFET</option>
<option name='isolated_nets'>control handling of nets with no topological path to ground: error (default), warning</option>
<option name='itl1'>Iteration limiting for Newton and Gmin stepping (2X)</option>
<option name='itl2'>Iteration limiting for Newton during DC sweeps</option>
<option name='kcl_check'>Check KCL, on/off/dc_only/tran_only</option>
<option name='kcl_node_list'>KCL check list select method, selective/full/none</option>
<option name='list'>Output device parameters</option>
<option name='lone'>Expression value for a boolean 1.</option>
<option name='lte_check'>Check for location trunction error</option>
<option name='lthresh'>Expression value for the threshold on boolean operations.</option>
<option name='lzero'>Expression value for a boolean 0.</option>
<option name='matrix_reordering'>Conditions for matrix reordering</option>
<option name='maxmos_dim'>Checks all MOS device maximum dimensions (microns).</option>
<option name='mextram_clip'>When a mextram model is clipped, how should we report it?  warning or error?</option>
<option name='mextram_fex'>Override mextram EXMOD to help convergence in some cases.</option>
<option name='min_start_phase'>Minimum phase for first point in an AC response waveform.</option>
<option name='minmos_dim'>Checks all MOS device minimum dimensions (microns).</option>
<option name='mod'>Output all model parameters</option>
<option name='nl_dev_curmax'>maximum current for nonlinear devices</option>
<option name='nl_dev_gmax'>maximum conductance for nonlinear devices</option>
<option name='node'>Output a table showing devices connected to each node</option>
<option name='nport'>fft mode</option>
<option name='numdgt'>Number of digits for precision in ascii output</option>
<option name='op'>Output device operating point values</option>
<option name='parallel_gmin'>Cross gmin </option>
<option name='partial_op'>Output device operating point values at partial results times</option>
<option name='pivabs'>Absolute pivot threshold</option>
<option name='pivrel'>Relative pivot threshold</option>
<option name='psfxl_flush_interval'>The nominal PSFXL flush rate (can grow)</option>
<option name='psfxl_init_flush_interval'>The initial PSFXL flush rate</option>
<option name='psfxl_max_flush_interval'>The upper limit that PSFXL flush rate can grow to</option>
<option name='pst_iterations'>Number of iterations allowed for PST</option>
<option name='pst_points'>Number of points allowed for PST</option>
<option name='pst_ramp_time'>Ramp time for PST</option>
<option name='pst_resets'>Number of resets allowed for PST</option>
<option name='pst_skip_newton'>Skip final newton </option>
<option name='pst_stop_time'>Stop time for PST</option>
<option name='punch_select'>How to handle errors when processing punch selection statements</option>
<option name='pwl_smooth'>PWL smooth coeff (0~0.5)</option>
<option name='random_seed'>unsigned seed for system random functions</option>
<option name='reltol'>Relative error tolerance</option>
<option name='res_limiting'>limit resistor value between rmin and gmin, pspice should set this to false </option>
<option name='resmax'>Threshold for outputing node equivalent resistance</option>
<option name='rmin'>Minimum resistance</option>
<option name='roundtol'>absolute tolerance for matrix rounding errors</option>
<option name='rshunt'>Resistor to groud for all the user-defined nets</option>
<option name='rthresh'>the threshold that small res will use ccvs formular v=i*r</option>
<option name='src_use_t0'>src use t=0 value for DC</option>
<option name='subckt'>Output subcircuit parameters</option>
<option name='temp_scale_tol'>Ratio betweeen absolute temperature tol and absolute voltage tol</option>
<option name='tempmax'>Override tempmax parameter for all models in Celsius degree</option>
<option name='ti_bsim3_noise'>global overide of bsim3 NLEV model parameter</option>
<option name='tnom'>Nominal model temperature in Celsius degree</option>
<option name='tpunch_small_signal'>Run all small signal analyses only at each tpunch point.</option>
<option name='vabstol'>Absolute error tolerance for node voltage</option>
<option name='vccs_cmin'>add cmin to vccs terminals  </option>
<option name='vcvs_gmin'>add cross gmin to vcvs output</option>
<option name='veriloga_prune'>isolated veriloga device can be pruned</option>
<option name='voltmax'>maximum voltage allowed </option>
</options>
</topic>
