//============================================================
# f377 source
//74F377: Octal D Flip-Flops with clock enable
//dm 10-24-97: copied ls377 in LS.TXT
//	changed SUPPLY_MIN_MAX, VIL_VIL_VALUE,
//  iol, ioh, iil, iih, icc, rise, fall
//  setup, hold, width and prop delays values.
// jjt 16/3/2001: added D6 and D7
//                to the internal_reg assignment statement and
//                state_bit assignment statement
//============================================================
INPUTS VCC, GND, E, CP, D7, D6, D5, D4, D3, D2, D1, D0;
OUTPUTS VCC_LD, E_LD, CP_LD, D7_LD, D6_LD, D5_LD, D4_LD, D3_LD, D2_LD, D1_LD,
		D0_LD, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0;
INTEGERS internal_reg;
REALS tt_val, tplh_val, tphl_val, ril_val, rih_val, riccl_val,
	  ricch_val, ricc_val, ts_data, thh_data, thl_data,
	  tsh_val, tsl_val, th_val, CP_twh, CP_twl;

PWR_GND_PINS(VCC,GND);		//set pwr_param and gnd_param values
SUPPLY_MIN_MAX(4.5,5.5);	//check for min supply=4.5 and max supply=5.5
VOL_VOH_MIN(0.2,-0.4,0.1);	//set min vol_param=gnd_param+0.2, max voh_param=pwr_param-0.4
VIL_VIH_VALUE(1.45,1.55);	//set input threshold values: vil and vih
IO_PAIRS(E:E_LD, CP:CP_LD, D7:D7_LD, D6:D6_LD, D5:D5_LD,
         D4:D4_LD, D3:D3_LD, D2:D2_LD, D1:D1_LD, D0:D0_LD);

IF (init_sim) THEN
  BEGIN
//MESSAGE("time\tCP\tE\tD0\tD1\tD2\tD3\tD4\tD5\tD6\tD7\tQ0\tQ1\tQ2\tQ3\tQ4\tQ5\tQ6\tQ7");

    //NOTE: both ttlh and tthl are the same value
    tt_val= (MIN_TYP_MAX(tt_param: NULL, 2.5n,  NULL));

    tplh_val= (MIN_TYP_MAX(tp_param: 4n, 7n, 9n));
	tphl_val= (MIN_TYP_MAX(tp_param: 4n, 7n, 9n));

	ts_data= (2n);
	thh_data= (0n);
	thl_data= (1n);

	tsh_val= (3n);
	tsl_val= (4n);
	th_val= (0n);

	CP_twh= (4n);
	CP_twl= (4.5n);

    //F std output drive IOL max=20mA @ vol=0.5V: rol_param=(0.5-vol_param)/20mA
    rol_param= (MIN_TYP_MAX(drv_param: NULL, 15,  NULL));

    //F std output drive IOH max=-1mA @ voh=4.5V: roh_param=(voh_param-4.5)/1mA
    roh_param= (MIN_TYP_MAX(drv_param: NULL, 100, NULL));

    //F input load IIH=20uA @ 2.7V: ril= (2.7-vol_param)/20uA;
    ril_val= (MIN_TYP_MAX(ld_param: NULL, NULL, 125k));

    //F input load IIL=-20uA @ 0.5V: rih= (voh_param-0.5)/20uA
    rih_val= (MIN_TYP_MAX(ld_param: NULL, NULL, 205k));

    //Icch with output high: 90.9= 5V/55mA typical, 76.4= 5.5V/72mA max 
    ricch_val= (MIN_TYP_MAX(i_param: NULL, 90.9, 76.4));

    //Iccl with output low: 71.4= 5V/70mA typical, 61.1= 5.5V/90mA max 
    riccl_val= (MIN_TYP_MAX(i_param: NULL, 71.4, 61.1));

    internal_reg= (0);
	STATE Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 = ZERO;	//initialize output
	EXIT;
  END;

DRIVE Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 = (v0=vol_param,v1=voh_param,ttlh=tt_val,tthl=tt_val);
LOAD E_LD CP_LD D7_LD D6_LD D5_LD D4_LD D3_LD D2_LD D1_LD D0_LD =
	 (v0=vol_param,r0=ril_val,v1=voh_param,r1=rih_val,io=1e9,t=1p);

IF ((~(E)) && CHANGED_LH(CP)) THEN
  BEGIN
    internal_reg= (NUMBER(D7 D6 D5 D4 D3 D2 D1 D0));
  END;

STATE_BIT Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7= (internal_reg);

//MESSAGE("%fs\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d",
//	   present_time,CP,E,D0,D1,D2,D3,D4,D5,D6,D7,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7);
IF (Q7 && Q6 && Q5 && Q4 && Q3 && Q2 && Q1 && Q0) THEN
  BEGIN
    ricc_val= (ricch_val);	//output high
  ELSE
    ricc_val= (riccl_val);	//output low
  END;

LOAD VCC_LD = (v0=gnd_param,r0=ricc_val,t=1p);
IF (warn_param) THEN
  BEGIN
	WIDTH(CP Twl=CP_twl Twh=CP_twh "CP");
	SETUP_HOLD(CP=LH D0 D1 D2 D3 D4 D5 D6 D7 Ts=ts_data Thh=thh_data Thl=thl_data "Dn->CP");
	SETUP_HOLD(CP=LH E Tsh=tsh_val Tsl=tsl_val Th=th_val "E->CP");
  END;

DELAY Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 =
  CASE (TRAN_LH) : tplh_val
  CASE (TRAN_HL) : tphl_val
END;
EXIT;