----------------------------------------------------------------------- 
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 
-- -------------------------------------------------------------------- 
-- Copyright (c) 2001 by Lattice Semiconductor Corporation 
-- -------------------------------------------------------------------- 
-- 
-- 
--                     Lattice Semiconductor Corporation 
--                     5555 NE Moore Court 
--                     Hillsboro, OR 97214 
--                     U.S.A 
-- 
--                     TEL: 1-800-Lattice (USA and Canada) 
--                          408-826-6000 (other locations) 
-- 
--                     web: http://www.latticesemi.com/ 
--                     email: techsupport@latticesemi.com 
-- 
-- -------------------------------------------------------------------- 
-- 
-- Simulation Library File for ispXPGA device 
-- 
-- -------------------------------------------------------------------- 
-- 
-- Revision History : 
-- $Header: R:/src/mod_kits/ispXPGA/VHDL/rcs/lava1.vhd 1.83 2004/03/25 18:48:30Z jli Exp $
-- Remove REN for MS;
-- Added arc for AS_LSB;
-- Modified the array element to pass MTI;
-- REV 1.1;
-- REV 1.2, changed the sympath from 20 bit to 2 bit for CDRX_10B12B;
-- REV 2.0: change RAMB256X18DSR & RAMB512X9DSR to not use CE as enable 
--          during write operations
-- REV 3.0: change cdrx_ss* and tx_ss* to compute half_period not using
--          the negedge. use posedge to posedge and divide it by two 
-- REV 4.0: change INIT values of RAM -- 20 bits longer than declared
-- REV 5.0: specify array_size (instead of open) in generic_map; eliminate
--          the second duplicated SC_SPRAM_16K_L module



LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.VITAL_timing.all;
USE IEEE.VITAL_primitives.all;
 
 
package VLOGTOVITAL_TABLES is
 
---------------------------------------------------------------------------------
-- Local type declaration
---------------------------------------------------------------------------------

    TYPE edge_table IS ARRAY (std_ulogic, std_ulogic) OF boolean ;

---------------------------------------------------------------------------------
-- Contants Specifications
-- posedge, negedge
---------------------------------------------------------------------------------
    CONSTANT POSEDGE : edge_table := (
    --      ---------------------------------------------------------
    --      |  U      X      0      1      Z      W      L      H      - |   |
    --      ---------------------------------------------------------
            ( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
            ( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
            ( FALSE, TRUE,  FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
            ( FALSE, FALSE, FALSE, FALSE,FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
            ( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
            ( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
            ( FALSE, TRUE,  FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
            ( FALSE, FALSE, FALSE, FALSE,FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
            ( FALSE, FALSE, FALSE, FALSE,FALSE, FALSE, FALSE, FALSE, FALSE )  -- | - |
        );

    CONSTANT NEGEDGE : edge_table := (
    --      ---------------------------------------------------- -----
    --      |  U    X    0    1    Z    W    L    H    - |   |
    --      ---------------------------------------------------- -----
            ( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
            ( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
            ( FALSE, FALSE, FALSE,FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
            ( FALSE, TRUE,  TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
            ( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
            ( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
            ( FALSE, FALSE, FALSE,FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
            ( FALSE, TRUE,  TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
            ( FALSE, FALSE, FALSE,FALSE, FALSE, FALSE, FALSE, FALSE, FALSE )  -- | - |
        );

        -------------------------------------------------------------------------------
        --State Table Declaration
        -------------------------------------------------------------------------------

	CONSTANT dfftab : VitalStateTableType := (
	-- D CLK R S lstSt Q
	( '-', '-', '0', '1', '-', '0' ),
	( '-', '-', '1', '0', '-', '1' ),
	( '1', '/', '1', '-', '-', '1' ),
	( '0', '/', '-', '1', '-', '0' ),
	( '1', '-', '1', '*', '1', '1' ),
	( '-', '0', '1', '*', '1', '1' ),
	( '-', '1', '1', '*', '1', '1' ),
	( '1', '-', '0', '\', '0', 'X' ),---
	( '-', '0', '0', '\', '0', 'X' ),---
	( '-', '1', '0', '\', '0', 'X' ),---
	( '0', '-', '*', '1', '0', '0' ),
	( '-', '0', '*', '1', '0', '0' ),
	( '-', '1', '*', '1', '0', '0' ),
	( '0', '-', '\', '0', '1', 'X' ),--
	( '-', '0', '\', '0', '1', 'X' ),--
	( '-', '1', '\', '0', '1', 'X' ),--
	( '1', 'R', '1', '1', '1', '1' ),
	( '0', 'R', '1', '1', '0', '0' ),
	( '-', '\', '-', '-', '-', 'S' ),
	( '-', 'v', '-', '-', '-', 'S' ),
	( '0', 'r', '-', '-', '0', 'S' ),
	( '0', 'f', '-', '-', '0', 'S' ),
	( '1', 'r', '-', '-', '1', 'S' ),
	( '1', 'f', '-', '-', '1', 'S' ),
	( '*', '1', '-', '-', '-', 'S' ),
	( '*', '0', '-', '-', '-', 'S' ),
	( 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'X', '-', 'S' ) );


        -------------------------------------------------------------------------------
        --State Table Declaration
        -------------------------------------------------------------------------------

	CONSTANT dff_1tab : VitalStateTableType := (
	-- D CLK R S lstSt Q
	( '-', '-', '0', '1', '-', '0' ),
	( '-', '-', '1', '0', '-', '1' ),
	( '1', '/', '1', '-', '-', '1' ),
	( '0', '/', '-', '1', '-', '0' ),
	( '1', '-', '1', '*', '1', '1' ),
	( '-', '1', '1', '*', '1', '1' ),
	( '-', '0', '1', '*', '1', '1' ),
	( '1', '-', '0', '\', '0', 'X' ),---
	( '-', '1', '0', '\', '0', 'X' ),---
	( '-', '0', '0', '\', '0', 'X' ),---
	( '0', '-', '*', '1', '0', '0' ),
	( '-', '1', '*', '1', '0', '0' ),
	( '-', '0', '*', '1', '0', '0' ),
	( '0', '-', '\', '0', '1', 'X' ),--
	( '-', '1', '\', '0', '1', 'X' ),--
	( '-', '0', '\', '0', '1', 'X' ),--
	( '1', 'F', '1', '1', '1', '1' ),
	( '0', 'F', '1', '1', '0', '0' ),
	( '-', '\', '-', '-', '-', 'S' ),
	( '-', 'v', '-', '-', '-', 'S' ),
	( '0', 'f', '-', '-', '0', 'S' ),
	( '0', 'r', '-', '-', '0', 'S' ),
	( '1', 'f', '-', '-', '1', 'S' ),
	( '1', 'r', '-', '-', '1', 'S' ),
	( '*', '0', '-', '-', '-', 'S' ),
	( '*', '1', '-', '-', '-', 'S' ),
	( 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'X', '-', 'S' ) );


	-------------------------------------------------------------------------------
	-------------------------------------------------------------------------------
	--State Table Declaration
	-------------------------------------------------------------------------------
	CONSTANT latchtab : VitalStateTableType := (
	-- D LAT R S lstSt Q
	( '-', '-', '0', '1', '-', '0' ),
	( '-', '-', '1', '0', '-', '1' ),
	( '*', '0', '1', '1', '-', 'S' ),
	( '-', '\', '1', '1', '-', 'S' ),
	( '-', 'v', '1', '1', '-', 'S' ),
	( '-', 'f', '1', '1', '-', 'S' ),
	( '0', '^', '-', '1', '-', '0' ),
	( '1', '^', '1', '-', '-', '1' ),
	( '0', 'r', '1', '1', '0', '0' ),
	( '1', 'r', '1', '1', '1', '1' ),
	( '\', '1', '-', '1', '-', '0' ),
	( 'v', '1', '-', '1', '-', '0' ),
	( '/', '1', '1', '-', '-', '1' ),
	( '^', '1', '1', '-', '-', '1' ),
	( '0', '/', '-', '1', '-', '0' ),
	( '1', '/', '1', '-', '-', '1' ),
	( '-', '0', '1', '/', '-', 'S' ),
	( '-', '0', '1', '^', '-', 'S' ),
	( '-', '0', '/', '1', '-', 'S' ),
	( '-', '0', '^', '1', '-', 'S' ),
	( '0', '1', '-', '/', '-', '0' ),
	( '0', '1', '-', '^', '-', '0' ),
	( '1', '1', '/', '-', '-', '1' ),
	( '1', '1', '^', '-', '-', '1' ),
	( '1', '1', '1', '/', '-', '1' ),
	( '1', '1', '1', '^', '-', '1' ),
	( '0', '1', '/', '1', '-', '0' ),
	( '0', '1', '^', '1', '-', '0' ),
	( '/', 'X', '1', '-', '1', '1' ),
	( '^', 'X', '1', '-', '1', '1' ),
	( '\', 'X', '-', '1', '0', '0' ),
	( 'v', 'X', '-', '1', '0', '0' ),
	( 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'X', '-', 'S' ) );


	-------------------------------------------------------------------------------
	--State Table Declaration
	-------------------------------------------------------------------------------
	CONSTANT jkfftab : VitalStateTableType := (
	-- CLK J K S R lstSt Q
	( '-', '-', '-', '0', '1', '-', '1' ),
	( '-', '-', '-', '1', '0', '-', '0' ),
	( '-', '-', '-', '*', '1', '1', '1' ),
	( '-', '-', '-', '1', '*', '0', '0' ),
	( '/', '0', '0', '1', '1', '-', 'S' ),
	( '/', '0', '1', '1', '1', '-', '0' ),
	( '/', '1', '0', '1', '1', '-', '1' ),
	( '/', '1', '1', '1', '1', '1', '0' ),
	( '/', '1', '1', '1', '1', '0', '1' ),
	( '\', '-', '-', '-', '-', '-', 'S' ),
	( 'B', '*', '-', '-', '-', '-', 'S' ),
	( 'B', '-', '*', '-', '-', '-', 'S' ),
	( 'R', '0', '0', '1', '1', '-', 'S' ),
	( 'R', '0', '-', '1', '-', '0', 'S' ),
	( 'R', '-', '0', '-', '1', '1', 'S' ),
	( 'v', '-', '-', '-', '-', '-', 'S' ),
	( 'f', '0', '0', '1', '1', '-', 'S' ),
	( 'f', '0', '-', '1', '-', '0', 'S' ),
	( 'f', '-', '0', '-', '1', '1', 'S' ),
	( 'X', '*', '0', '-', '1', '1', 'S' ),
	( 'X', '0', '*', '1', '-', '0', 'S' ),
	( 'S', 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'X', '-', 'S' ) );


	-------------------------------------------------------------------------------
	--State Table Declaration
	-------------------------------------------------------------------------------
	CONSTANT rsfftab : VitalStateTableType := (
	-- CLK RE SE S R lstSt Q
	( '-', '-', '-', '0', '1', '-', '1' ),
	( '-', '-', '-', '1', '0', '-', '0' ),
	( '-', '1', '1', '/', '1', '-', 'S' ),
	( '-', '1', '1', '^', '1', '-', 'S' ),
	( '-', '1', '1', '1', '/', '-', 'S' ),
	( '-', '1', '1', '1', '^', '-', 'S' ),
	( '/', '0', '0', '1', '1', '-', 'S' ),
	( '/', '0', '1', '1', '1', '-', '1' ),
	( '/', '1', '0', '1', '1', '-', '0' ),
	( '\', '-', '-', '-', '-', '-', 'S' ),
	( 'R', '0', '0', '1', '1', '-', 'S' ),
	( 'R', '0', '-', '1', '-', '0', 'S' ),
	( 'R', '-', '0', '-', '1', '1', 'S' ),
	( 'v', '-', '-', '-', '-', '-', 'S' ),
	( 'f', '0', '0', '1', '1', '-', 'S' ),
	( 'f', '0', '-', '1', '-', '0', 'S' ),
	( 'f', '-', '0', '-', '1', '1', 'S' ),
	( 'X', '*', '0', '-', '1', '1', 'S' ),
	( 'X', '0', '*', '1', '-', '0', 'S' ),
	( 'S', 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'S', '/', '-', 'S' ),----
	( 'S', 'S', 'S', '/', 'S', '-', 'S' ),----
	( 'S', 'S', 'S', 'S', 'r', '-', 'X' ),----
	( 'S', 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'X', '-', 'S' ),
	( '-', '*', '-', '1', '1', '-', 'S' ),
	( '-', '-', '*', '1', '1', '-', 'S' ));


	-------------------------------------------------------------------------------
	--State Table Declaration
	-------------------------------------------------------------------------------
	CONSTANT tfftab : VitalStateTableType := (
	-- CLK T S R lstSt Q
	( '-', '-', '0', '1', '-', '1' ),
	( '-', '-', '1', '0', '-', '0' ),
	( 'X', '0', '1', '-', '0', 'S' ),
	( '-', '-', '*', '1', '1', '1' ),
	( '-', '-', '1', '*', '0', '0' ),
	( '/', '0', '1', '1', '-', 'S' ),
	( '/', '1', '1', '1', '1', '0' ),
	( '/', '1', '1', '1', '0', '1' ),
	( '\', '-', '-', '-', '-', 'S' ),
	( 'B', '*', '-', '-', '-', 'S' ),
	( 'R', '0', '1', '1', '-', 'S' ),
	( 'R', '0', '1', '-', '0', 'S' ),
	( 'R', '0', '-', '1', '1', 'S' ),
	( 'v', '-', '-', '-', '-', 'S' ),
	( 'f', '0', '1', '1', '-', 'S' ),
	( 'f', '-', '-', '1', '1', 'S' ),
	( 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'X', '-', 'S' ) );


	-------------------------------------------------------------------------------
	--State Table Declaration
	-------------------------------------------------------------------------------
	CONSTANT dffcetab : VitalStateTableType := (
	-- D CLK R S CE lstSt Q
	( '-', '-', '0', '1', '-', '-', '0' ),
	( '-', '-', '1', '0', '-', '-', '1' ),
	( '-', '-', '1', '1', '0', '-', 'S' ),
	( '1', '/', '1', '-', '1', '-', '1' ),
	( '0', '/', '-', '1', '1', '-', '0' ),
	( '1', '-', '1', '*', '1', '1', '1' ),
	( '-', '0', '1', '*', '1', '1', '1' ),
	( '-', '1', '1', '*', '1', '1', '1' ),
	( '0', '-', '*', '1', '1', '0', '0' ),
	( '-', '0', '*', '1', '1', '0', '0' ),
	( '-', '1', '*', '1', '1', '0', '0' ),
	( '1', 'R', '1', '1', '1', '1', '1' ),
	( '0', 'R', '1', '1', '1', '0', '0' ),
	( '-', '\', '-', '-', '1', '-', 'S' ),
	( '-', 'v', '-', '-', '1', '-', 'S' ),
	( '0', 'r', '-', '-', '1', '0', 'S' ),
	( '0', 'f', '-', '-', '1', '0', 'S' ),
	( '1', 'r', '-', '-', '1', '1', 'S' ),
	( '1', 'f', '-', '-', '1', '1', 'S' ),
	( '*', '1', '-', '-', '1', '-', 'S' ),
	( '*', '0', '-', '-', '1', '-', 'S' ),
	( 'S', 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'S', '-', 'S' ),
--	( 'S', 'S', 'S', 'S', 'r', '-', 'X' ),
--	( 'S', 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'f', '-', 'X' ),
	( '-', '-', '1', '1', '*', '-', 'S' ),
	( 'X', 'X', 'X', 'X', 'X', '-', 'S' ) );



	-------------------------------------------------------------------------------
	--State Table Declaration
	-------------------------------------------------------------------------------
	CONSTANT dffcebtab : VitalStateTableType := (
	-- D CLK R S CE lstSt Q
	( '-', '-', '0', '1', '-', '-', '0' ),
	( '-', '-', '1', '0', '-', '-', '1' ),
	( '-', '-', '1', '1', '1', '-', 'S' ),
	( '1', '/', '1', '-', '0', '-', '1' ),
	( '0', '/', '-', '1', '0', '-', '0' ),
	( '1', '-', '1', '*', '0', '1', '1' ),
	( '-', '0', '1', '*', '0', '1', '1' ),
	( '-', '1', '1', '*', '0', '1', '1' ),
	( '0', '-', '*', '1', '0', '0', '0' ),
	( '-', '0', '*', '1', '0', '0', '0' ),
	( '-', '1', '*', '1', '0', '0', '0' ),
	( '1', 'R', '1', '1', '0', '1', '1' ),
	( '0', 'R', '1', '1', '0', '0', '0' ),
	( '-', '\', '-', '-', '0', '-', 'S' ),
	( '-', 'v', '-', '-', '0', '-', 'S' ),
	( '0', 'r', '-', '-', '0', '0', 'S' ),
	( '0', 'f', '-', '-', '0', '0', 'S' ),
	( '1', 'r', '-', '-', '0', '1', 'S' ),
	( '1', 'f', '-', '-', '0', '1', 'S' ),
	( '*', '1', '-', '-', '0', '-', 'S' ),
	( '*', '0', '-', '-', '0', '-', 'S' ),
	( 'S', 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'S', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'S', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'S', '-', 'S' ),
	( 'S', 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'S', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'S', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'S', '-', 'S' ),
	( 'S', 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'S', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'S', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'S', '-', 'S' ),
	( 'S', 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'S', 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'S', '-', 'S' ),
	( 'r', 'X', 'X', 'X', 'S', '-', 'X' ),
	( 'f', 'X', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'r', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'f', 'X', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'r', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'f', 'X', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'r', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'f', 'S', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'S', '-', 'S' ),
--	( 'S', 'S', 'S', 'S', 'f', '-', 'X' ),
--	( 'S', 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'S', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'S', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'r', '-', 'X' ),
	( 'X', 'X', 'X', 'S', 'X', '-', 'S' ),
	( 'S', 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'S', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'S', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'r', '-', 'X' ),
	( 'X', 'X', 'S', 'X', 'X', '-', 'S' ),
	( 'S', 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'S', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'S', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'r', '-', 'X' ),
	( 'X', 'S', 'X', 'X', 'X', '-', 'S' ),
	( 'S', 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'S', 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'r', '-', 'X' ),
	( 'S', 'X', 'X', 'X', 'X', '-', 'S' ),
	( 'r', 'X', 'X', 'X', 'X', '-', 'X' ),
	( 'f', 'X', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'r', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'f', 'X', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'r', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'f', 'X', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'r', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'f', 'X', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'f', '-', 'X' ),
	( 'X', 'X', 'X', 'X', 'r', '-', 'X' ),
	( '-', '-', '1', '1', '*', '-', 'S' ),
	( 'X', 'X', 'X', 'X', 'X', '-', 'S' ) );

end VLOGTOVITAL_TABLES;


--------- RAM_PACKAGE ------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synopsys translate_off

library IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
-- synopsys translate_on

package RAM_PACKAGE is

   SUBTYPE  data_word_typ_18        is std_logic_vector (17 downto 0);
   SUBTYPE  data_word_typ_9         is std_logic_vector (8 downto 0);
   SUBTYPE  address_type_8          is std_logic_vector (7 downto 0);
   SUBTYPE  address_type_9          is std_logic_vector (8 downto 0);
   TYPE     memory_array_typ_256    is array(0 to 255) of data_word_typ_18;
   TYPE     memory_array_typ_512    is array(0 to 511) of data_word_typ_9;

   CONSTANT x_data_18  : data_word_typ_18  := "XXXXXXXXXXXXXXXXXX";
   CONSTANT z_data_18  : data_word_typ_18  := "ZZZZZZZZZZZZZZZZZZ";
   CONSTANT x_add_8    : address_type_8    := "XXXXXXXX";

   CONSTANT x_data_9  : data_word_typ_9    := "XXXXXXXXX";
   CONSTANT z_data_9  : data_word_typ_9    := "ZZZZZZZZZ";
   CONSTANT x_add_9    : address_type_9    := "XXXXXXXXX";

   function VEC2INT	(v : std_logic_vector)	return integer;
   function BITX	(v : std_logic)		return boolean;
   function VECX	(v : std_logic_vector)	return boolean;

   function FillInit256	(v : std_logic_vector)	return memory_array_typ_256;
   function FillInit512	(v : std_logic_vector)	return memory_array_typ_512;

   CONSTANT L : VitalTableSymbolType := '0';
   CONSTANT H : VitalTableSymbolType := '1';
   CONSTANT x : VitalTableSymbolType := '-';
   CONSTANT S : VitalTableSymbolType := 'S';
   CONSTANT U : VitalTableSymbolType := 'X';

   CONSTANT RAM_RDATA_tab : VitalStateTableType := (
    ( L,  H,  x,  L ),
    ( H,  H,  x,  H ),
    ( x,  L,  x,  S ));
 
   CONSTANT RAMS_RDATA_tab : VitalStateTableType := (
    ( L,  L,  L,  x,  H,  x,  L ),
    ( L,  L,  x,  H,  H,  x,  L ),
    ( L,  H,  H,  x,  H,  x,  H ),
    ( L,  H,  x,  H,  H,  x,  H ),
    ( L,  x,  L,  L,  H,  x,  L ),
    ( L,  x,  H,  L,  H,  x,  H ),
    ( H,  x,  x,  x,  x,  x,  S ),
    ( x,  x,  x,  x,  L,  x,  S ));

   CONSTANT RAMS_RDATA_tab_H : VitalStateTableType := (
    ( H,  L,  L,  x,  L,  x,  L ),
    ( H,  L,  x,  H,  L,  x,  L ),
    ( H,  H,  H,  x,  L,  x,  H ),
    ( H,  H,  x,  H,  L,  x,  H ),
    ( H,  x,  L,  L,  L,  x,  L ),
    ( H,  x,  H,  L,  L,  x,  H ),
    ( L,  x,  x,  x,  x,  x,  S ),
    ( x,  x,  x,  x,  H,  x,  S ));

  function ADDR4_TO_INT (
      ADDRESS : in std_logic_vector(3 downto 0)
  ) return integer;
 
  function ADDR5_TO_INT (
      ADDRESS : in std_logic_vector(4 downto 0)
  ) return integer;

  function ADDR6_TO_INT (
      ADDRESS : in std_logic_vector(5 downto 0)
  ) return integer;
 
end RAM_PACKAGE;

-----------------------------------------------------------------------------
 
package body RAM_PACKAGE is
 
  function ADDR4_TO_INT (
      ADDRESS : in std_logic_vector(3 downto 0)
  ) return integer is
 
  variable I : integer;
 
  begin
    case ADDRESS is
      when "0000"  =>  I := 0;
      when "0001"  =>  I := 1;
      when "0010"  =>  I := 2;
      when "0011"  =>  I := 3;
      when "0100"  =>  I := 4;
      when "0101"  =>  I := 5;
      when "0110"  =>  I := 6;
      when "0111"  =>  I := 7;
      when "1000"  =>  I := 8;
      when "1001"  =>  I := 9;
      when "1010"  =>  I := 10;
      when "1011"  =>  I := 11;
      when "1100"  =>  I := 12;
      when "1101"  =>  I := 13;
      when "1110"  =>  I := 14;
      when "1111"  =>  I := 15;
      when others  =>  I := 0;
    end case;
    return I;
  end ADDR4_TO_INT;

  function ADDR5_TO_INT (
      ADDRESS : in std_logic_vector(4 downto 0)
  ) return integer is
 
  variable I : integer;
 
  begin
    case ADDRESS is
      when "00000"  =>  I := 0;
      when "00001"  =>  I := 1;
      when "00010"  =>  I := 2;
      when "00011"  =>  I := 3;
      when "00100"  =>  I := 4;
      when "00101"  =>  I := 5;
      when "00110"  =>  I := 6;
      when "00111"  =>  I := 7;
      when "01000"  =>  I := 8;
      when "01001"  =>  I := 9;
      when "01010"  =>  I := 10;
      when "01011"  =>  I := 11;
      when "01100"  =>  I := 12;
      when "01101"  =>  I := 13;
      when "01110"  =>  I := 14;
      when "01111"  =>  I := 15;
      when "10000"  =>  I := 16;
      when "10001"  =>  I := 17;
      when "10010"  =>  I := 18;
      when "10011"  =>  I := 19;
      when "10100"  =>  I := 20;
      when "10101"  =>  I := 21;
      when "10110"  =>  I := 22;
      when "10111"  =>  I := 23;
      when "11000"  =>  I := 24;
      when "11001"  =>  I := 25;
      when "11010"  =>  I := 26;
      when "11011"  =>  I := 27;
      when "11100"  =>  I := 28;
      when "11101"  =>  I := 29;
      when "11110"  =>  I := 30;
      when "11111"  =>  I := 31;
      when others   =>  I := 0;
    end case;
    return I;
  end ADDR5_TO_INT;

  function ADDR6_TO_INT (
      ADDRESS : in std_logic_vector(5 downto 0)
  ) return integer is
 
  variable I : integer;
 
  begin
    case ADDRESS is
      when "000000"  =>  I := 0;
      when "000001"  =>  I := 1;
      when "000010"  =>  I := 2;
      when "000011"  =>  I := 3;
      when "000100"  =>  I := 4;
      when "000101"  =>  I := 5;
      when "000110"  =>  I := 6;
      when "000111"  =>  I := 7;
      when "001000"  =>  I := 8;
      when "001001"  =>  I := 9;
      when "001010"  =>  I := 10;
      when "001011"  =>  I := 11;
      when "001100"  =>  I := 12;
      when "001101"  =>  I := 13;
      when "001110"  =>  I := 14;
      when "001111"  =>  I := 15;
      when "010000"  =>  I := 16;
      when "010001"  =>  I := 17;
      when "010010"  =>  I := 18;
      when "010011"  =>  I := 19;
      when "010100"  =>  I := 20;
      when "010101"  =>  I := 21;
      when "010110"  =>  I := 22;
      when "010111"  =>  I := 23;
      when "011000"  =>  I := 24;
      when "011001"  =>  I := 25;
      when "011010"  =>  I := 26;
      when "011011"  =>  I := 27;
      when "011100"  =>  I := 28;
      when "011101"  =>  I := 29;
      when "011110"  =>  I := 30;
      when "011111"  =>  I := 31;
      when "100000"  =>  I := 32;
      when "100001"  =>  I := 33;
      when "100010"  =>  I := 34;
      when "100011"  =>  I := 35;
      when "100100"  =>  I := 36;
      when "100101"  =>  I := 37;
      when "100110"  =>  I := 38;
      when "100111"  =>  I := 39;
      when "101000"  =>  I := 40;
      when "101001"  =>  I := 41;
      when "101010"  =>  I := 42;
      when "101011"  =>  I := 43;
      when "101100"  =>  I := 44;
      when "101101"  =>  I := 45;
      when "101110"  =>  I := 46;
      when "101111"  =>  I := 47;
      when "110000"  =>  I := 48;
      when "110001"  =>  I := 49;
      when "110010"  =>  I := 50;
      when "110011"  =>  I := 51;
      when "110100"  =>  I := 52;
      when "110101"  =>  I := 53;
      when "110110"  =>  I := 54;
      when "110111"  =>  I := 55;
      when "111000"  =>  I := 56;
      when "111001"  =>  I := 57;
      when "111010"  =>  I := 58;
      when "111011"  =>  I := 59;
      when "111100"  =>  I := 60;
      when "111101"  =>  I := 61;
      when "111110"  =>  I := 62;
      when "111111"  =>  I := 63;
      when others   =>  I := 0;
    end case;
    return I;
  end ADDR6_TO_INT;

  function FillInit256	(v : std_logic_vector)	return memory_array_typ_256 is
         variable  mem_slice : data_word_typ_18;
         variable  memory_a  : memory_array_typ_256;
      begin

      for I in 0 to 255 loop
         --  mem_slice   := v(i) & v(256+i) & v(2*256+i) & v(3*256+i) &
         --                 v(4*256+i) & v(5*256+i) & v(6*256+i) & v(7*256+i) &
         --                 v(8*256+i) & v(9*256+i) & v(10*256+i) & v(11*256+i) &
         --                 v(12*256+i) & v(13*256+i) & v(14*256+i) & v(15*256+i) &
         --                 v(16*256+i) & v(17*256+i); 
         --  mem_slice   := v(17*256+i) & v(16*256+i) & v(15*256+i) & v(14*256+i) &
         --                 v(13*256+i) & v(12*256+i) & v(11*256+i) & v(10*256+i) &
         --                 v(9*256+i) & v(8*256+i) & v(7*256+i) & v(6*256+i) &
         --                 v(5*256+i) & v(4*256+i) & v(3*256+i) & v(2*256+i) &
         --                 v(1*256+i) & v(i); 
           mem_slice   := v(255-i) & v(256+255-i) & v(2*256+255-i) & v(3*256+255-i) &
                          v(4*256+255-i) & v(5*256+255-i) & v(6*256+255-i) & v(7*256+255-i) &
                          v(8*256+255-i) & v(9*256+255-i) & v(10*256+255-i) & v(11*256+255-i) &
                          v(12*256+255-i) & v(13*256+255-i) & v(14*256+255-i) & v(15*256+255-i) &
                          v(16*256+255-i) & v(17*256+255-i); 
           memory_a(i) := mem_slice;
      end loop;
           return memory_a;
  end FillInit256;

  function FillInit512	(v : std_logic_vector)	return memory_array_typ_512 is
         variable  mem_slice : data_word_typ_9;
         variable  memory_a  : memory_array_typ_512;
      begin

      for I in 0 to 511 loop
           --mem_slice   := v(i) & v(512+i) & v(2*512+i) & v(3*512+i) &
           --               v(4*512+i) & v(5*512+i) & v(6*512+i) & v(7*512+i) &
           --               v(8*512+i); 
           --mem_slice   := v(8*512+i) & v(7*512+i) & v(6*512+i) & v(5*512+i) &
           --               v(4*512+i) & v(3*512+i) & v(2*512+i) & v(1*512+i) &
           --               v(i); 
           mem_slice   := v(511-i) & v(512+511-i) & v(2*512+511-i) & v(3*512+511-i) &
                          v(4*512+511-i) & v(5*512+511-i) & v(6*512+511-i) & v(7*512+511-i) &
                          v(8*512+511-i); 
           memory_a(i) := mem_slice;
      end loop;
           return memory_a;
  end FillInit512;

  function VEC2INT           (v: std_logic_vector) return integer is
      variable result: integer := 0;
      variable addition: integer := 1;
   begin
      for b in v'reverse_range loop
         if v (b) = '1' then
            result := result + addition;
         end if;
         addition := addition * 2;
      end loop;
      return result;
   end VEC2INT;

   function VECX              (v: std_logic_vector) return boolean is
   begin
      for b in v'range loop
         if bitX (v (b)) then
            return true;
         end if;
      end loop;
      return false;
   end VECX;

   function BITX              (v: std_logic) return boolean is
   begin
      case v is
         when 'X'    => return true;
         when others => return false;
      end case;
   end BITX;

end RAM_PACKAGE;
--------------------------end RAM_PACKAGE----------------------------------
----- VITAL model for cell B_KEEPER -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;

entity B_KEEPER is
  generic( InstancePath: STRING := "*");
  port(X : inout STD_ULOGIC);
  attribute VITAL_LEVEL0 of B_KEEPER : entity is TRUE;
end B_KEEPER;

architecture VITAL of B_KEEPER is

   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

   signal X_ipd : std_ulogic := 'L';

begin

   process (X)
   begin
       if (X'event) then
           if (X = '1') then
               X_ipd <= 'H';
           elsif (X = '0') then
               X_ipd <= 'L';
           end if;
       end if;
   end process;
 
   X <= X_ipd;

end VITAL;

configuration CFG_VITAL of B_KEEPER is
   for VITAL
   end for;
end CFG_VITAL;

----- VITAL model for cell SPLL -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity SPLL is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      IN_FREQ: STRING := "100.0";
      CLK_OUT_TO_PIN: STRING := "OFF";
      WAKE_ON_LOCK: STRING := "OFF";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_IN_CLK_OUT             :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tipd_CLK_IN                    :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CLK_IN                         :	in    STD_ULOGIC;
      CLK_OUT                        :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of SPLL : entity is FALSE;
end SPLL;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of SPLL is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL CLK_IN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CLK_IN_ipd, CLK_IN, tipd_CLK_IN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_IN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(CLK_IN_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => CLK_OUT,
       GlitchData => O_GlitchData,
       OutSignalName => "CLK_OUT",
       OutTemp => O_zd,
       Paths => (0 => (CLK_IN_ipd'last_event, tpd_CLK_IN_CLK_OUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_SPLL_VITAL of SPLL is 
        for VITAL
        end for; 
end CFG_SPLL_VITAL;

----- VITAL model for cell STDPLL -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library LAVA1;
use LAVA1.components.all;

-- entity declaration --
entity STDPLL is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "1";
      DIV      : string  := "1";
      POST     : string  := "1";
      SECDIV   : string  := "1";
      lock_cyc : integer := 2;
      PLL_DLY  : string  := "1";
      CLK_OUT_TO_PIN  : string  := "OFF";
      WAKE_ON_LOCK  : string  := "OFF";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_IN_CLK_OUT             :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tpd_CLK_IN_PLL_LOCK             :	VitalDelayType01 := (0.00 ns, 0.00 ns);
      tipd_CLK_IN             :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      CLK_IN                         :	in    STD_ULOGIC;
      CLK_OUT                        :	out   STD_ULOGIC;
      PLL_LOCK                       :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of STDPLL : entity is FALSE;
end STDPLL;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
use LAVA1.components.all;
architecture VITAL of STDPLL is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL CLK_IN_ipd	 : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL clklock_half_period1 : TIME :=100 ns;
  SIGNAL clklock_half_period0 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly1 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly0 : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_falling_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;

  SIGNAL clock_count : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_start  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';
  CONSTANT clockboost: integer := str2int(mult) / str2int(div);
  CONSTANT tpd: time := 0.25 ns * str2real(pll_dly);

BEGIN

   WireDelay : block
   begin
   VitalWireDelay (CLK_IN_ipd, CLK_IN, tipd_CLK_IN);
   end block;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN
       clklock_half_period <= (clklock_half_period0 + clklock_half_period1)/2;

  WAIT UNTIL (CLK_IN_ipd'EVENT AND CLK_IN_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     IF clklock_rising_edge_count = 0 THEN
        clklock_last_rising_edge <= NOW;	
	start_inclk <= CLK_IN_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
       clklock_half_period0 <= (NOW - clklock_last_falling_edge)* real(str2int(div))/real(str2int(mult));
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
       clklock_half_period_minus_dly0 <= (NOW - clklock_last_falling_edge) + tpd;
     END IF;
     END IF;
 
  WAIT UNTIL (CLK_IN_ipd'EVENT AND CLK_IN_ipd='0');
     clklock_falling_edge_count <= clklock_falling_edge_count +1;	  	
     IF clklock_falling_edge_count = 0 THEN	
	clklock_last_falling_edge <= NOW;
	clklock_half_period1 <= (NOW - clklock_last_rising_edge)* real(str2int(div))/real(str2int(mult)); 
     ELSIF clklock_falling_edge_count = 1 THEN
        clklock_half_period_minus_dly1 <= (NOW - clklock_last_rising_edge) + tpd;
     END IF;
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc + 1 THEN
        if(clockboost >1) then
	   FOR i IN 1 TO (2*clockboost) LOOP 	          
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	END LOOP;
      else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
      end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
end process;

process
begin
   wait until CLK_OUT_sig_d_start = '1'; LOOP
     wait for clklock_half_period1;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not;
     wait for clklock_half_period0;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not ;
   END LOOP;
end process;

process(clklock_falling_edge_count)
begin
   if (clklock_falling_edge_count >= lock_cyc + 1) then
       CLK_OUT_start <= '1' after clklock_half_period_minus_dly0;
   end if;
end process;

process
begin
   wait until  CLK_OUT_start = '1'; LOOP
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d;
     wait for clklock_half_period1;
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d ;
     wait for clklock_half_period0;
     END LOOP;
end process;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    CLK_OUT <= CLK_OUT_plus_delay;

    PLL_LOCK <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus;
               


end VITAL;

configuration CFG_STDPLL_VITAL of STDPLL is 
        for VITAL
        end for; 
end CFG_STDPLL_VITAL;

----- VITAL model for cell STDPLLX -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library LAVA1;
use LAVA1.components.all;

-- entity declaration --
entity STDPLLX is
   generic(
      IN_FREQ  : string  := "100.0";
      CLK_OUT_TO_PIN  : string  := "OFF";
      WAKE_ON_LOCK  : string  := "OFF";
      PLL_FBK_ATTRIBUTE : string := "CLKTREE";
      MULT     : string  := "1";
      DIV      : string  := "1";
      POST     : string  := "1";
      LOCK_CYC : integer := 2;
      SECDIV   : string   := "1";
      PLL_DLY  : string  := "1";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_PLL_RST_PLL_LOCK :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_IN_CLK_OUT :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_IN_PLL_LOCK :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_CLK_IN_SEC_OUT :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_CLK_IN    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_PLL_FBK   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_PLL_RST   :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      CLK_IN            : in    STD_ULOGIC;
      PLL_FBK           : in    STD_ULOGIC;
      PLL_RST           : in    STD_ULOGIC := '0';
      CLK_OUT           : out   STD_ULOGIC;
      SEC_OUT           : out   STD_ULOGIC;
      PLL_LOCK          : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of STDPLLX : entity is FALSE;
end STDPLLX;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
use LAVA1.components.all;


architecture VITAL of STDPLLX is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL CLK_IN_ipd	 : STD_ULOGIC := 'X';
  SIGNAL PLL_RST_ipd	 : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL clklock_half_period1 : TIME :=100 ns;
  SIGNAL clklock_half_period0 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly1 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly0 : TIME :=100 ns;
  SIGNAL secd_delay_minus1 : TIME :=100 ns;
  SIGNAL secd_delay_minus0 : TIME :=100 ns;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_falling_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;

  SIGNAL clock_count : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  CONSTANT secdiv_p: integer := str2int(secdiv);
  CONSTANT clockboost: integer := str2int(mult) / str2int(div);
  CONSTANT tpd: time := 0.25 ns * str2int(pll_dly);
  SIGNAL  PLL_RST_int  : STD_LOGIC;

BEGIN
   PLL_RST_int <= PLL_RST_ipd WHEN (PLL_RST_ipd = '0' or PLL_RST_ipd = '1') else
                  '0';
   WireDelay : block
   begin
   VitalWireDelay (CLK_IN_ipd, CLK_IN, tipd_CLK_IN);
   VitalWireDelay (PLL_RST_ipd, PLL_RST, tipd_PLL_RST);
   end block;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN
       clklock_half_period <= (clklock_half_period0 + clklock_half_period1)/2;

   WAIT UNTIL (CLK_IN_ipd'EVENT AND CLK_IN_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     IF clklock_rising_edge_count = 0 THEN
        clklock_last_rising_edge <= NOW;	
	start_inclk <= CLK_IN_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
       clklock_half_period0 <= (NOW - clklock_last_falling_edge)* real(str2int(div))/real(str2int(mult));
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
       clklock_half_period_minus_dly0 <= (NOW - clklock_last_falling_edge) + tpd;
        secd_delay_minus0 <= clklock_half_period0 * secdiv_p + tpd;
     END IF;
     END IF;
 
   WAIT UNTIL (CLK_IN_ipd'EVENT AND CLK_IN_ipd='0');
     clklock_falling_edge_count <= clklock_falling_edge_count +1;	  	
     IF clklock_falling_edge_count = 0 THEN	
	clklock_last_falling_edge <= NOW;
	clklock_half_period1 <= (NOW - clklock_last_rising_edge)* real(str2int(div))/real(str2int(mult)); 
     ELSIF clklock_falling_edge_count = 1 THEN
        clklock_half_period_minus_dly1 <= (NOW - clklock_last_rising_edge) + tpd;
        secd_delay_minus1 <= clklock_half_period1 * secdiv_p + tpd;
     END IF;
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc + 1 and PLL_RST_int ='0' THEN
         if(clockboost >1) then
	   FOR i IN 1 TO (2*clockboost) LOOP 	        
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

process
begin
    wait until CLK_OUT_sig_d_start = '1'; LOOP
     wait for clklock_half_period1;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not;
     wait for clklock_half_period0;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not ;
   END LOOP;
end process;

process(clklock_falling_edge_count)
begin
   if (clklock_falling_edge_count >= lock_cyc + 1 and PLL_RST_int = '0') then
       CLK_OUT_start <= '1' after clklock_half_period_minus_dly0;
   end if;
end process;

process
begin
   wait until  CLK_OUT_start = '1'; LOOP
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d;
     wait for clklock_half_period1;
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d ;
     wait for clklock_half_period0;
     END LOOP;
end process;

process
begin
   wait until SEC_OUT_sig_d_start = '1'; LOOP
     wait for clklock_half_period1 * secdiv_p;
   SEC_OUT_sig_d_not <= not SEC_OUT_sig_d_not;
     wait for clklock_half_period0 * secdiv_p;
   SEC_OUT_sig_d_not <= not SEC_OUT_sig_d_not ;
   END LOOP;
end process;

process(clklock_falling_edge_count)
begin
   if(clklock_falling_edge_count >= lock_cyc + 1 and PLL_RST_int = '0') then
        SEC_OUT_start <= '1' after clklock_half_period_minus_dly0;
   end if;
end process;

process
begin
   wait until  SEC_OUT_start = '1'; LOOP
      SEC_OUT_sig_3d <= not SEC_OUT_sig_3d;
     wait for clklock_half_period1 * secdiv_p;
      SEC_OUT_sig_3d <= not SEC_OUT_sig_3d ;
     wait for clklock_half_period0 * secdiv_p;
     END LOOP;
end process;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    CLK_OUT <= CLK_OUT_plus_delay and not PLL_RST_int;

    PLL_LOCK <= PLL_LOCK_plus and not PLL_RST_int when tpd >= 0 ns else
                PLL_LOCK_minus and  not PLL_RST_int;

    SEC_OUT_sig_d <= SEC_OUT_sig_d_start and not SEC_OUT_sig_d_not; 

    SEC_OUT_plus_delay <= SEC_OUT_sig_d after tpd when tpd >= 0 ns else
                          SEC_OUT_sig_3d; 

    SEC_OUT <= SEC_OUT_plus_delay and not PLL_RST_int;

end VITAL;

configuration CFG_STDPLLX_VITAL of STDPLLX is 
        for VITAL
        end for; 
end CFG_STDPLLX_VITAL;

----- VITAL model for cell DFF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;

-- entity declaration --
entity DFF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      R_DELAY : TIME := 2 ns;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge    :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge     :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge            :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge                :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFF : entity is TRUE;
end DFF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFF is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R              : STD_ULOGIC := '0';

begin

   R <= '1' after R_DELAY; 

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_posedge,
          TimingData              => Tmkr_D_CLK_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/DFF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_posedge or Pviol_CLK;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_CLK_dly, CLK_dly, R,'1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFF_VITAL of DFF is 
        for VITAL
        end for; 
end CFG_DFF_VITAL;


----- VITAL model for cell DFF_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFF_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      R_DELAY : TIME := 2 ns;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_negedge    :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_negedge     :	VitalDelayType := 0.000 ns;
      tperiod_CLK_negedge            :	VitalDelayType := 0.000 ns;
      tpw_CLK_negedge                :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFF_1 : entity is TRUE;
end DFF_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFF_1 is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R              : STD_ULOGIC := '0';

begin

   R <= '1' after R_DELAY;  

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE CLK_inverted : STD_ULOGIC := 'X';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_negedge,
          TimingData              => Tmkr_D_CLK_negedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_negedge,
          SetupLow                => tsetup_D_CLK_noedge_negedge,
          HoldHigh                => thold_D_CLK_noedge_negedge,
          HoldLow                 => thold_D_CLK_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_negedge,
          PulseWidthHigh          => tpw_CLK_negedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/DFF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------

      CLK_inverted := (NOT CLK_dly);
      Violation := Tviol_D_CLK_negedge or Pviol_CLK;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_CLK_dly, CLK_inverted, R,'1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFF_1_VITAL of DFF_1 is 
        for VITAL
        end for; 
end CFG_DFF_1_VITAL;


----- VITAL model for cell DFFCB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      R_DELAY : TIME := 2 ns;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.010 ns, 0.010 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      thold_CE_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge        :	VitalDelayType := 4.400 ns;
      tperiod_CLK_posedge            :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCB : entity is TRUE;
end DFFCB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCB is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R              : STD_ULOGIC := '0';

begin

   R <= '1' after R_DELAY; 

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCB",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_posedge,
          TimingData              => Tmkr_CE_CLK_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_posedge,
          SetupLow                => tsetup_CE_CLK_noedge_posedge,
          HoldHigh                => thold_CE_CLK_noedge_posedge,
          HoldLow                 => thold_CE_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCB",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1,
          PeriodData              => PInfo_CLK_CE_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          HeaderMsg               => InstancePath & "/DFFCB",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_posedge or Tviol_CE_CLK_posedge or Pviol_CLK_CE_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_CLK_dly, CLK_dly, R,'1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCB_VITAL of DFFCB is 
        for VITAL
        end for; 
end CFG_DFFCB_VITAL;



----- VITAL model for cell DFFCB_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCB_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      R_DELAY : TIME := 2 ns;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_negedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_negedge :	VitalDelayType := 0.000 ns;
      thold_CE_CLK_noedge_negedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_negedge        :	VitalDelayType := 0.000 ns;
      tperiod_CLK_negedge            :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCB_1 : entity is TRUE;
end DFFCB_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCB_1 is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R              : STD_ULOGIC := '0';

begin

   R <= '1' after R_DELAY; 

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   VARIABLE CLK_inverted : STD_ULOGIC := 'X';
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_negedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_negedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_negedge,
          SetupLow                => tsetup_D_CLK_noedge_negedge,
          HoldHigh                => thold_D_CLK_noedge_negedge,
          HoldLow                 => thold_D_CLK_noedge_negedge,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCB_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_negedge,
          TimingData              => Tmkr_CE_CLK_negedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_negedge,
          SetupLow                => tsetup_CE_CLK_noedge_negedge,
          HoldHigh                => thold_CE_CLK_noedge_negedge,
          HoldLow                 => thold_CE_CLK_noedge_negedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCB_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1,
          PeriodData              => PInfo_CLK_CE_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_negedge,
          PulseWidthHigh          => tpw_CLK_negedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          HeaderMsg               => InstancePath & "/DFFCB_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      CLK_inverted := (NOT CLK_dly);
      Violation := Tviol_D_CLK_CE_EQ_1_negedge or Tviol_CE_CLK_negedge or Pviol_CLK_CE_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_CLK_dly, CLK_inverted, R, '1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCB_1_VITAL of DFFCB_1 is 
        for VITAL
        end for; 
end CFG_DFFCB_1_VITAL;

----- VITAL model for cell DFFCBR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCBR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_CE_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge :	VitalDelayType := 0.000 ns;
      trecovery_R_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCBR : entity is TRUE;
end DFFCBR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCBR is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, R_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_ANB_R_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1_ANB_R_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1_ANB_R_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_ANB_R_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01((R_CLK_dly) AND NOT (CE_ipd)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_posedge,
          TimingData              => Tmkr_CE_CLK_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_posedge_posedge,
          SetupLow                => tsetup_CE_CLK_posedge_posedge,
          HoldHigh                => thold_CE_CLK_posedge_posedge,
          HoldLow                 => thold_CE_CLK_posedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_R_CLK_CE_EQ_1_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_posedge_posedge,
          Removal                 => thold_R_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1_ANB_R_EQ_1,
          PeriodData              => PInfo_CLK_CE_EQ_1_ANB_R_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01((R_CLK_dly) AND NOT (CE_ipd)) = '1',
          HeaderMsg               => InstancePath & "/DFFCBR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_1_posedge or Tviol_CE_CLK_posedge or Tviol_R_CLK_CE_EQ_1_posedge or Pviol_CLK_CE_EQ_1_ANB_R_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_CLK_dly, CLK_dly,R_CLK_dly,'1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCBR_VITAL of DFFCBR is 
        for VITAL
        end for; 
end CFG_DFFCBR_VITAL;

----- VITAL model for cell DFFCBRH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCBRH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_CE_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge 		:	VitalDelayType := 0.000 ns;
      tpw_R_posedge 		:	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge :	VitalDelayType := 0.000 ns;
      trecovery_R_CLK_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_negedge_posedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCBRH : entity is TRUE;
end DFFCBRH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCBRH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd		 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, R_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_ANB_R_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1_ANB_R_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_R				: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1_ANB_R_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R				: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE R_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_0_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_ANB_R_EQ_0_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(((NOT R_CLK_dly)) AND NOT (CE_ipd)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_posedge,
          TimingData              => Tmkr_CE_CLK_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_posedge,
          SetupLow                => tsetup_CE_CLK_noedge_posedge,
          HoldHigh                => thold_CE_CLK_noedge_posedge,
          HoldLow                 => thold_CE_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_R_CLK_CE_EQ_1_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_negedge_posedge,
          Removal                 => thold_R_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_R_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/DFFCBRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1_ANB_R_EQ_0,
          PeriodData              => PInfo_CLK_CE_EQ_1_ANB_R_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(((NOT R_CLK_dly)) AND NOT (CE_ipd)) = '1',
          HeaderMsg               => InstancePath & "/DFFCBRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_0_posedge or Tviol_CE_CLK_posedge or Tviol_R_CLK_CE_EQ_1_posedge or Pviol_CLK_CE_EQ_1_ANB_R_EQ_0 or Pviol_R;
      R_inverted := (NOT R_CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_CLK_dly, CLK_dly,R_inverted,'1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCBRH_VITAL of DFFCBRH is 
        for VITAL
        end for; 
end CFG_DFFCBRH_VITAL;


----- VITAL model for cell DFFCBRH_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCBRH_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_negedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_CE_CLK_noedge_negedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_negedge 		:	VitalDelayType := 0.000 ns;
      tpw_R_negedge 		:	VitalDelayType := 0.000 ns;
      tperiod_CLK_negedge :	VitalDelayType := 0.000 ns;
      trecovery_R_CLK_negedge_negedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_negedge_negedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCBRH_1 : entity is TRUE;
end DFFCBRH_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCBRH_1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, R_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_0_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_ANB_R_EQ_0_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_CE_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_CE_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1_ANB_R_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_R				: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1_ANB_R_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R				: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE R_inverted : STD_ULOGIC := 'X';
   VARIABLE CLK_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_0_negedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_ANB_R_EQ_0_negedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_negedge,
          SetupLow                => tsetup_D_CLK_noedge_negedge,
          HoldHigh                => thold_D_CLK_noedge_negedge,
          HoldLow                 => thold_D_CLK_noedge_negedge,
          CheckEnabled            => TO_X01(((NOT R_CLK_dly)) AND NOT (CE_ipd)) = '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_negedge,
          TimingData              => Tmkr_CE_CLK_negedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_negedge,
          SetupLow                => tsetup_CE_CLK_noedge_negedge,
          HoldHigh                => thold_CE_CLK_noedge_negedge,
          HoldLow                 => thold_CE_CLK_noedge_negedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_CE_EQ_1_negedge,
          TimingData              => Tmkr_R_CLK_CE_EQ_1_negedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_negedge_negedge,
          Removal                 => thold_R_CLK_negedge_negedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_R_negedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath & "/DFFCBRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1_ANB_R_EQ_0,
          PeriodData              => PInfo_CLK_CE_EQ_1_ANB_R_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_negedge,
          PulseWidthHigh          => tpw_CLK_negedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(((NOT R_CLK_dly)) AND NOT (CE_ipd)) = '1',
          HeaderMsg               => InstancePath & "/DFFCBRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_0_negedge or Tviol_CE_CLK_negedge or Tviol_R_CLK_CE_EQ_1_negedge or Pviol_CLK_CE_EQ_1_ANB_R_EQ_0 or Pviol_R;
      R_inverted := (NOT R_CLK_dly);
      CLK_inverted := (NOT CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_CLK_dly, CLK_inverted,R_inverted,'1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCBRH_1_VITAL of DFFCBRH_1 is 
        for VITAL
        end for; 
end CFG_DFFCBRH_1_VITAL;


----- VITAL model for cell DFFCBSRH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCBSRH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge    :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge     :	VitalDelayType := 0.000 ns;
      tsetup_SR_CLK_noedge_posedge   :	VitalDelayType := 0.100 ns;
      thold_SR_CLK_noedge_posedge    :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_posedge   :  VitalDelayType := 0.100 ns;
      thold_CE_CLK_noedge_posedge    :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge            :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge                :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_SR_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SR                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CE                             :	in    STD_ULOGIC;
      SR                             :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCBSRH : entity is TRUE;
end DFFCBSRH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCBSRH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	         : STD_ULOGIC := 'X';
   SIGNAL SR_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL SR_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SR_ipd, SR, tipd_SR);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (SR_CLK_dly, SR_ipd, tisd_SR_CLK);

   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, SR_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_SR_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_SR_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE D_in_zd : STD_ULOGIC := '0';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(CE_ipd) ='0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBSRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_SR_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_SR_CLK_CE_EQ_1_posedge,
          TestSignal              => SR_CLK_dly,
          TestSignalName          => "SR",
          TestDelay               => tisd_SR_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_SR_CLK_noedge_posedge,
          SetupLow                => tsetup_SR_CLK_noedge_posedge,
          HoldHigh                => thold_SR_CLK_noedge_posedge,
          HoldLow                 => thold_SR_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(CE_ipd) ='0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBSRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_posedge,
          TimingData              => Tmkr_CE_CLK_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_posedge,
          SetupLow                => tsetup_CE_CLK_noedge_posedge,
          HoldHigh                => thold_CE_CLK_noedge_posedge,
          HoldLow                 => thold_CE_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBSRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1,
          PeriodData              => PInfo_CLK_CE_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(CE_ipd) ='0',
          HeaderMsg               => InstancePath &"/DFFCBSRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      D_in_zd := VitalAND2(NOT(SR_CLK_dly) ,  D_CLK_dly);
      Violation := Tviol_D_CLK_CE_EQ_1_posedge or Tviol_CE_CLK_posedge or Pviol_CLK_CE_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_in_zd, CLK_dly, '1','1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCBSRH_VITAL of DFFCBSRH is 
        for VITAL
        end for; 
end CFG_DFFCBSRH_VITAL;

----- VITAL model for cell DFFCBSRH_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCBSRH_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_negedge    :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_negedge     :	VitalDelayType := 0.000 ns;
      tsetup_SR_CLK_noedge_negedge   :	VitalDelayType := 0.100 ns;
      thold_SR_CLK_noedge_negedge    :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_negedge   :VitalDelayType := 0.100 ns;
      thold_CE_CLK_noedge_negedge    :	VitalDelayType := 0.000 ns;
      tperiod_CLK_negedge            :	VitalDelayType := 0.000 ns;
      tpw_CLK_negedge                :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_SR_CLK                    :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                    :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SR                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CE                             :	in    STD_ULOGIC;
      SR                             :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCBSRH_1 : entity is TRUE;
end DFFCBSRH_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCBSRH_1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	         : STD_ULOGIC := 'X';
   SIGNAL SR_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL SR_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SR_ipd, SR, tipd_SR);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (SR_CLK_dly, SR_ipd, tisd_SR_CLK);

   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, SR_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_SR_CLK_CE_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_SR_CLK_CE_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE D_in_zd : STD_ULOGIC := '0';
   VARIABLE CLK_inverted : STD_ULOGIC := 'X';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_negedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_negedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_negedge,
          SetupLow                => tsetup_D_CLK_noedge_negedge,
          HoldHigh                => thold_D_CLK_noedge_negedge,
          HoldLow                 => thold_D_CLK_noedge_negedge,
          CheckEnabled            => TO_X01(CE_ipd) ='0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBSRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_SR_CLK_CE_EQ_1_negedge,
          TimingData              => Tmkr_SR_CLK_CE_EQ_1_negedge,
          TestSignal              => SR_CLK_dly,
          TestSignalName          => "SR",
          TestDelay               => tisd_SR_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_SR_CLK_noedge_negedge,
          SetupLow                => tsetup_SR_CLK_noedge_negedge,
          HoldHigh                => thold_SR_CLK_noedge_negedge,
          HoldLow                 => thold_SR_CLK_noedge_negedge,
          CheckEnabled            => TO_X01(CE_ipd) ='0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBSRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_negedge,
          TimingData              => Tmkr_CE_CLK_negedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_negedge,
          SetupLow                => tsetup_CE_CLK_noedge_negedge,
          HoldHigh                => thold_CE_CLK_noedge_negedge,
          HoldLow                 => thold_CE_CLK_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBSRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1,
          PeriodData              => PInfo_CLK_CE_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_negedge,
          PulseWidthHigh          => tpw_CLK_negedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(CE_ipd) ='0',
          HeaderMsg               => InstancePath &"/DFFCBSRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      CLK_inverted := NOT(CLK_dly);
      D_in_zd := VitalAND2(NOT(SR_CLK_dly) ,  D_CLK_dly);
      Violation := Tviol_D_CLK_CE_EQ_1_negedge or Tviol_CE_CLK_negedge or Pviol_CLK_CE_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_in_zd, CLK_inverted, '1','1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCBSRH_1_VITAL of DFFCBSRH_1 is 
        for VITAL
        end for; 
end CFG_DFFCBSRH_1_VITAL;

----- VITAL model for cell DFFCBSSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCBSSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge    :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge     :	VitalDelayType := 0.000 ns;
      tsetup_SS_CLK_noedge_posedge   :	VitalDelayType := 0.100 ns;
      thold_SS_CLK_noedge_posedge    :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_posedge   :  VitalDelayType := 0.100 ns;
      thold_CE_CLK_noedge_posedge    :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge            :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge                :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_SS_CLK                    :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                    :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SS                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CE                             :	in    STD_ULOGIC;
      SS                             :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCBSSH : entity is TRUE;
end DFFCBSSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCBSSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	         : STD_ULOGIC := 'X';
   SIGNAL SS_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL SS_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SS_ipd, SS, tipd_SS);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (SS_CLK_dly, SS_ipd, tisd_SS_CLK);

   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, SS_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_SS_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_SS_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE D_in_zd : STD_ULOGIC := '0';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(CE_ipd) ='0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_SS_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_SS_CLK_CE_EQ_1_posedge,
          TestSignal              => SS_CLK_dly,
          TestSignalName          => "SS",
          TestDelay               => tisd_SS_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_SS_CLK_noedge_posedge,
          SetupLow                => tsetup_SS_CLK_noedge_posedge,
          HoldHigh                => thold_SS_CLK_noedge_posedge,
          HoldLow                 => thold_SS_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(CE_ipd) ='0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_posedge,
          TimingData              => Tmkr_CE_CLK_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_posedge,
          SetupLow                => tsetup_CE_CLK_noedge_posedge,
          HoldHigh                => thold_CE_CLK_noedge_posedge,
          HoldLow                 => thold_CE_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1,
          PeriodData              => PInfo_CLK_CE_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(CE_ipd) ='0',
          HeaderMsg               => InstancePath &"/DFFCBSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      D_in_zd := VitalOR2(SS_CLK_dly ,  D_CLK_dly);
      Violation := Tviol_D_CLK_CE_EQ_1_posedge or Tviol_CE_CLK_posedge or Pviol_CLK_CE_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_in_zd, CLK_dly, '1','1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCBSSH_VITAL of DFFCBSSH is 
        for VITAL
        end for; 
end CFG_DFFCBSSH_VITAL;



----- VITAL model for cell DFFCBSSH_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCBSSH_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_negedge    :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_negedge     :	VitalDelayType := 0.000 ns;
      tsetup_SS_CLK_noedge_negedge   :	VitalDelayType := 0.100 ns;
      thold_SS_CLK_noedge_negedge    :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_negedge   :  VitalDelayType := 0.100 ns;
      thold_CE_CLK_noedge_negedge    :	VitalDelayType := 0.000 ns;
      tperiod_CLK_negedge            :	VitalDelayType := 0.000 ns;
      tpw_CLK_negedge                :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_SS_CLK                    :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                    :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SS                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CE                             :	in    STD_ULOGIC;
      SS                             :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCBSSH_1 : entity is TRUE;
end DFFCBSSH_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCBSSH_1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	         : STD_ULOGIC := 'X';
   SIGNAL SS_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL SS_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SS_ipd, SS, tipd_SS);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (SS_CLK_dly, SS_ipd, tisd_SS_CLK);

   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, SS_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_SS_CLK_CE_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_SS_CLK_CE_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE D_in_zd : STD_ULOGIC := '0';
   VARIABLE CLK_inverted : STD_ULOGIC := 'X';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_negedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_negedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_negedge,
          SetupLow                => tsetup_D_CLK_noedge_negedge,
          HoldHigh                => thold_D_CLK_noedge_negedge,
          HoldLow                 => thold_D_CLK_noedge_negedge,
          CheckEnabled            => TO_X01(CE_ipd) ='0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBSSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_SS_CLK_CE_EQ_1_negedge,
          TimingData              => Tmkr_SS_CLK_CE_EQ_1_negedge,
          TestSignal              => SS_CLK_dly,
          TestSignalName          => "SS",
          TestDelay               => tisd_SS_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_SS_CLK_noedge_negedge,
          SetupLow                => tsetup_SS_CLK_noedge_negedge,
          HoldHigh                => thold_SS_CLK_noedge_negedge,
          HoldLow                 => thold_SS_CLK_noedge_negedge,
          CheckEnabled            => TO_X01(CE_ipd) ='0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBSSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_negedge,
          TimingData              => Tmkr_CE_CLK_negedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_negedge,
          SetupLow                => tsetup_CE_CLK_noedge_negedge,
          HoldHigh                => thold_CE_CLK_noedge_negedge,
          HoldLow                 => thold_CE_CLK_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBSSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1,
          PeriodData              => PInfo_CLK_CE_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_negedge,
          PulseWidthHigh          => tpw_CLK_negedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(CE_ipd) ='0',
          HeaderMsg               => InstancePath &"/DFFCBSSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      CLK_inverted := NOT(CLK_dly);
      D_in_zd := VitalOR2(SS_CLK_dly ,  D_CLK_dly);
      Violation := Tviol_D_CLK_CE_EQ_1_negedge or Tviol_CE_CLK_negedge or Pviol_CLK_CE_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_in_zd, CLK_inverted, '1','1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCBSSH_1_VITAL of DFFCBSSH_1 is 
        for VITAL
        end for; 
end CFG_DFFCBSSH_1_VITAL;



----- VITAL model for cell DFFCBRSS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;


-- entity declaration --
entity DFFCBRSS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_R_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_CE_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge :	VitalDelayType := 0.000 ns;
      trecovery_R_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      trecovery_S_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCBRSS : entity is TRUE;
end DFFCBRSS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCBRSS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, R_CLK_dly, S_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_1_ANB_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_ANB_R_EQ_1_ANB_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_CE_EQ_1_ANB_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_CE_EQ_1_ANB_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_CE_EQ_1_ANB_R_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_CE_EQ_1_ANB_R_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1_ANB_R_EQ_1_ANB_S_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1_ANB_R_EQ_1_ANB_S_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE D_int : STD_ULOGIC ;
   VARIABLE S_inverted : STD_ULOGIC ;
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_1_ANB_S_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_ANB_R_EQ_1_ANB_S_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01((R_CLK_dly) AND NOT (CE_ipd) AND (S_CLK_dly)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBRSS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_posedge,
          TimingData              => Tmkr_CE_CLK_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_posedge_posedge,
          SetupLow                => tsetup_CE_CLK_posedge_posedge,
          HoldHigh                => thold_CE_CLK_posedge_posedge,
          HoldLow                 => thold_CE_CLK_posedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBRSS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_CE_EQ_1_ANB_S_EQ_1_posedge,
          TimingData              => Tmkr_R_CLK_CE_EQ_1_ANB_S_EQ_1_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_posedge_posedge,
          Removal                 => thold_R_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TO_X01((S_CLK_dly) AND NOT (CE_ipd)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBRSS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_CE_EQ_1_ANB_R_EQ_1_posedge,
          TimingData              => Tmkr_S_CLK_CE_EQ_1_ANB_R_EQ_1_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_posedge_posedge,
          Removal                 => thold_S_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TO_X01((R_CLK_dly) AND NOT (CE_ipd)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBRSS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1_ANB_R_EQ_1_ANB_S_EQ_1,
          PeriodData              => PInfo_CLK_CE_EQ_1_ANB_R_EQ_1_ANB_S_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01((R_CLK_dly) AND NOT (CE_ipd) AND (S_CLK_dly)) = '1',
          HeaderMsg               => InstancePath & "/DFFCBRSS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_1_ANB_S_EQ_1_posedge or Tviol_CE_CLK_posedge or Tviol_R_CLK_CE_EQ_1_ANB_S_EQ_1_posedge or Tviol_S_CLK_CE_EQ_1_ANB_R_EQ_1_posedge or Pviol_CLK_CE_EQ_1_ANB_R_EQ_1_ANB_S_EQ_1;
      S_inverted := VitalINV (S_CLK_dly);
      D_int := VitalOR2 (D_CLK_dly,S_inverted);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_int, CLK_dly, R_CLK_dly, '1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 2 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCBRSS_VITAL of DFFCBRSS is 
        for VITAL
        end for; 
end CFG_DFFCBRSS_VITAL;

----- VITAL model for cell DFFCBRSSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCBRSSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_R_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_CE_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge :	VitalDelayType := 0.000 ns;
      tpw_R_posedge :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge :	VitalDelayType := 0.000 ns;
      trecovery_R_CLK_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_negedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_S_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCBRSSH : entity is TRUE;
end DFFCBRSSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCBRSSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, R_CLK_dly, S_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_0_ANB_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_ANB_R_EQ_0_ANB_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_CE_EQ_1_ANB_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_CE_EQ_1_ANB_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_CE_EQ_1_ANB_R_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_CE_EQ_1_ANB_R_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1_ANB_R_EQ_0_ANB_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_R	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1_ANB_R_EQ_0_ANB_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE R_inverted : STD_ULOGIC := 'X';
   VARIABLE D_int : STD_ULOGIC := '0';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_0_ANB_S_EQ_0_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_ANB_R_EQ_0_ANB_S_EQ_0_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(((NOT R_CLK_dly)) AND NOT (CE_ipd) AND ((NOT S_CLK_dly))) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBRSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_posedge,
          TimingData              => Tmkr_CE_CLK_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_posedge,
          SetupLow                => tsetup_CE_CLK_noedge_posedge,
          HoldHigh                => thold_CE_CLK_noedge_posedge,
          HoldLow                 => thold_CE_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBRSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_CE_EQ_1_ANB_S_EQ_0_posedge,
          TimingData              => Tmkr_R_CLK_CE_EQ_1_ANB_S_EQ_0_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_negedge_posedge,
          Removal                 => thold_R_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TO_X01(((NOT S_CLK_dly)) AND NOT (CE_ipd)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBRSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_S_CLK_CE_EQ_1_ANB_R_EQ_0_posedge,
          TimingData              => Tmkr_S_CLK_CE_EQ_1_ANB_R_EQ_0_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_S_CLK_noedge_posedge,
          SetupLow                => tsetup_S_CLK_noedge_posedge,
          HoldHigh                => thold_S_CLK_noedge_posedge,
          HoldLow                 => thold_S_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(((NOT R_CLK_dly)) AND NOT (CE_ipd)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBRSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_R_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFCBRSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1_ANB_R_EQ_0_ANB_S_EQ_0,
          PeriodData              => PInfo_CLK_CE_EQ_1_ANB_R_EQ_0_ANB_S_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(((NOT R_CLK_dly)) AND (NOT (CE_ipd)) AND ((NOT S_CLK_dly))) = '1',
          HeaderMsg               => InstancePath & "/DFFCBRSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_ANB_R_EQ_0_ANB_S_EQ_0_posedge or Tviol_CE_CLK_posedge or Tviol_R_CLK_CE_EQ_1_ANB_S_EQ_0_posedge or Tviol_S_CLK_CE_EQ_1_ANB_R_EQ_0_posedge or Pviol_CLK_CE_EQ_1_ANB_R_EQ_0_ANB_S_EQ_0 or Pviol_R;
      R_inverted := (NOT R_CLK_dly);
      D_int := VitalOR2 (D_CLK_dly,S_CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_int, CLK_dly, R_inverted, '1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 2 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCBRSSH_VITAL of DFFCBRSSH is 
        for VITAL
        end for; 
end CFG_DFFCBRSSH_VITAL;

----- VITAL model for cell DFFCBS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCBS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_CE_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge :	VitalDelayType := 0.000 ns;
      trecovery_S_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCBS : entity is TRUE;
end DFFCBS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCBS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, S_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_ANB_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_ANB_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1_ANB_S_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1_ANB_S_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_ANB_S_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_ANB_S_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01((S_CLK_dly) AND NOT (CE_ipd)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_posedge,
          TimingData              => Tmkr_CE_CLK_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_posedge_posedge,
          SetupLow                => tsetup_CE_CLK_posedge_posedge,
          HoldHigh                => thold_CE_CLK_posedge_posedge,
          HoldLow                 => thold_CE_CLK_posedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_S_CLK_CE_EQ_1_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_posedge_posedge,
          Removal                 => thold_S_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1_ANB_S_EQ_1,
          PeriodData              => PInfo_CLK_CE_EQ_1_ANB_S_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01((S_CLK_dly) AND NOT (CE_ipd)) = '1',
          HeaderMsg               => InstancePath & "/DFFCBS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_ANB_S_EQ_1_posedge or Tviol_CE_CLK_posedge or Tviol_S_CLK_CE_EQ_1_posedge or Pviol_CLK_CE_EQ_1_ANB_S_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_CLK_dly, CLK_dly,'1',S_CLK_dly, CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCBS_VITAL of DFFCBS is 
        for VITAL
        end for; 
end CFG_DFFCBS_VITAL;

----- VITAL model for cell DFFCBSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCBSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_CE_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge :	VitalDelayType := 0.000 ns;
      tpw_S_posedge :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge :	VitalDelayType := 0.000 ns;
      trecovery_S_CLK_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_negedge_posedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCBSH : entity is TRUE;
end DFFCBSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCBSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, S_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_ANB_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_ANB_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1_ANB_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_S	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1_ANB_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE S_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_ANB_S_EQ_0_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_ANB_S_EQ_0_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(((NOT S_CLK_dly)) AND NOT (CE_ipd)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_posedge,
          TimingData              => Tmkr_CE_CLK_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_posedge,
          SetupLow                => tsetup_CE_CLK_noedge_posedge,
          HoldHigh                => thold_CE_CLK_noedge_posedge,
          HoldLow                 => thold_CE_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_S_CLK_CE_EQ_1_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_negedge_posedge,
          Removal                 => thold_S_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFCBSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1_ANB_S_EQ_0,
          PeriodData              => PInfo_CLK_CE_EQ_1_ANB_S_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(((NOT S_CLK_dly)) AND NOT (CE_ipd)) = '0',
          HeaderMsg               => InstancePath & "/DFFCBSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_ANB_S_EQ_0_posedge or Tviol_CE_CLK_posedge or Tviol_S_CLK_CE_EQ_1_posedge or Pviol_CLK_CE_EQ_1_ANB_S_EQ_0 or Pviol_S;
      S_inverted := (NOT S_CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_CLK_dly, CLK_dly,'1', S_inverted, CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCBSH_VITAL of DFFCBSH is 
        for VITAL
        end for; 
end CFG_DFFCBSH_VITAL;


----- VITAL model for cell DFFCBSH_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCBSH_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_negedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_CE_CLK_noedge_negedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_negedge :	VitalDelayType := 0.000 ns;
      tpw_S_negedge :	VitalDelayType := 0.000 ns;
      tperiod_CLK_negedge :	VitalDelayType := 0.000 ns;
      trecovery_S_CLK_negedge_negedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_negedge_negedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCBSH_1 : entity is TRUE;
end DFFCBSH_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCBSH_1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, S_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_ANB_S_EQ_0_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_ANB_S_EQ_0_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_CE_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_CE_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1_ANB_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_S	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1_ANB_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE S_inverted : STD_ULOGIC := 'X';
   VARIABLE CLK_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_ANB_S_EQ_0_negedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_ANB_S_EQ_0_negedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_negedge,
          SetupLow                => tsetup_D_CLK_noedge_negedge,
          HoldHigh                => thold_D_CLK_noedge_negedge,
          HoldLow                 => thold_D_CLK_noedge_negedge,
          CheckEnabled            => TO_X01(((NOT S_CLK_dly)) AND NOT (CE_ipd)) = '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_negedge,
          TimingData              => Tmkr_CE_CLK_negedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_negedge,
          SetupLow                => tsetup_CE_CLK_noedge_negedge,
          HoldHigh                => thold_CE_CLK_noedge_negedge,
          HoldLow                 => thold_CE_CLK_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_CE_EQ_1_negedge,
          TimingData              => Tmkr_S_CLK_CE_EQ_1_negedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_negedge_negedge,
          Removal                 => thold_S_CLK_negedge_negedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_negedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFCBSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1_ANB_S_EQ_0,
          PeriodData              => PInfo_CLK_CE_EQ_1_ANB_S_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_negedge,
          PulseWidthHigh          => tpw_CLK_negedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(((NOT S_CLK_dly)) AND NOT (CE_ipd)) = '1',
          HeaderMsg               => InstancePath & "/DFFCBSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_CE_EQ_1_ANB_S_EQ_0_negedge or Tviol_CE_CLK_negedge or Tviol_S_CLK_CE_EQ_1_negedge or Pviol_CLK_CE_EQ_1_ANB_S_EQ_0 or Pviol_S;
      S_inverted := (NOT S_CLK_dly);
      CLK_inverted := (NOT CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_CLK_dly, CLK_inverted,'1', S_inverted, CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCBSH_1_VITAL of DFFCBSH_1 is 
        for VITAL
        end for; 
end CFG_DFFCBSH_1_VITAL;


----- VITAL model for cell DFFR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge         :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge             :	VitalDelayType := 0.000 ns;
      trecovery_R_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_posedge_posedge    :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFR : entity is TRUE;
end DFFR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFR is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, R_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_R_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_R_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_R_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_R_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_R_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_R_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(R_CLK_dly) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_posedge,
          TimingData              => Tmkr_R_CLK_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_posedge_posedge,
          Removal                 => thold_R_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_R_EQ_1,
          PeriodData              => PInfo_CLK_R_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01((R_CLK_dly) ) = '1',
          HeaderMsg               => InstancePath & "/DFFR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_R_EQ_1_posedge or Tviol_R_CLK_posedge or Pviol_CLK_R_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
              D_CLK_dly, CLK_dly, R_CLK_dly, '1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFR_VITAL of DFFR is 
        for VITAL
        end for; 
end CFG_DFFR_VITAL;

----- VITAL model for cell DFFRH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFRH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge         :	VitalDelayType := 0.000 ns;
      tpw_R_posedge         :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge             :	VitalDelayType := 0.000 ns;
      trecovery_R_CLK_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_negedge_posedge    :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFRH : entity is TRUE;
end DFFRH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFRH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, R_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_R_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_R_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_R_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_R	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_R_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE R_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_R_EQ_0_posedge,
          TimingData              => Tmkr_D_CLK_R_EQ_0_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01((R_CLK_dly)) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_posedge,
          TimingData              => Tmkr_R_CLK_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_negedge_posedge,
          Removal                 => thold_R_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_R_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_R_EQ_0,
          PeriodData              => PInfo_CLK_R_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(R_CLK_dly ) = '0',
          HeaderMsg               => InstancePath & "/DFFRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_R_EQ_0_posedge or Tviol_R_CLK_posedge or Pviol_CLK_R_EQ_0 or Pviol_R;
      R_inverted := (NOT R_CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_CLK_dly, CLK_dly, R_inverted, '1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFRH_VITAL of DFFRH is 
        for VITAL
        end for; 
end CFG_DFFRH_VITAL;



----- VITAL model for cell DFFRH_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFRH_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_negedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_negedge         :	VitalDelayType := 0.000 ns;
      tpw_R_negedge         :	VitalDelayType := 0.000 ns;
      tperiod_CLK_negedge             :	VitalDelayType := 0.000 ns;
      trecovery_R_CLK_negedge_negedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_negedge_negedge    :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFRH_1 : entity is TRUE;
end DFFRH_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFRH_1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, R_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_R_EQ_0_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_R_EQ_0_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_R_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_R	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_R_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE R_inverted : STD_ULOGIC := 'X';
   VARIABLE CLK_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_R_EQ_0_negedge,
          TimingData              => Tmkr_D_CLK_R_EQ_0_negedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_negedge,
          SetupLow                => tsetup_D_CLK_noedge_negedge,
          HoldHigh                => thold_D_CLK_noedge_negedge,
          HoldLow                 => thold_D_CLK_noedge_negedge,
          CheckEnabled            => TO_X01((R_CLK_dly)) = '0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_negedge,
          TimingData              => Tmkr_R_CLK_negedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_negedge_negedge,
          Removal                 => thold_R_CLK_negedge_negedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_R_negedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_R_EQ_0,
          PeriodData              => PInfo_CLK_R_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_negedge,
          PulseWidthHigh          => tpw_CLK_negedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(R_CLK_dly ) = '0',
          HeaderMsg               => InstancePath & "/DFFRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_R_EQ_0_negedge or Tviol_R_CLK_negedge or Pviol_CLK_R_EQ_0 or Pviol_R;
      R_inverted := (NOT R_CLK_dly);
      CLK_inverted := (NOT CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dff_1tab,
        DataIn => (
               D_CLK_dly, CLK_inverted, R_inverted, '1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFRH_1_VITAL of DFFRH_1 is 
        for VITAL
        end for; 
end CFG_DFFRH_1_VITAL;


----- VITAL model for cell DFFSRH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFSRH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge    :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge     :	VitalDelayType := 0.000 ns;
      tsetup_SR_CLK_noedge_posedge    :	VitalDelayType := 0.100 ns;
      thold_SR_CLK_noedge_posedge     :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge            :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge                :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_SR_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SR                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SR                             :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFSRH : entity is TRUE;
end DFFSRH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFSRH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	         : STD_ULOGIC := 'X';
   SIGNAL SR_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL SR_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SR_ipd, SR, tipd_SR);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (SR_CLK_dly, SR_ipd, tisd_SR_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, SR_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   VARIABLE D_in_zd : STD_ULOGIC := '0';
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_posedge,
          TimingData              => Tmkr_D_CLK_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFSRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/DFFSRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      D_in_zd := VitalAND2 (NOT(SR_CLK_dly) , D_CLK_dly);
      Violation := Tviol_D_CLK_posedge or Pviol_CLK;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_in_zd, CLK_dly, '1','1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFSRH_VITAL of DFFSRH is 
        for VITAL
        end for; 
end CFG_DFFSRH_VITAL;


----- VITAL model for cell DFFSRH_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFSRH_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_negedge    :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_negedge     :	VitalDelayType := 0.000 ns;
      tsetup_SR_CLK_noedge_negedge    :	VitalDelayType := 0.100 ns;
      thold_SR_CLK_noedge_negedge     :	VitalDelayType := 0.000 ns;
      tperiod_CLK_negedge            :	VitalDelayType := 0.000 ns;
      tpw_CLK_negedge                :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_SR_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SR                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SR                             :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFSRH_1 : entity is TRUE;
end DFFSRH_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFSRH_1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	         : STD_ULOGIC := 'X';
   SIGNAL SR_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL SR_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SR_ipd, SR, tipd_SR);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (SR_CLK_dly, SR_ipd, tisd_SR_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, SR_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   VARIABLE CLK_inverted : STD_ULOGIC := 'X';
   VARIABLE D_in_zd : STD_ULOGIC := '0';
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_negedge,
          TimingData              => Tmkr_D_CLK_negedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_negedge,
          SetupLow                => tsetup_D_CLK_noedge_negedge,
          HoldHigh                => thold_D_CLK_noedge_negedge,
          HoldLow                 => thold_D_CLK_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFSRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_negedge,
          PulseWidthHigh          => tpw_CLK_negedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/DFFSRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      D_in_zd := VitalAND2(NOT(SR_CLK_dly), D_CLK_dly);
      CLK_inverted := (NOT CLK_dly);
      Violation := Tviol_D_CLK_negedge or Pviol_CLK;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_in_zd, CLK_inverted, '1','1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFSRH_1_VITAL of DFFSRH_1 is 
        for VITAL
        end for; 
end CFG_DFFSRH_1_VITAL;



----- VITAL model for cell DFFRSS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;


-- entity declaration --
entity DFFRSS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge  :	VitalDelayType := 0.000 ns;
      trecovery_R_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      trecovery_S_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_posedge_posedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFRSS : entity is TRUE;
end DFFRSS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFRSS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, R_CLK_dly, S_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_R_EQ_1_ANB_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_R_EQ_1_ANB_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_R_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_R_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_R_EQ_1_ANB_S_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_R_EQ_1_ANB_S_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE NOT_S_zd : STD_ULOGIC := '0';
   VARIABLE D_in_zd : STD_ULOGIC := '0';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_R_EQ_1_ANB_S_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_R_EQ_1_ANB_S_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01((S_CLK_dly) AND (R_CLK_dly)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRSS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_S_EQ_1_posedge,
          TimingData              => Tmkr_R_CLK_S_EQ_1_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_posedge_posedge,
          Removal                 => thold_R_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TO_X01(S_CLK_dly) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRSS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_R_EQ_1_posedge,
          TimingData              => Tmkr_S_CLK_R_EQ_1_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_posedge_posedge,
          Removal                 => thold_S_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TO_X01(R_CLK_dly) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRSS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_R_EQ_1_ANB_S_EQ_1,
          PeriodData              => PInfo_CLK_R_EQ_1_ANB_S_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(( (S_CLK_dly) ) AND ( (R_CLK_dly) )) = '1',
          HeaderMsg               => InstancePath & "/DFFRSS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------

        NOT_S_zd := VitalINV (S_CLK_dly);
        D_in_zd := VitalOR2 (NOT_S_zd , D_CLK_dly);

      Violation := Tviol_D_CLK_R_EQ_1_ANB_S_EQ_1_posedge or Tviol_R_CLK_S_EQ_1_posedge or Tviol_S_CLK_R_EQ_1_posedge or Pviol_CLK_R_EQ_1_ANB_S_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_in_zd, CLK_dly, R_CLK_dly, '1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 2 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFRSS_VITAL of DFFRSS is 
        for VITAL
        end for; 
end CFG_DFFRSS_VITAL;

----- VITAL model for cell DFFRSSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFRSSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_R_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge :	VitalDelayType := 0.000 ns;
      tpw_R_posedge :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge  :	VitalDelayType := 0.000 ns;
      trecovery_R_CLK_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_CLK_negedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_S_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_R_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFRSSH : entity is TRUE;
end DFFRSSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFRSSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (R_ipd, R, tipd_R);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (R_CLK_dly, R_ipd, tisd_R_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, R_CLK_dly, S_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_R_EQ_0_ANB_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_R_EQ_0_ANB_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_CLK_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_CLK_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_R_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_R_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_R_EQ_0_ANB_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_R	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_R_EQ_0_ANB_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_R	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE R_inverted : STD_ULOGIC := 'X';
   VARIABLE S_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE D_in_zd : STD_ULOGIC := '0';


   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_R_EQ_0_ANB_S_EQ_0_posedge,
          TimingData              => Tmkr_D_CLK_R_EQ_0_ANB_S_EQ_0_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(((NOT S_CLK_dly)) AND ((NOT R_CLK_dly))) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_CLK_S_EQ_0_posedge,
          TimingData              => Tmkr_R_CLK_S_EQ_0_posedge,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_R_CLK_negedge_posedge,
          Removal                 => thold_R_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TO_X01((NOT S_CLK_dly)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_S_CLK_R_EQ_0_posedge,
          TimingData              => Tmkr_S_CLK_R_EQ_0_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_S_CLK_noedge_posedge,
          SetupLow                => tsetup_S_CLK_noedge_posedge,
          HoldHigh                => thold_S_CLK_noedge_posedge,
          HoldLow                 => thold_S_CLK_noedge_posedge,
          CheckEnabled            => TO_X01((NOT R_CLK_dly)) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFRSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_R,
          PeriodData              => PInfo_R,
          TestSignal              => R_CLK_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_R_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFRSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_R_EQ_0_ANB_S_EQ_0,
          PeriodData              => PInfo_CLK_R_EQ_0_ANB_S_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(((NOT S_CLK_dly)) AND ((NOT R_CLK_dly))) = '1',
          HeaderMsg               => InstancePath & "/DFFRSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------

        D_in_zd := VitalOR2 (S_CLK_dly , D_CLK_dly);

      Violation := Tviol_D_CLK_R_EQ_0_ANB_S_EQ_0_posedge or Tviol_S_CLK_R_EQ_0_posedge or Pviol_CLK_R_EQ_0_ANB_S_EQ_0 or Tviol_R_CLK_S_EQ_0_posedge or Pviol_R;
      S_inverted := (NOT S_CLK_dly);
      R_inverted := (NOT R_CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_in_zd, CLK_dly, R_inverted, '1' ));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (R_CLK_dly'last_event, tpd_R_Q, TRUE),
                 1 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 2 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFRSSH_VITAL of DFFRSSH is 
        for VITAL
        end for; 
end CFG_DFFRSSH_VITAL;

----- VITAL model for cell DFFS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge         :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge             :	VitalDelayType := 0.000 ns;
      trecovery_S_CLK_posedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_posedge_posedge    :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFS : entity is TRUE;
end DFFS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, S_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_S_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_S_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_S_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_S_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_S_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_S_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(S_CLK_dly) = '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_posedge,
          TimingData              => Tmkr_S_CLK_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_posedge_posedge,
          Removal                 => thold_S_CLK_posedge_posedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_S_EQ_1,
          PeriodData              => PInfo_CLK_S_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01((S_CLK_dly) ) = '1',
          HeaderMsg               => InstancePath & "/DFFS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_S_EQ_1_posedge or Tviol_S_CLK_posedge or Pviol_CLK_S_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_CLK_dly, CLK_dly, '1', S_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFS_VITAL of DFFS is 
        for VITAL
        end for; 
end CFG_DFFS_VITAL;

----- VITAL model for cell DFFSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge         :	VitalDelayType := 0.000 ns;
      tpw_S_posedge         :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge             :	VitalDelayType := 0.000 ns;
      trecovery_S_CLK_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_negedge_posedge    :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFSH : entity is TRUE;
end DFFSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, S_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_S_EQ_0_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_S_EQ_0_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_S	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE S_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_S_EQ_0_posedge,
          TimingData              => Tmkr_D_CLK_S_EQ_0_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01((S_CLK_dly)) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_posedge,
          TimingData              => Tmkr_S_CLK_posedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_negedge_posedge,
          Removal                 => thold_S_CLK_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_S_EQ_0,
          PeriodData              => PInfo_CLK_S_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(S_CLK_dly ) = '0',
          HeaderMsg               => InstancePath & "/DFFSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_S_EQ_0_posedge or Tviol_S_CLK_posedge or Pviol_CLK_S_EQ_0;
      S_inverted := (NOT S_CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_CLK_dly, CLK_dly, '1', S_inverted));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFSH_VITAL of DFFSH is 
        for VITAL
        end for; 
end CFG_DFFSH_VITAL;


----- VITAL model for cell DFFSH_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFSH_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_S_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_negedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_negedge         :	VitalDelayType := 0.000 ns;
      tpw_S_negedge         :	VitalDelayType := 0.000 ns;
      tperiod_CLK_negedge             :	VitalDelayType := 0.000 ns;
      trecovery_S_CLK_negedge_negedge :	VitalDelayType := 0.100 ns;
      thold_S_CLK_negedge_negedge    :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_S_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFSH_1 : entity is TRUE;
end DFFSH_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFSH_1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (S_CLK_dly, S_ipd, tisd_S_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, S_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_S_EQ_0_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_S_EQ_0_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_CLK_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_CLK_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_S	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE S_inverted : STD_ULOGIC := 'X';
   VARIABLE CLK_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_S_EQ_0_negedge,
          TimingData              => Tmkr_D_CLK_S_EQ_0_negedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_negedge,
          SetupLow                => tsetup_D_CLK_noedge_negedge,
          HoldHigh                => thold_D_CLK_noedge_negedge,
          HoldLow                 => thold_D_CLK_noedge_negedge,
          CheckEnabled            => TO_X01((S_CLK_dly)) = '0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_CLK_negedge,
          TimingData              => Tmkr_S_CLK_negedge,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          Recovery                => trecovery_S_CLK_negedge_negedge,
          Removal                 => thold_S_CLK_negedge_negedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_CLK_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_CLK,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_negedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DFFSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_S_EQ_0,
          PeriodData              => PInfo_CLK_S_EQ_0,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_negedge,
          PulseWidthHigh          => tpw_CLK_negedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(S_CLK_dly ) = '0',
          HeaderMsg               => InstancePath & "/DFFSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_CLK_S_EQ_0_negedge or Tviol_S_CLK_negedge or Pviol_CLK_S_EQ_0;
      S_inverted := (NOT S_CLK_dly);
      CLK_inverted := (NOT CLK_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_CLK_dly, CLK_inverted, '1', S_inverted));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (S_CLK_dly'last_event, tpd_S_Q, TRUE),
                 1 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFSH_1_VITAL of DFFSH_1 is 
        for VITAL
        end for; 
end CFG_DFFSH_1_VITAL;


----- VITAL model for cell DFFSSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFSSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge    :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge     :	VitalDelayType := 0.000 ns;
      tsetup_SS_CLK_noedge_posedge    :	VitalDelayType := 0.100 ns;
      thold_SS_CLK_noedge_posedge     :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge            :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge                :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_SS_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SS                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SS                             :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFSSH : entity is TRUE;
end DFFSSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFSSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	         : STD_ULOGIC := 'X';
   SIGNAL SS_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL SS_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SS_ipd, SS, tipd_SS);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (SS_CLK_dly, SS_ipd, tisd_SS_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, SS_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   VARIABLE D_in_zd : STD_ULOGIC := '0';
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_posedge,
          TimingData              => Tmkr_D_CLK_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/DFFSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      D_in_zd := VitalOR2(SS_CLK_dly, D_CLK_dly);
      Violation := Tviol_D_CLK_posedge or Pviol_CLK;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_in_zd, CLK_dly, '1','1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFSSH_VITAL of DFFSSH is 
        for VITAL
        end for; 
end CFG_DFFSSH_VITAL;



----- VITAL model for cell DFFSSH_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFSSH_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_negedge    :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_negedge     :	VitalDelayType := 0.000 ns;
      tsetup_SS_CLK_noedge_negedge    :	VitalDelayType := 0.100 ns;
      thold_SS_CLK_noedge_negedge     :	VitalDelayType := 0.000 ns;
      tperiod_CLK_negedge            :	VitalDelayType := 0.000 ns;
      tpw_CLK_negedge                :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_SS_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SS                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SS                             :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFSSH_1 : entity is TRUE;
end DFFSSH_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFSSH_1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	         : STD_ULOGIC := 'X';
   SIGNAL SS_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL SS_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SS_ipd, SS, tipd_SS);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (SS_CLK_dly, SS_ipd, tisd_SS_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, SS_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   VARIABLE CLK_inverted : STD_ULOGIC := 'X';
   VARIABLE D_in_zd : STD_ULOGIC := '1';
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_negedge,
          TimingData              => Tmkr_D_CLK_negedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_negedge,
          SetupLow                => tsetup_D_CLK_noedge_negedge,
          HoldHigh                => thold_D_CLK_noedge_negedge,
          HoldLow                 => thold_D_CLK_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFSSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_negedge,
          PulseWidthHigh          => tpw_CLK_negedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/DFFSSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      D_in_zd := VitalOR2(SS_CLK_dly, D_CLK_dly);
      CLK_inverted := (NOT CLK_dly);
      Violation := Tviol_D_CLK_negedge or Pviol_CLK;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_in_zd, CLK_inverted, '1','1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFSSH_1_VITAL of DFFSSH_1 is 
        for VITAL
        end for; 
end CFG_DFFSSH_1_VITAL;




----- VITAL model for cell DFFLSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFLSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge    :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge     :	VitalDelayType := 0.000 ns;
      tsetup_SD_CLK_noedge_posedge   :	VitalDelayType := 0.100 ns;
      thold_SD_CLK_noedge_posedge    :	VitalDelayType := 0.000 ns;
      tsetup_LD_CLK_noedge_posedge   :	VitalDelayType := 0.100 ns;
      thold_LD_CLK_noedge_posedge    :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge            :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge                :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_SD_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_LD_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SD                             :	in    STD_ULOGIC;
      LD                             :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFLSH : entity is TRUE;
end DFFLSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFLSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL SD_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL LD_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (LD_ipd, LD, tipd_LD);
   VitalWireDelay (SD_ipd, SD, tipd_SD);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (SD_CLK_dly, SD_ipd, tisd_SD_CLK);
   VitalSignalDelay (LD_CLK_dly, LD_ipd, tisd_LD_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, SD_CLK_dly, LD_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_SD_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tviol_LD_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_LD_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK	: STD_ULOGIC := '0';
   VARIABLE Tmkr_SD_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE PInfo_CLK	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE D_SD_MUX : STD_ULOGIC := 'X';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_posedge,
          TimingData              => Tmkr_D_CLK_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFLSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_SD_CLK_posedge,
          TimingData              => Tmkr_SD_CLK_posedge,
          TestSignal              => SD_CLK_dly,
          TestSignalName          => "SD",
          TestDelay               => tisd_SD_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_SD_CLK_noedge_posedge,
          SetupLow                => tsetup_SD_CLK_noedge_posedge,
          HoldHigh                => thold_SD_CLK_noedge_posedge,
          HoldLow                 => thold_SD_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFLSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_LD_CLK_posedge,
          TimingData              => Tmkr_LD_CLK_posedge,
          TestSignal              => LD_CLK_dly,
          TestSignalName          => "LD",
          TestDelay               => tisd_LD_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_LD_CLK_noedge_posedge,
          SetupLow                => tsetup_LD_CLK_noedge_posedge,
          HoldHigh                => thold_LD_CLK_noedge_posedge,
          HoldLow                 => thold_LD_CLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFLSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/DFFLSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      D_SD_MUX := VitalMUX2
		     (data0 => D_CLK_dly, 
		      data1 => SD_CLK_dly,
		      dselect => LD_CLK_dly);
      Violation := Tviol_D_CLK_posedge or Pviol_CLK;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_SD_MUX, CLK_dly, '1','1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFLSH_VITAL of DFFLSH is 
        for VITAL
        end for; 
end CFG_DFFLSH_VITAL;

----- VITAL model for cell DFFLSH_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFLSH_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_negedge    :	VitalDelayType := 0.200 ns;
      thold_D_CLK_noedge_negedge     :	VitalDelayType := 0.000 ns;
      tsetup_SD_CLK_noedge_negedge   :	VitalDelayType := 0.200 ns;
      thold_SD_CLK_noedge_negedge    :	VitalDelayType := 0.000 ns;
      tsetup_LD_CLK_noedge_negedge   :	VitalDelayType := 0.200 ns;
      thold_LD_CLK_noedge_negedge    :	VitalDelayType := 0.000 ns;
      tperiod_CLK_negedge            :	VitalDelayType := 0.000 ns;
      tpw_CLK_negedge                :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_SD_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_LD_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SD                             :	in    STD_ULOGIC;
      LD                             :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFLSH_1 : entity is TRUE;
end DFFLSH_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFLSH_1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL SD_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL LD_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (LD_ipd, LD, tipd_LD);
   VitalWireDelay (SD_ipd, SD, tipd_SD);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (SD_CLK_dly, SD_ipd, tisd_SD_CLK);
   VitalSignalDelay (LD_CLK_dly, LD_ipd, tisd_LD_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CLK_dly, D_CLK_dly, SD_CLK_dly, LD_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_SD_CLK_negedge	: STD_ULOGIC := '0';
   VARIABLE Tviol_LD_CLK_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_LD_CLK_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK	: STD_ULOGIC := '0';
   VARIABLE Tmkr_SD_CLK_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE PInfo_CLK	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE D_SD_MUX : STD_ULOGIC := 'X';
   VARIABLE CLK_inverted : STD_ULOGIC := '0';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_negedge,
          TimingData              => Tmkr_D_CLK_negedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_negedge,
          SetupLow                => tsetup_D_CLK_noedge_negedge,
          HoldHigh                => thold_D_CLK_noedge_negedge,
          HoldLow                 => thold_D_CLK_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFLSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_SD_CLK_negedge,
          TimingData              => Tmkr_SD_CLK_negedge,
          TestSignal              => SD_CLK_dly,
          TestSignalName          => "SD",
          TestDelay               => tisd_SD_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_SD_CLK_noedge_negedge,
          SetupLow                => tsetup_SD_CLK_noedge_negedge,
          HoldHigh                => thold_SD_CLK_noedge_negedge,
          HoldLow                 => thold_SD_CLK_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFLSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_LD_CLK_negedge,
          TimingData              => Tmkr_LD_CLK_negedge,
          TestSignal              => LD_CLK_dly,
          TestSignalName          => "LD",
          TestDelay               => tisd_LD_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_LD_CLK_noedge_negedge,
          SetupLow                => tsetup_LD_CLK_noedge_negedge,
          HoldHigh                => thold_LD_CLK_noedge_negedge,
          HoldLow                 => thold_LD_CLK_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFLSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_negedge,
          PulseWidthHigh          => tpw_CLK_negedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/DFFLSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      CLK_inverted := VitalINV(CLK_dly);
      D_SD_MUX := VitalMUX2
		     (data0 => D_CLK_dly, 
		      data1 => SD_CLK_dly,
		      dselect => LD_CLK_dly);
      Violation := Tviol_D_CLK_negedge or Pviol_CLK;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dfftab,
        DataIn => (
               D_SD_MUX, CLK_inverted, '1','1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFLSH_1_VITAL of DFFLSH_1 is 
        for VITAL
        end for; 
end CFG_DFFLSH_1_VITAL;

----- VITAL model for cell DFFCBLSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCBLSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_SD_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_SD_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_LD_CLK_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_LD_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      thold_CE_CLK_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_posedge        :	VitalDelayType := 0.000 ns;
      tperiod_CLK_posedge            :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_SD_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_LD_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SD                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LD                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      SD                              :	in    STD_ULOGIC;
      LD                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCBLSH : entity is TRUE;
end DFFCBLSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCBLSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	         : STD_ULOGIC := 'X';
   SIGNAL SD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL SD_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL LD_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SD_ipd, SD, tipd_SD);
   VitalWireDelay (LD_ipd, LD, tipd_LD);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (SD_CLK_dly, SD_ipd, tisd_SD_CLK);
   VitalSignalDelay (LD_CLK_dly, LD_ipd, tisd_LD_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, SD_CLK_dly, LD_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_SD_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_SD_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_LD_CLK_CE_EQ_1_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_LD_CLK_CE_EQ_1_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_posedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_posedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE D_MUX_SD : STD_ULOGIC := '0';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_posedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_posedge,
          SetupLow                => tsetup_D_CLK_noedge_posedge,
          HoldHigh                => thold_D_CLK_noedge_posedge,
          HoldLow                 => thold_D_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBLSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_SD_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_SD_CLK_CE_EQ_1_posedge,
          TestSignal              => SD_CLK_dly,
          TestSignalName          => "SD",
          TestDelay               => tisd_SD_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_SD_CLK_noedge_posedge,
          SetupLow                => tsetup_SD_CLK_noedge_posedge,
          HoldHigh                => thold_SD_CLK_noedge_posedge,
          HoldLow                 => thold_SD_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBLSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_LD_CLK_CE_EQ_1_posedge,
          TimingData              => Tmkr_LD_CLK_CE_EQ_1_posedge,
          TestSignal              => LD_CLK_dly,
          TestSignalName          => "LD",
          TestDelay               => tisd_LD_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_LD_CLK_noedge_posedge,
          SetupLow                => tsetup_LD_CLK_noedge_posedge,
          HoldHigh                => thold_LD_CLK_noedge_posedge,
          HoldLow                 => thold_LD_CLK_noedge_posedge,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBLSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_posedge,
          TimingData              => Tmkr_CE_CLK_posedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_posedge,
          SetupLow                => tsetup_CE_CLK_noedge_posedge,
          HoldHigh                => thold_CE_CLK_noedge_posedge,
          HoldLow                 => thold_CE_CLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DFFCBLSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1,
          PeriodData              => PInfo_CLK_CE_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_posedge,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          HeaderMsg               => InstancePath & "/DFFCBLSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      D_MUX_SD := VitalMUX2(
			    data0 => D_CLK_dly,
			    data1 => SD_CLK_dly,
			    dselect => LD_CLK_dly);
      Violation := Tviol_D_CLK_CE_EQ_1_posedge or Tviol_CE_CLK_posedge or Pviol_CLK_CE_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_MUX_SD, CLK_dly,'1','1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCBLSH_VITAL of DFFCBLSH is 
        for VITAL
        end for; 
end CFG_DFFCBLSH_VITAL;

----- VITAL model for cell DFFCBLSH_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DFFCBLSH_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_CLK_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_CLK_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_D_CLK_noedge_negedge :	VitalDelayType := 0.000 ns;
      tsetup_SD_CLK_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_SD_CLK_noedge_negedge :	VitalDelayType := 0.000 ns;
      tsetup_LD_CLK_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_LD_CLK_noedge_negedge :	VitalDelayType := 0.000 ns;
      tsetup_CE_CLK_noedge_negedge :	VitalDelayType := 0.000 ns;
      thold_CE_CLK_noedge_negedge :	VitalDelayType := 0.000 ns;
      tpw_CLK_negedge        :	VitalDelayType := 0.000 ns;
      tperiod_CLK_negedge            :	VitalDelayType := 0.000 ns;
      ticd_CLK                       :	VitalDelayType := 0.000 ns;
      tisd_D_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_SD_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_LD_CLK                     :	VitalDelayType := 0.000 ns;
      tisd_CE_CLK                     :	VitalDelayType := 0.000 ns;
      tipd_CE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SD                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LD                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CE                             :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      SD                              :	in    STD_ULOGIC;
      LD                              :	in    STD_ULOGIC;
      CLK                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DFFCBLSH_1 : entity is TRUE;
end DFFCBLSH_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DFFCBLSH_1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D_ipd	         : STD_ULOGIC := 'X';
   SIGNAL SD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL SD_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL LD_CLK_dly	 : STD_ULOGIC := 'X';
   SIGNAL CE_CLK_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CE_ipd, CE, tipd_CE);
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SD_ipd, SD, tipd_SD);
   VitalWireDelay (LD_ipd, LD, tipd_LD);
   VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK);
   VitalSignalDelay (D_CLK_dly, D_ipd, tisd_D_CLK);
   VitalSignalDelay (SD_CLK_dly, SD_ipd, tisd_SD_CLK);
   VitalSignalDelay (LD_CLK_dly, LD_ipd, tisd_LD_CLK);
   VitalSignalDelay (CE_CLK_dly, CE_ipd, tisd_CE_CLK);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CE_ipd, CLK_dly, D_CLK_dly, SD_CLK_dly, LD_CLK_dly, CE_CLK_dly)

   -- timing check results
   VARIABLE Tviol_D_CLK_CE_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_CLK_CE_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_SD_CLK_CE_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_SD_CLK_CE_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_LD_CLK_CE_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_LD_CLK_CE_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_CE_CLK_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_CE_CLK_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_CLK_CE_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_CLK_CE_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 4);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE D_MUX_SD : STD_ULOGIC := '0';
   VARIABLE CLK_inverted : STD_ULOGIC := '0';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_CLK_CE_EQ_1_negedge,
          TimingData              => Tmkr_D_CLK_CE_EQ_1_negedge,
          TestSignal              => D_CLK_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_D_CLK_noedge_negedge,
          SetupLow                => tsetup_D_CLK_noedge_negedge,
          HoldHigh                => thold_D_CLK_noedge_negedge,
          HoldLow                 => thold_D_CLK_noedge_negedge,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBLSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_SD_CLK_CE_EQ_1_negedge,
          TimingData              => Tmkr_SD_CLK_CE_EQ_1_negedge,
          TestSignal              => SD_CLK_dly,
          TestSignalName          => "SD",
          TestDelay               => tisd_SD_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_SD_CLK_noedge_negedge,
          SetupLow                => tsetup_SD_CLK_noedge_negedge,
          HoldHigh                => thold_SD_CLK_noedge_negedge,
          HoldLow                 => thold_SD_CLK_noedge_negedge,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBLSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_LD_CLK_CE_EQ_1_negedge,
          TimingData              => Tmkr_LD_CLK_CE_EQ_1_negedge,
          TestSignal              => LD_CLK_dly,
          TestSignalName          => "LD",
          TestDelay               => tisd_LD_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_LD_CLK_noedge_negedge,
          SetupLow                => tsetup_LD_CLK_noedge_negedge,
          HoldHigh                => thold_LD_CLK_noedge_negedge,
          HoldLow                 => thold_LD_CLK_noedge_negedge,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBLSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_CLK_negedge,
          TimingData              => Tmkr_CE_CLK_negedge,
          TestSignal              => CE_CLK_dly,
          TestSignalName          => "CE",
          TestDelay               => tisd_CE_CLK,
          RefSignal               => CLK_dly,
          RefSignalName          => "CLK",
          RefDelay                => ticd_CLK,
          SetupHigh               => tsetup_CE_CLK_noedge_negedge,
          SetupLow                => tsetup_CE_CLK_noedge_negedge,
          HoldHigh                => thold_CE_CLK_noedge_negedge,
          HoldLow                 => thold_CE_CLK_noedge_negedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DFFCBLSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK_CE_EQ_1,
          PeriodData              => PInfo_CLK_CE_EQ_1,
          TestSignal              => CLK_dly,
          TestSignalName          => "CLK",
          TestDelay               => ticd_CLK,
          Period                  => tperiod_CLK_negedge,
          PulseWidthHigh          => tpw_CLK_negedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(CE_ipd) = '0',
          HeaderMsg               => InstancePath & "/DFFCBLSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      CLK_inverted := VitalINV(CLK_dly);
      D_MUX_SD := VitalMUX2(
			    data0 => D_CLK_dly,
			    data1 => SD_CLK_dly,
			    dselect => LD_CLK_dly);
      Violation := Tviol_D_CLK_CE_EQ_1_negedge or Tviol_CE_CLK_negedge or Pviol_CLK_CE_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => dffcebtab,
        DataIn => (
               D_MUX_SD, CLK_inverted,'1','1', CE_CLK_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (CLK_dly'last_event, tpd_CLK_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DFFCBLSH_1_VITAL of DFFCBLSH_1 is 
        for VITAL
        end for; 
end CFG_DFFCBLSH_1_VITAL;



----- VITAL model for cell DLAT -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;


-- entity declaration --
entity DLAT is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_LAT_noedge_negedge    :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_negedge     :	VitalDelayType := 0.000 ns;
      tperiod_LAT_posedge            :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge                :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLAT : entity is TRUE;
end DLAT;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DLAT is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_negedge,
          TimingData              => Tmkr_D_LAT_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_negedge,
          SetupLow                => tsetup_D_LAT_noedge_negedge,
          HoldHigh                => thold_D_LAT_noedge_negedge,
          HoldLow                 => thold_D_LAT_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLAT",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT,
          PeriodData              => PInfo_LAT,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/DLAT",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_LAT_negedge or Pviol_LAT;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_LAT_dly, LAT_dly,'1','1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLAT_VITAL of DLAT is 
        for VITAL
        end for; 
end CFG_DLAT_VITAL;


----- VITAL model for cell DLAT_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;


-- entity declaration --
entity DLAT_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_LAT_noedge_posedge    :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_posedge     :	VitalDelayType := 0.000 ns;
      tperiod_LAT_posedge            :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge                :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLAT_1 : entity is TRUE;
end DLAT_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DLAT_1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   VARIABLE LAT_inverted : STD_ULOGIC := 'X';
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_negedge,
          TimingData              => Tmkr_D_LAT_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName           => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_posedge,
          SetupLow                => tsetup_D_LAT_noedge_posedge,
          HoldHigh                => thold_D_LAT_noedge_posedge,
          HoldLow                 => thold_D_LAT_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DLAT_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT,
          PeriodData              => PInfo_LAT,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/DLAT_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_LAT_negedge or Pviol_LAT;
      LAT_inverted := (NOT LAT_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_LAT_dly, LAT_inverted,'1','1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLAT_1_VITAL of DLAT_1 is 
        for VITAL
        end for; 
end CFG_DLAT_1_VITAL;



----- VITAL model for cell DLATR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DLATR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_R_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_LAT_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_negedge :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge         :	VitalDelayType := 0.000 ns;
      tperiod_LAT_posedge             :	VitalDelayType := 0.000 ns;
      trecovery_R_LAT_posedge_negedge :	VitalDelayType := 0.100 ns;
      thold_R_LAT_posedge_negedge    :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_R_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATR : entity is TRUE;
end DLATR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DLATR is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   VitalWireDelay (R_ipd, R, tipd_R);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (R_LAT_dly, R_ipd, tisd_R_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, R_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_R_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_R_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT_R_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT_R_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_R_EQ_1_negedge,
          TimingData              => Tmkr_D_LAT_R_EQ_1_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_negedge,
          SetupLow                => tsetup_D_LAT_noedge_negedge,
          HoldHigh                => thold_D_LAT_noedge_negedge,
          HoldLow                 => thold_D_LAT_noedge_negedge,
          CheckEnabled            => TO_X01(R_LAT_dly) = '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_LAT_negedge,
          TimingData              => Tmkr_R_LAT_negedge,
          TestSignal              => R_LAT_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          Recovery                => trecovery_R_LAT_posedge_negedge,
          Removal                 => thold_R_LAT_posedge_negedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT_R_EQ_1,
          PeriodData              => PInfo_LAT_R_EQ_1,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(R_LAT_dly ) = '1',
          HeaderMsg               => InstancePath & "/DLATR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_LAT_R_EQ_1_negedge or Tviol_R_LAT_negedge or Pviol_LAT_R_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_LAT_dly, LAT_dly, R_LAT_dly,'1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE),
                 2 => (R_LAT_dly'last_event, tpd_R_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATR_VITAL of DLATR is 
        for VITAL
        end for; 
end CFG_DLATR_VITAL;

----- VITAL model for cell DLATRH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DLATRH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_R_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_LAT_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_negedge :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge         :	VitalDelayType := 0.000 ns;
      tpw_R_posedge         :	VitalDelayType := 0.000 ns;
      tperiod_LAT_posedge             :	VitalDelayType := 0.000 ns;
      trecovery_R_LAT_negedge_negedge :	VitalDelayType := 0.100 ns;
      thold_R_LAT_negedge_negedge    :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_R_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATRH : entity is TRUE;
end DLATRH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DLATRH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   VitalWireDelay (R_ipd, R, tipd_R);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (R_LAT_dly, R_ipd, tisd_R_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, R_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_R_EQ_0_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_R_EQ_0_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT_R_EQ_0	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT_R_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE R_inverted : STD_ULOGIC := 'X';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_R_EQ_0_negedge,
          TimingData              => Tmkr_D_LAT_R_EQ_0_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_negedge,
          SetupLow                => tsetup_D_LAT_noedge_negedge,
          HoldHigh                => thold_D_LAT_noedge_negedge,
          HoldLow                 => thold_D_LAT_noedge_negedge,
          CheckEnabled            => TO_X01((R_LAT_dly)) = '0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_LAT_negedge,
          TimingData              => Tmkr_R_LAT_negedge,
          TestSignal              => R_LAT_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          Recovery                => trecovery_R_LAT_negedge_negedge,
          Removal                 => thold_R_LAT_negedge_negedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT_R_EQ_0,
          PeriodData              => PInfo_LAT_R_EQ_0,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01((R_LAT_dly) ) = '0',
          HeaderMsg               => InstancePath & "/DLATRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_LAT_R_EQ_0_negedge or Tviol_R_LAT_negedge or Pviol_LAT_R_EQ_0;
      R_inverted := (NOT R_LAT_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_LAT_dly, LAT_dly,R_inverted,'1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE),
                 2 => (R_LAT_dly'last_event, tpd_R_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATRH_VITAL of DLATRH is 
        for VITAL
        end for; 
end CFG_DLATRH_VITAL;


----- VITAL model for cell DLATRH_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DLATRH_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_R_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_LAT_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge         :	VitalDelayType := 0.000 ns;
      tpw_R_posedge         :	VitalDelayType := 0.000 ns;
      tperiod_LAT_posedge             :	VitalDelayType := 0.000 ns;
      trecovery_R_LAT_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_R_LAT_negedge_posedge    :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_R_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_R                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      R                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATRH_1 : entity is TRUE;
end DLATRH_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DLATRH_1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL R_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL R_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   VitalWireDelay (R_ipd, R, tipd_R);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (R_LAT_dly, R_ipd, tisd_R_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, R_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_R_EQ_0_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_R_EQ_0_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_R_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_R_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT_R_EQ_0	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT_R_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE R_inverted : STD_ULOGIC := 'X';
   VARIABLE LAT_inverted : STD_ULOGIC := 'X';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_R_EQ_0_negedge,
          TimingData              => Tmkr_D_LAT_R_EQ_0_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_posedge,
          SetupLow                => tsetup_D_LAT_noedge_posedge,
          HoldHigh                => thold_D_LAT_noedge_posedge,
          HoldLow                 => thold_D_LAT_noedge_posedge,
          CheckEnabled            => TO_X01((R_LAT_dly)) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DLATRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_R_LAT_negedge,
          TimingData              => Tmkr_R_LAT_negedge,
          TestSignal              => R_LAT_dly,
          TestSignalName          => "R",
          TestDelay               => tisd_R_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          Recovery                => trecovery_R_LAT_negedge_posedge,
          Removal                 => thold_R_LAT_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DLATRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT_R_EQ_0,
          PeriodData              => PInfo_LAT_R_EQ_0,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01((R_LAT_dly) ) = '0',
          HeaderMsg               => InstancePath & "/DLATRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_LAT_R_EQ_0_negedge or Tviol_R_LAT_negedge or Pviol_LAT_R_EQ_0;
      R_inverted := (NOT R_LAT_dly);
      LAT_inverted := (NOT LAT_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_LAT_dly, LAT_inverted, R_inverted,'1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE),
                 2 => (R_LAT_dly'last_event, tpd_R_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATRH_1_VITAL of DLATRH_1 is 
        for VITAL
        end for; 
end CFG_DLATRH_1_VITAL;


----- VITAL model for cell DLATSRH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;


-- entity declaration --
entity DLATSRH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_SR_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_LAT_noedge_negedge    :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_negedge     :	VitalDelayType := 0.000 ns;
      tsetup_SR_LAT_noedge_negedge    :	VitalDelayType := 0.100 ns;
      thold_SR_LAT_noedge_negedge     :	VitalDelayType := 0.000 ns;
      tperiod_LAT_posedge            :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge                :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_SR_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SR                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SR                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATSRH : entity is TRUE;
end DLATSRH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DLATSRH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SR_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL SR_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SR_ipd, SR, tipd_SR);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (SR_LAT_dly, SR_ipd, tisd_SR_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, SR_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_SR_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_SR_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE D_in_zd : STD_ULOGIC := '0';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_negedge,
          TimingData              => Tmkr_D_LAT_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_negedge,
          SetupLow                => tsetup_D_LAT_noedge_negedge,
          HoldHigh                => thold_D_LAT_noedge_negedge,
          HoldLow                 => thold_D_LAT_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATSRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_SR_LAT_negedge,
          TimingData              => Tmkr_SR_LAT_negedge,
          TestSignal              => SR_LAT_dly,
          TestSignalName          => "SR",
          TestDelay               => tisd_SR_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_SR_LAT_noedge_negedge,
          SetupLow                => tsetup_SR_LAT_noedge_negedge,
          HoldHigh                => thold_SR_LAT_noedge_negedge,
          HoldLow                 => thold_SR_LAT_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATSRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT,
          PeriodData              => PInfo_LAT,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/DLATSRH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      D_in_zd := VitalAND2(NOT(SR_LAT_dly), D_LAT_dly);
      Violation := Tviol_D_LAT_negedge or Pviol_LAT or Tviol_SR_LAT_negedge;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_in_zd, LAT_dly,'1','1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATSRH_VITAL of DLATSRH is 
        for VITAL
        end for; 
end CFG_DLATSRH_VITAL;

----- VITAL model for cell DLATSRH_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;


-- entity declaration --
entity DLATSRH_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_LAT_noedge_posedge    :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_posedge     :	VitalDelayType := 0.000 ns;
      tsetup_SR_LAT_noedge_posedge    :	VitalDelayType := 0.100 ns;
      thold_SR_LAT_noedge_posedge     :	VitalDelayType := 0.000 ns;
      tperiod_LAT_posedge            :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge                :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_SR_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SR                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SR                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATSRH_1 : entity is TRUE;
end DLATSRH_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DLATSRH_1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SR_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL SR_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SR_ipd, SR, tipd_SR);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (SR_LAT_dly, SR_ipd, tisd_SR_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, SR_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_SR_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_SR_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE D_in_zd : STD_ULOGIC := '0';
   VARIABLE LAT_inverted : STD_ULOGIC := 'X';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_negedge,
          TimingData              => Tmkr_D_LAT_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName           => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_posedge,
          SetupLow                => tsetup_D_LAT_noedge_posedge,
          HoldHigh                => thold_D_LAT_noedge_posedge,
          HoldLow                 => thold_D_LAT_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATSRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_SR_LAT_negedge,
          TimingData              => Tmkr_SR_LAT_negedge,
          TestSignal              => SR_LAT_dly,
          TestSignalName          => "SR",
          TestDelay               => tisd_SR_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_SR_LAT_noedge_posedge,
          SetupLow                => tsetup_SR_LAT_noedge_posedge,
          HoldHigh                => thold_SR_LAT_noedge_posedge,
          HoldLow                 => thold_SR_LAT_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATSRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT,
          PeriodData              => PInfo_LAT,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/DLATSRH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      D_in_zd := VitalAND2(NOT(SR_LAT_dly),  D_LAT_dly);
      LAT_inverted := NOT(LAT_dly);
      Violation := Tviol_D_LAT_negedge or Pviol_LAT or Tviol_SR_LAT_negedge;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_in_zd, LAT_inverted,'1','1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATSRH_1_VITAL of DLATSRH_1 is 
        for VITAL
        end for; 
end CFG_DLATSRH_1_VITAL;



----- VITAL model for cell DLATS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DLATS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_LAT_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_negedge :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge         :	VitalDelayType := 0.000 ns;
      tperiod_LAT_posedge             :	VitalDelayType := 0.000 ns;
      trecovery_S_LAT_posedge_negedge :	VitalDelayType := 0.100 ns;
      thold_S_LAT_posedge_negedge    :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_S_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATS : entity is TRUE;
end DLATS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DLATS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (S_LAT_dly, S_ipd, tisd_S_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, S_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_S_EQ_1_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_S_EQ_1_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT_S_EQ_1	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT_S_EQ_1	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_S_EQ_1_negedge,
          TimingData              => Tmkr_D_LAT_S_EQ_1_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_negedge,
          SetupLow                => tsetup_D_LAT_noedge_negedge,
          HoldHigh                => thold_D_LAT_noedge_negedge,
          HoldLow                 => thold_D_LAT_noedge_negedge,
          CheckEnabled            => TO_X01(S_LAT_dly) = '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_LAT_negedge,
          TimingData              => Tmkr_S_LAT_negedge,
          TestSignal              => S_LAT_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          Recovery                => trecovery_S_LAT_posedge_negedge,
          Removal                 => thold_S_LAT_posedge_negedge,
          ActiveLow               => TRUE,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT_S_EQ_1,
          PeriodData              => PInfo_LAT_S_EQ_1,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01(S_LAT_dly ) = '1',
          HeaderMsg               => InstancePath & "/DLATS",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_LAT_S_EQ_1_negedge or Tviol_S_LAT_negedge or Pviol_LAT_S_EQ_1;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_LAT_dly, LAT_dly,'1', S_LAT_dly));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE),
                 2 => (S_LAT_dly'last_event, tpd_S_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATS_VITAL of DLATS is 
        for VITAL
        end for; 
end CFG_DLATS_VITAL;

----- VITAL model for cell DLATSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DLATSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_LAT_noedge_negedge :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_negedge :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge         :	VitalDelayType := 0.000 ns;
      tpw_S_posedge         :	VitalDelayType := 0.000 ns;
      tperiod_LAT_posedge             :	VitalDelayType := 0.000 ns;
      trecovery_S_LAT_negedge_negedge :	VitalDelayType := 0.100 ns;
      thold_S_LAT_negedge_negedge    :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_S_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATSH : entity is TRUE;
end DLATSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DLATSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (S_LAT_dly, S_ipd, tisd_S_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, S_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_S_EQ_0_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_S_EQ_0_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_S	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE S_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_S_EQ_0_negedge,
          TimingData              => Tmkr_D_LAT_S_EQ_0_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_negedge,
          SetupLow                => tsetup_D_LAT_noedge_negedge,
          HoldHigh                => thold_D_LAT_noedge_negedge,
          HoldLow                 => thold_D_LAT_noedge_negedge,
          CheckEnabled            => TO_X01((S_LAT_dly)) = '0',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_LAT_negedge,
          TimingData              => Tmkr_S_LAT_negedge,
          TestSignal              => S_LAT_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          Recovery                => trecovery_S_LAT_negedge_negedge,
          Removal                 => thold_S_LAT_negedge_negedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_LAT_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_LAT,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DLATSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT_S_EQ_0,
          PeriodData              => PInfo_LAT_S_EQ_0,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01((S_LAT_dly) ) = '0',
          HeaderMsg               => InstancePath & "/DLATSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_LAT_S_EQ_0_negedge or Tviol_S_LAT_negedge or Pviol_LAT_S_EQ_0 or Pviol_S;
      S_inverted := (NOT S_LAT_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_LAT_dly, LAT_dly, '1',S_inverted));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE),
                 2 => (S_LAT_dly'last_event, tpd_S_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATSH_VITAL of DLATSH is 
        for VITAL
        end for; 
end CFG_DLATSH_VITAL;


----- VITAL model for cell DLATSH_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;



-- entity declaration --
entity DLATSH_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_LAT_noedge_posedge :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_posedge :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge         :	VitalDelayType := 0.000 ns;
      tpw_S_posedge         :	VitalDelayType := 0.000 ns;
      tperiod_LAT_posedge             :	VitalDelayType := 0.000 ns;
      trecovery_S_LAT_negedge_posedge :	VitalDelayType := 0.100 ns;
      thold_S_LAT_negedge_posedge    :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_S_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      S                              :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATSH_1 : entity is TRUE;
end DLATSH_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DLATSH_1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL S_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   VitalWireDelay (S_ipd, S, tipd_S);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (S_LAT_dly, S_ipd, tisd_S_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, S_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_S_EQ_0_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_S_EQ_0_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_S_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_S_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT_S_EQ_0	: STD_ULOGIC := '0';
   VARIABLE Pviol_S	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT_S_EQ_0	: VitalPeriodDataType := VitalPeriodDataInit;
   VARIABLE PInfo_S	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE S_inverted : STD_ULOGIC := 'X';
   VARIABLE LAT_inverted : STD_ULOGIC := 'X';
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_S_EQ_0_negedge,
          TimingData              => Tmkr_D_LAT_S_EQ_0_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_posedge,
          SetupLow                => tsetup_D_LAT_noedge_posedge,
          HoldHigh                => thold_D_LAT_noedge_posedge,
          HoldLow                 => thold_D_LAT_noedge_posedge,
          CheckEnabled            => TO_X01((S_LAT_dly)) = '0',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DLATSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalRecoveryRemovalCheck (
          Violation               => Tviol_S_LAT_negedge,
          TimingData              => Tmkr_S_LAT_negedge,
          TestSignal              => S_LAT_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          Recovery                => trecovery_S_LAT_negedge_posedge,
          Removal                 => thold_S_LAT_negedge_posedge,
          ActiveLow               => FALSE,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/DLATSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_S,
          PeriodData              => PInfo_S,
          TestSignal              => S_LAT_dly,
          TestSignalName          => "S",
          TestDelay               => tisd_S_LAT,
          Period                  => 0 ns,
          PulseWidthHigh          => 0 ns,
          PulseWidthLow           => tpw_S_posedge,
          CheckEnabled            => TRUE, 
          HeaderMsg               => InstancePath & "/DLATSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT_S_EQ_0,
          PeriodData              => PInfo_LAT_S_EQ_0,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TO_X01((S_LAT_dly) ) = '0',
          HeaderMsg               => InstancePath & "/DLATSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      Violation := Tviol_D_LAT_S_EQ_0_negedge or Tviol_S_LAT_negedge or Pviol_LAT_S_EQ_0 or Pviol_S;
      S_inverted := (NOT S_LAT_dly);
      LAT_inverted := (NOT LAT_dly);
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_LAT_dly, LAT_inverted, '1',S_inverted));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE),
                 2 => (S_LAT_dly'last_event, tpd_S_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATSH_1_VITAL of DLATSH_1 is 
        for VITAL
        end for; 
end CFG_DLATSH_1_VITAL;

----- VITAL model for cell DLATSSH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;


-- entity declaration --
entity DLATSSH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_SS_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_LAT_noedge_negedge    :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_negedge     :	VitalDelayType := 0.000 ns;
      tsetup_SS_LAT_noedge_negedge    :	VitalDelayType := 0.100 ns;
      thold_SS_LAT_noedge_negedge     :	VitalDelayType := 0.000 ns;
      tperiod_LAT_posedge            :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge                :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_SS_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SS                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SS                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATSSH : entity is TRUE;
end DLATSSH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DLATSSH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SS_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL SS_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SS_ipd, SS, tipd_SS);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (SS_LAT_dly, SS_ipd, tisd_SS_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, SS_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE D_in_zd : STD_ULOGIC := '0';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_negedge,
          TimingData              => Tmkr_D_LAT_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_negedge,
          SetupLow                => tsetup_D_LAT_noedge_negedge,
          HoldHigh                => thold_D_LAT_noedge_negedge,
          HoldLow                 => thold_D_LAT_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT,
          PeriodData              => PInfo_LAT,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/DLATSSH",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      D_in_zd := VitalOR2(SS_LAT_dly , D_LAT_dly);
      Violation := Tviol_D_LAT_negedge or Pviol_LAT;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_in_zd, LAT_dly,'1','1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATSSH_VITAL of DLATSSH is 
        for VITAL
        end for; 
end CFG_DLATSSH_VITAL;

----- VITAL model for cell DLATSSH_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

LIBRARY LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;


-- entity declaration --
entity DLATSSH_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_D_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_SS_Q                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LAT_Q                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tsetup_D_LAT_noedge_posedge    :	VitalDelayType := 0.100 ns;
      thold_D_LAT_noedge_posedge     :	VitalDelayType := 0.000 ns;
      tsetup_SS_LAT_noedge_posedge    :	VitalDelayType := 0.100 ns;
      thold_SS_LAT_noedge_posedge     :	VitalDelayType := 0.000 ns;
      tperiod_LAT_posedge            :	VitalDelayType := 0.000 ns;
      tpw_LAT_posedge                :	VitalDelayType := 0.000 ns;
      ticd_LAT                       :	VitalDelayType := 0.000 ns;
      tisd_D_LAT                     :	VitalDelayType := 0.000 ns;
      tisd_SS_LAT                     :	VitalDelayType := 0.000 ns;
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SS                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LAT                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SS                              :	in    STD_ULOGIC;
      LAT                            :	in    STD_ULOGIC;
      Q                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DLATSSH_1 : entity is TRUE;
end DLATSSH_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of DLATSSH_1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SS_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL D_LAT_dly	 : STD_ULOGIC := 'X';
   SIGNAL SS_LAT_dly	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SS_ipd, SS, tipd_SS);
   VitalWireDelay (LAT_ipd, LAT, tipd_LAT);
   end block;
   ----------------------
   --  INPUT SIGNAL DELAYs
   ----------------------
   SignalDelay : block
   begin
   VitalSignalDelay (LAT_dly, LAT_ipd, ticd_LAT);
   VitalSignalDelay (D_LAT_dly, D_ipd, tisd_D_LAT);
   VitalSignalDelay (SS_LAT_dly, SS_ipd, tisd_SS_LAT);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (LAT_dly, D_LAT_dly, SS_LAT_dly)

   -- timing check results
   VARIABLE Tviol_D_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_D_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Tviol_SS_LAT_negedge	: STD_ULOGIC := '0';
   VARIABLE Tmkr_SS_LAT_negedge	: VitalTimingDataType := VitalTimingDataInit;
   VARIABLE Pviol_LAT	: STD_ULOGIC := '0';
   VARIABLE PInfo_LAT	: VitalPeriodDataType := VitalPeriodDataInit;

   -- functionality results
   VARIABLE Violation : STD_ULOGIC := '0';
   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 3);
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS Q_zd : STD_LOGIC is Results(1);
   VARIABLE D_in_zd : STD_ULOGIC := '0';
   VARIABLE LAT_inverted : STD_ULOGIC := '0';

   -- output glitch detection variables
   VARIABLE Q_GlitchData	: VitalGlitchDataType;

   begin

      ------------------------
      --  Timing Check Section
      ------------------------
      if (TimingChecksOn) then
         VitalSetupHoldCheck (
          Violation               => Tviol_D_LAT_negedge,
          TimingData              => Tmkr_D_LAT_negedge,
          TestSignal              => D_LAT_dly,
          TestSignalName          => "D",
          TestDelay               => tisd_D_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_D_LAT_noedge_posedge,
          SetupLow                => tsetup_D_LAT_noedge_posedge,
          HoldHigh                => thold_D_LAT_noedge_posedge,
          HoldLow                 => thold_D_LAT_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATSSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_SS_LAT_negedge,
          TimingData              => Tmkr_SS_LAT_negedge,
          TestSignal              => SS_LAT_dly,
          TestSignalName          => "SS",
          TestDelay               => tisd_SS_LAT,
          RefSignal               => LAT_dly,
          RefSignalName          => "LAT",
          RefDelay                => ticd_LAT,
          SetupHigh               => tsetup_SS_LAT_noedge_posedge,
          SetupLow                => tsetup_SS_LAT_noedge_posedge,
          HoldHigh                => thold_SS_LAT_noedge_posedge,
          HoldLow                 => thold_SS_LAT_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/DLATSSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalPeriodPulseCheck (
          Violation               => Pviol_LAT,
          PeriodData              => PInfo_LAT,
          TestSignal              => LAT_dly,
          TestSignalName          => "LAT",
          TestDelay               => ticd_LAT,
          Period                  => tperiod_LAT_posedge,
          PulseWidthHigh          => tpw_LAT_posedge,
          PulseWidthLow           => 0 ns,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/DLATSSH_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

      -------------------------
      --  Functionality Section
      -------------------------
      LAT_inverted := VitalINV(LAT_dly);
      D_in_zd := VitalOR2(SS_LAT_dly , D_LAT_dly);
      Violation := Tviol_D_LAT_negedge or Pviol_LAT;
      VitalStateTable(
        Result => Q_zd,
        PreviousDataIn => PrevData_Q,
        StateTable => latchtab,
        DataIn => (
               D_in_zd, LAT_inverted,'1','1'));
      Q_zd := Violation XOR Q_zd;

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Q,
       GlitchData => Q_GlitchData,
       OutSignalName => "Q",
       OutTemp => Q_zd,
       Paths => (0 => (D_LAT_dly'last_event, tpd_D_Q, TRUE),
                 1 => (LAT_dly'last_event, tpd_LAT_Q, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_DLATSSH_1_VITAL of DLATSSH_1 is 
        for VITAL
        end for; 
end CFG_DLATSSH_1_VITAL;

----- VITAL model for cell LUT1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LUT1 is
   generic(
      TimingChecksOn: Boolean := TRUE;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      INIT                           :	bit_vector);

   port(
      O                              :	out   STD_ULOGIC;
      I0                             :	in    STD_ULOGIC);
attribute VITAL_LEVEL0 of LUT1 : entity is TRUE;
end LUT1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of LUT1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalMUX
                 (data => To_StdLogicVector(INIT),
                  dselect => (0 => I0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnEvent,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_LUT1_V of LUT1 is
   for VITAL 
   end for;
end CFG_LUT1_V;


----- VITAL model for cell LUT2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LUT2 is
   generic(
      TimingChecksOn: Boolean := TRUE;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      INIT                           :	bit_vector);

   port(
      O                              :	out   STD_ULOGIC;
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC);
attribute VITAL_LEVEL0 of LUT2 : entity is TRUE;
end LUT2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of LUT2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalMUX
                 (data => To_StdLogicVector(INIT),
                  dselect => (I1_ipd, I0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE)),
       Mode => OnEvent,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_LUT2_V of LUT2 is
   for VITAL 
   end for;
end CFG_LUT2_V;

----- CELL LUT3 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LUT3 is
   generic(
      TimingChecksOn: Boolean := TRUE;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      INIT                           :	bit_vector);

   port(
      O                              :	out   STD_ULOGIC;
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC);
attribute VITAL_LEVEL0 of LUT3 : entity is TRUE;
end LUT3;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of LUT3 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalMUX
                 (data => To_StdLogicVector(INIT),
                  dselect => (I2_ipd, I1_ipd, I0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE)),
       Mode => OnEvent,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_LUT3_V of LUT3 is
   for VITAL
   end for;
end CFG_LUT3_V;

----- CELL LUT4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LUT4 is
   generic(
      TimingChecksOn: Boolean := TRUE;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      INIT                           :	bit_vector);

   port(
      O                              :	out   STD_ULOGIC;
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC);
attribute VITAL_LEVEL0 of LUT4 : entity is TRUE;
end LUT4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
architecture VITAL of LUT4 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalMUX
                 (data => To_StdLogicVector(INIT),
                  dselect => (I3_ipd, I2_ipd, I1_ipd, I0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE)),
       Mode => OnEvent,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_LUT4_V of LUT4 is
   for VITAL
   end for;
end CFG_LUT4_V;

----- CELL LUT5 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LUT5 is
   generic(
      TimingChecksOn: Boolean := TRUE;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      INIT                           :	bit_vector);

   port(
      O                              :	out   STD_ULOGIC;
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC);
attribute VITAL_LEVEL0 of LUT5 : entity is TRUE;
end LUT5;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of LUT5 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalMUX
                 (data => To_StdLogicVector(INIT),
                  dselect => (I4_ipd, I3_ipd, I2_ipd, I1_ipd, I0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I2_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE)),
       Mode => OnEvent,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_LUT5_V of LUT5 is
   for VITAL
   end for;
end CFG_LUT5_V;

----- CELL LUT6 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LUT6 is
   generic(
      TimingChecksOn: Boolean := TRUE;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      INIT                           :	bit_vector);

   port(
      O                              :	out   STD_ULOGIC;
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC);
attribute VITAL_LEVEL0 of LUT6 : entity is TRUE;
end LUT6;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of LUT6 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalMUX
                 (data => To_StdLogicVector(INIT),
                  dselect => (I5_ipd, I4_ipd, I3_ipd, I2_ipd, I1_ipd, I0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I2_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE)),
       Mode => OnEvent,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_LUT6_V of LUT6 is
   for VITAL
   end for;
end CFG_LUT6_V;


----- CELL AS_LSB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity AS_LSB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_A0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_AS_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_AS_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AS                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      AS                             :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of AS_LSB : entity is TRUE;
end AS_LSB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of AS_LSB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';
   SIGNAL AS_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   VitalWireDelay (AS_ipd, AS, tipd_AS);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, B0_ipd, CIN_ipd, AS_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := (B0_ipd) XOR (A0_ipd) XOR (CIN_ipd);
      COUT_zd :=
       (((NOT ((AS_ipd) XOR (CIN_ipd)))) AND (A0_ipd)) OR (((NOT ((AS_ipd)
         XOR (B0_ipd)))) AND (A0_ipd)) OR (((NOT ((AS_ipd) XOR (CIN_ipd))))
         AND ((NOT ((AS_ipd) XOR (B0_ipd)))));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_S0, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_S0, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE),
                 3 => (AS_ipd'last_event, tpd_AS_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE),
                 3 => (AS_ipd'last_event, tpd_AS_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_AS_LSB_VITAL of AS_LSB is
   for VITAL
   end for;
end CFG_AS_LSB_VITAL;


----- CELL BI_DIR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BI_DIR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_OE_IO                      :	VitalDelayType01z := (0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns);
      tpd_I0_IO                      :	VitalDelayType01 := (0.010 ns, 0.010 ns);
      tpd_IO_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_IO                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      IO                             :	inout STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BI_DIR : entity is TRUE;
end BI_DIR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of BI_DIR is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL IO_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   VitalWireDelay (IO_ipd, IO, tipd_IO);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, OE_ipd, IO_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS IO_zd : STD_LOGIC is Results(1);
   ALIAS O_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE IO_GlitchData	: VitalGlitchDataType;
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      IO_zd := VitalBUFIF0 (data => I0_ipd,
              enable => (NOT OE_ipd));
      O_zd := TO_X01(IO_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => IO,
       GlitchData => IO_GlitchData,
       OutSignalName => "IO",
       OutTemp => IO_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_IO), TRUE),
                 1 => (I0_ipd'last_event, VitalExtendToFillDelay(tpd_I0_IO), TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (IO_ipd'last_event, tpd_IO_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_BI_DIR_VITAL of BI_DIR is
   for VITAL
   end for;
end CFG_BI_DIR_VITAL;


----- CELL BUFEI -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BUFEI is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_OE_O                       :	VitalDelayType01z := (0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns);
      tpd_I0_O                       :	VitalDelayType01 := (0.010 ns, 0.010 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BUFEI : entity is TRUE;
end BUFEI;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of BUFEI is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, OE_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalBUFIF0 (data => I0_ipd,
              enable => OE_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_O), TRUE),
                 1 => (I0_ipd'last_event, VitalExtendToFillDelay(tpd_I0_O), TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;

end VITAL;

configuration CFG_BUFEI_VITAL of BUFEI is
   for VITAL
   end for;
end CFG_BUFEI_VITAL;

----- CELL CCU_BUF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_BUF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_CI_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CI                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CI                             :	in    STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_BUF : entity is TRUE;
end CCU_BUF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_BUF is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CI_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CI_ipd, CI, tipd_CI);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CI_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(CI_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => O_GlitchData,
       OutSignalName => "COUT",
       OutTemp => O_zd,
       Paths => (0 => (CI_ipd'last_event, tpd_CI_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_BUF_VITAL of CCU_BUF is
   for VITAL
   end for;
end CFG_CCU_BUF_VITAL;

----- CELL CCU_OUT -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_OUT is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_CI_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CI                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CI                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_OUT : entity is TRUE;
end CCU_OUT;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_OUT is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CI_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CI_ipd, CI, tipd_CI);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CI_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(CI_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (CI_ipd'last_event, tpd_CI_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_OUT_VITAL of CCU_OUT is
   for VITAL
   end for;
end CFG_CCU_OUT_VITAL;


----- CELL FT_BUF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity FT_BUF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of FT_BUF : entity is TRUE;
end FT_BUF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of FT_BUF is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_FT_BUF_VITAL of FT_BUF is
   for VITAL
   end for;
end CFG_FT_BUF_VITAL;

----- CELL BUFF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BUFF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BUFF : entity is TRUE;
end BUFF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of BUFF is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_BUFF_VITAL of BUFF is
   for VITAL
   end for;
end CFG_BUFF_VITAL;


----- CELL BUFTH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BUFTH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_OE_O                       :	VitalDelayType01z := (0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns);
      tpd_I0_O                       :	VitalDelayType01 := (0.010 ns, 0.010 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BUFTH : entity is TRUE;
end BUFTH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of BUFTH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, OE_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalBUFIF0 (data => I0_ipd,
              enable => (NOT OE_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_O), TRUE),
                 1 => (I0_ipd'last_event, VitalExtendToFillDelay(tpd_I0_O), TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;

end VITAL;

configuration CFG_BUFTH_VITAL of BUFTH is
   for VITAL
   end for;
end CFG_BUFTH_VITAL;


----- CELL BUFTI -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BUFTI is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_OE_O                       :	VitalDelayType01z := (0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns);
      tpd_I0_O                       :	VitalDelayType01 := (0.010 ns, 0.010 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BUFTI : entity is TRUE;
end BUFTI;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of BUFTI is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, OE_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalBUFIF0 (data => I0_ipd,
              enable => (NOT OE_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_O), TRUE),
                 1 => (I0_ipd'last_event, VitalExtendToFillDelay(tpd_I0_O), TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;

end VITAL;

configuration CFG_BUFTI_VITAL of BUFTI is
   for VITAL
   end for;
end CFG_BUFTI_VITAL;


----- CELL BUFTL -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BUFTL is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_OE_O                       :	VitalDelayType01z := (0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns);
      tpd_I0_O                       :	VitalDelayType01 := (0.010 ns, 0.010 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BUFTL : entity is TRUE;
end BUFTL;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of BUFTL is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, OE_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalBUFIF0 (data => I0_ipd,
              enable => OE_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_O), TRUE),
                 1 => (I0_ipd'last_event, VitalExtendToFillDelay(tpd_I0_O), TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;

end VITAL;

configuration CFG_BUFTL_VITAL of BUFTL is
   for VITAL
   end for;
end CFG_BUFTL_VITAL;


----- CELL CCU_ABS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_ABS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_PN_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_PN_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_PN                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      PN                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_ABS : entity is TRUE;
end CCU_ABS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_ABS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL PN_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (PN_ipd, PN, tipd_PN);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, PN_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd :=
       (((CIN_ipd) XOR ((NOT D_ipd))) AND (PN_ipd)) OR ((D_ipd) AND ((NOT
         PN_ipd)));
      COUT_zd := (CIN_ipd) AND ((NOT D_ipd)) AND (PN_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 1 => (PN_ipd'last_event, tpd_PN_S0, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 1 => (PN_ipd'last_event, tpd_PN_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_ABS_VITAL of CCU_ABS is
   for VITAL
   end for;
end CFG_CCU_ABS_VITAL;


----- CELL CCU_ADD -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_ADD is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_A0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_ADD : entity is TRUE;
end CCU_ADD;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_ADD is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, B0_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := (B0_ipd) XOR (A0_ipd) XOR (CIN_ipd);
      COUT_zd :=
       ((CIN_ipd) AND (A0_ipd)) OR ((B0_ipd) AND (A0_ipd)) OR ((CIN_ipd) AND
         (B0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_S0, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_S0, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_ADD_VITAL of CCU_ADD is
   for VITAL
   end for;
end CFG_CCU_ADD_VITAL;

----- CELL CCU_GEN -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_GEN is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_A0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_GEN : entity is TRUE;
end CCU_GEN;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_GEN is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, B0_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := (B0_ipd) XOR (A0_ipd) XOR (CIN_ipd);
      COUT_zd :=
       ((CIN_ipd) AND (A0_ipd)) OR ((B0_ipd) AND (A0_ipd)) OR ((CIN_ipd) AND
         (B0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_S0, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_S0, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_GEN_VITAL of CCU_GEN is
   for VITAL
   end for;
end CFG_CCU_GEN_VITAL;


----- CELL CCU_GEN1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_GEN1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_A0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_GEN1 : entity is TRUE;
end CCU_GEN1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_GEN1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, B0_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := (B0_ipd) XOR (A0_ipd) XOR (CIN_ipd);
      COUT_zd :=
       ((CIN_ipd) AND (A0_ipd)) OR ((B0_ipd) AND (A0_ipd)) OR ((CIN_ipd) AND
         (B0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_S0, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_S0, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_GEN1_VITAL of CCU_GEN1 is
   for VITAL
   end for;
end CFG_CCU_GEN1_VITAL;

----- CELL CCU_GEN2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_GEN2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_A0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      D                              :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_GEN2 : entity is TRUE;
end CCU_GEN2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_GEN2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, B0_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := (B0_ipd) XOR (A0_ipd) XOR (CIN_ipd);
      COUT_zd :=
       ((CIN_ipd) AND (A0_ipd)) OR ((B0_ipd) AND (A0_ipd)) OR ((CIN_ipd) AND
         (B0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_S0, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_S0, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_GEN2_VITAL of CCU_GEN2 is
   for VITAL
   end for;
end CFG_CCU_GEN2_VITAL;

----- CELL CCU_SUB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_SUB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_A0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_SUB : entity is TRUE;
end CCU_SUB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_SUB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, B0_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := (NOT(B0_ipd)) XOR (A0_ipd) XOR (CIN_ipd);
      COUT_zd :=
       ((CIN_ipd) AND (A0_ipd)) OR ((NOT(B0_ipd)) AND (A0_ipd)) OR ((CIN_ipd) AND
         (NOT(B0_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_S0, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_S0, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_SUB_VITAL of CCU_SUB is
   for VITAL
   end for;
end CFG_CCU_SUB_VITAL;


----- CELL CCU_ADD_2S -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_ADD_2S is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_A0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_SEL_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_SEL_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SEL                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      SEL                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_ADD_2S : entity is TRUE;
end CCU_ADD_2S;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_ADD_2S is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SEL_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (SEL_ipd, SEL, tipd_SEL);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, B0_ipd, SEL_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE P_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := ((NOT A0_ipd) AND SEL_ipd) XOR B0_ipd XOR CIN_ipd;
      COUT_zd :=((NOT A0_ipd) AND SEL_ipd AND B0_ipd) OR ((NOT A0_ipd) AND SEL_ipd AND CIN_ipd) OR (CIN_ipd AND B0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => P_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_S0, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_S0, TRUE),
		 2 => (SEL_ipd'last_event, tpd_SEL_S0, TRUE),
                 3 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_COUT, TRUE),
		 2 => (SEL_ipd'last_event, tpd_SEL_COUT, TRUE),
                 3 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_ADD_2S_VITAL of CCU_ADD_2S is
   for VITAL
   end for;
end CFG_CCU_ADD_2S_VITAL;

----- CELL CCU_MULT -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_MULT is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_A0_P                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A1_P                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_P                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B1_P                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_P                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A1_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B1_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      A1                             :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      B1                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      P                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_MULT : entity is TRUE;
end CCU_MULT;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_MULT is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (A1_ipd, A1, tipd_A1);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (B1_ipd, B1, tipd_B1);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, B0_ipd, A1_ipd, B1_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS P_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE P_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      P_zd := ((B0_ipd) AND (A0_ipd)) XOR ((B1_ipd) AND (A1_ipd)) XOR (CIN_ipd);
      COUT_zd :=
       (A0_ipd AND B0_ipd AND A1_ipd AND B1_ipd) OR (A0_ipd AND B0_ipd AND CIN_ipd) OR (A1_ipd AND B1_ipd AND CIN_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => P,
       GlitchData => P_GlitchData,
       OutSignalName => "P",
       OutTemp => P_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_P, TRUE),
		 1 => (A1_ipd'last_event, tpd_A1_P, TRUE),
                 2 => (B0_ipd'last_event, tpd_B0_P, TRUE),
		 3 => (B1_ipd'last_event, tpd_B1_P, TRUE),
                 4 => (CIN_ipd'last_event, tpd_CIN_P, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
		 1 => (A1_ipd'last_event, tpd_A1_COUT, TRUE),
                 2 => (B0_ipd'last_event, tpd_B0_COUT, TRUE),
		 3 => (B1_ipd'last_event, tpd_B1_COUT, TRUE),
                 4 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_MULT_VITAL of CCU_MULT is
   for VITAL
   end for;
end CFG_CCU_MULT_VITAL;

----- CELL CCU_AGB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_AGB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_AGB : entity is TRUE;
end CCU_AGB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_AGB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, B0_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS COUT_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      COUT_zd :=
       ((CIN_ipd) AND ((NOT ((B0_ipd) XOR (A0_ipd))))) OR (((NOT B0_ipd))
         AND (A0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE),
                 2 => (B0_ipd'last_event, tpd_B0_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_AGB_VITAL of CCU_AGB is
   for VITAL
   end for;
end CFG_CCU_AGB_VITAL;


----- CELL CCU_AGBS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_AGBS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC;
      S0                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_AGBS : entity is TRUE;
end CCU_AGBS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_AGBS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, B0_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS COUT_zd : STD_LOGIC is Results(1);
   ALIAS S0_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;
   VARIABLE S0_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      COUT_zd :=
       ((CIN_ipd) AND ((NOT ((B0_ipd) XOR (A0_ipd))))) OR (((NOT B0_ipd))
         AND (A0_ipd));
      S0_zd := ((NOT B0_ipd)) XOR (A0_ipd) XOR (CIN_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE),
                 2 => (B0_ipd'last_event, tpd_B0_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_S0, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE),
                 2 => (B0_ipd'last_event, tpd_B0_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_AGBS_VITAL of CCU_AGBS is
   for VITAL
   end for;
end CFG_CCU_AGBS_VITAL;


----- CELL CCU_AS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_AS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_A0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_AS_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_AS_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AS                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      AS                             :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_AS : entity is TRUE;
end CCU_AS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_AS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';
   SIGNAL AS_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   VitalWireDelay (AS_ipd, AS, tipd_AS);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, B0_ipd, CIN_ipd, AS_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd :=
       ((((NOT AS_ipd)) AND ((NOT B0_ipd))) OR ((AS_ipd) AND (B0_ipd))) XOR
         (A0_ipd) XOR (CIN_ipd);
      COUT_zd :=
       (((((NOT AS_ipd)) AND ((NOT B0_ipd))) OR ((AS_ipd) AND (B0_ipd))) AND
         ((CIN_ipd) OR (A0_ipd))) OR ((CIN_ipd) AND (A0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_S0, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_S0, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE),
                 3 => (AS_ipd'last_event, tpd_AS_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE),
                 3 => (AS_ipd'last_event, tpd_AS_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_AS_VITAL of CCU_AS is
   for VITAL
   end for;
end CFG_CCU_AS_VITAL;


----- CELL CCU_BTH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_BTH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_A0_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A1_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D0_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_P                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_AS_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_SH_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_NOP_P                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A1_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_AS_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_SH_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_NOP_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AS                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SH                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_NOP                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      A1                             :	in    STD_ULOGIC;
      D0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      AS                             :	in    STD_ULOGIC;
      SH                             :	in    STD_ULOGIC;
      NOP                            :	in    STD_ULOGIC;
      P                              :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_BTH : entity is TRUE;
end CCU_BTH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_BTH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';
   SIGNAL AS_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SH_ipd	 : STD_ULOGIC := 'X';
   SIGNAL NOP_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (A1_ipd, A1, tipd_A1);
   VitalWireDelay (D0_ipd, D0, tipd_D0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   VitalWireDelay (AS_ipd, AS, tipd_AS);
   VitalWireDelay (SH_ipd, SH, tipd_SH);
   VitalWireDelay (NOP_ipd, NOP, tipd_NOP);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, A1_ipd, D0_ipd, CIN_ipd, AS_ipd, SH_ipd, NOP_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS P_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE P_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      P_zd :=
       ((NOP_ipd) AND (D0_ipd)) OR (((NOT NOP_ipd)) AND ((AS_ipd) XOR
         (((SH_ipd) AND (A1_ipd)) OR (((NOT SH_ipd)) AND (A0_ipd))) XOR
         (D0_ipd) XOR (CIN_ipd)));
      COUT_zd :=
       ((CIN_ipd) AND (D0_ipd)) OR (((CIN_ipd) OR (D0_ipd)) AND ((AS_ipd)
         XOR (((SH_ipd) AND (A1_ipd)) OR (((NOT SH_ipd)) AND (A0_ipd)))));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => P,
       GlitchData => P_GlitchData,
       OutSignalName => "P",
       OutTemp => P_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_P, TRUE),
                 1 => (A1_ipd'last_event, tpd_A1_P, TRUE),
                 2 => (D0_ipd'last_event, tpd_D0_P, TRUE),
                 3 => (CIN_ipd'last_event, tpd_CIN_P, TRUE),
                 4 => (AS_ipd'last_event, tpd_AS_P, TRUE),
                 5 => (SH_ipd'last_event, tpd_SH_P, TRUE),
                 6 => (NOP_ipd'last_event, tpd_NOP_P, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (A1_ipd'last_event, tpd_A1_COUT, TRUE),
                 2 => (D0_ipd'last_event, tpd_D0_COUT, TRUE),
                 3 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE),
                 4 => (AS_ipd'last_event, tpd_AS_COUT, TRUE),
                 5 => (SH_ipd'last_event, tpd_SH_COUT, TRUE),
                 6 => (NOP_ipd'last_event, tpd_NOP_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_BTH_VITAL of CCU_BTH is
   for VITAL
   end for;
end CFG_CCU_BTH_VITAL;


----- CELL CCU_BTH_LSTC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_BTH_LSTC is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_A0_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A1_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_P                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_ADD_P                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A1_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_ADD_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      A1                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      ADD                            :	in    STD_ULOGIC;
      P                              :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_BTH_LSTC : entity is TRUE;
end CCU_BTH_LSTC;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_BTH_LSTC is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';
   SIGNAL ADD_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (A1_ipd, A1, tipd_A1);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   VitalWireDelay (ADD_ipd, ADD, tipd_ADD);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, A1_ipd, CIN_ipd, ADD_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS P_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE P_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      P_zd := (A0_ipd) XOR ((ADD_ipd) AND (A1_ipd)) XOR (CIN_ipd);
      COUT_zd :=
       ((ADD_ipd) AND (A1_ipd) AND (CIN_ipd)) OR ((CIN_ipd) AND (A0_ipd)) OR
         ((ADD_ipd) AND (A1_ipd) AND (A0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => P,
       GlitchData => P_GlitchData,
       OutSignalName => "P",
       OutTemp => P_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_P, TRUE),
                 1 => (A1_ipd'last_event, tpd_A1_P, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_P, TRUE),
                 3 => (ADD_ipd'last_event, tpd_ADD_P, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (A1_ipd'last_event, tpd_A1_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE),
                 3 => (ADD_ipd'last_event, tpd_ADD_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_BTH_LSTC_VITAL of CCU_BTH_LSTC is
   for VITAL
   end for;
end CFG_CCU_BTH_LSTC_VITAL;


----- CELL CCU_BTH_TC_LSB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_BTH_TC_LSB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_A0_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A1_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_P                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_AS_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_SH_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_NOP_P                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A1_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_AS_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_SH_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_NOP_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AS                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SH                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_NOP                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      A1                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      AS                             :	in    STD_ULOGIC;
      SH                             :	in    STD_ULOGIC;
      NOP                            :	in    STD_ULOGIC;
      P                              :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_BTH_TC_LSB : entity is TRUE;
end CCU_BTH_TC_LSB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_BTH_TC_LSB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';
   SIGNAL AS_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SH_ipd	 : STD_ULOGIC := 'X';
   SIGNAL NOP_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (A1_ipd, A1, tipd_A1);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   VitalWireDelay (AS_ipd, AS, tipd_AS);
   VitalWireDelay (SH_ipd, SH, tipd_SH);
   VitalWireDelay (NOP_ipd, NOP, tipd_NOP);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, A1_ipd, CIN_ipd, AS_ipd, SH_ipd, NOP_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS P_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE P_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      P_zd :=
       ((NOT NOP_ipd)) AND ((AS_ipd) XOR (((SH_ipd) AND (A1_ipd)) OR (((NOT
         SH_ipd)) AND (A0_ipd))) XOR (CIN_ipd));
      COUT_zd :=
       (CIN_ipd) AND ((AS_ipd) XOR (((SH_ipd) AND (A1_ipd)) OR (((NOT
         SH_ipd)) AND (A0_ipd))));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => P,
       GlitchData => P_GlitchData,
       OutSignalName => "P",
       OutTemp => P_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_P, TRUE),
                 1 => (A1_ipd'last_event, tpd_A1_P, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_P, TRUE),
                 3 => (AS_ipd'last_event, tpd_AS_P, TRUE),
                 4 => (SH_ipd'last_event, tpd_SH_P, TRUE),
                 5 => (NOP_ipd'last_event, tpd_NOP_P, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (A1_ipd'last_event, tpd_A1_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE),
                 3 => (AS_ipd'last_event, tpd_AS_COUT, TRUE),
                 4 => (SH_ipd'last_event, tpd_SH_COUT, TRUE),
                 5 => (NOP_ipd'last_event, tpd_NOP_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_BTH_TC_LSB_VITAL of CCU_BTH_TC_LSB is
   for VITAL
   end for;
end CFG_CCU_BTH_TC_LSB_VITAL;


----- CELL CCU_BTH_TC_MSB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_BTH_TC_MSB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_A0_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D0_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_P                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_AS_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_NOP_P                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_AS_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_NOP_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AS                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_NOP                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      D0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      AS                             :	in    STD_ULOGIC;
      NOP                            :	in    STD_ULOGIC;
      P                              :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_BTH_TC_MSB : entity is TRUE;
end CCU_BTH_TC_MSB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_BTH_TC_MSB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL D0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';
   SIGNAL AS_ipd	 : STD_ULOGIC := 'X';
   SIGNAL NOP_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (D0_ipd, D0, tipd_D0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   VitalWireDelay (AS_ipd, AS, tipd_AS);
   VitalWireDelay (NOP_ipd, NOP, tipd_NOP);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, D0_ipd, CIN_ipd, AS_ipd, NOP_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS P_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE P_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      P_zd :=
       ((NOP_ipd) AND (D0_ipd)) OR (((NOT NOP_ipd)) AND ((AS_ipd) XOR
         (A0_ipd) XOR (D0_ipd) XOR (CIN_ipd)));
      COUT_zd :=
       ((CIN_ipd) AND ((A0_ipd) XOR (AS_ipd))) OR ((D0_ipd) AND ((A0_ipd)
         XOR (AS_ipd))) OR ((CIN_ipd) AND (D0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => P,
       GlitchData => P_GlitchData,
       OutSignalName => "P",
       OutTemp => P_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_P, TRUE),
                 1 => (D0_ipd'last_event, tpd_D0_P, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_P, TRUE),
                 3 => (AS_ipd'last_event, tpd_AS_P, TRUE),
                 4 => (NOP_ipd'last_event, tpd_NOP_P, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (D0_ipd'last_event, tpd_D0_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE),
                 3 => (AS_ipd'last_event, tpd_AS_COUT, TRUE),
                 4 => (NOP_ipd'last_event, tpd_NOP_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_BTH_TC_MSB_VITAL of CCU_BTH_TC_MSB is
   for VITAL
   end for;
end CFG_CCU_BTH_TC_MSB_VITAL;


----- CELL CCU_BTH_UNS_LSB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_BTH_UNS_LSB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_A0_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A1_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B1_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_P                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_A1_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B1_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      A0                             :	in    STD_ULOGIC;
      A1                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      B0                             :	in    STD_ULOGIC;
      B1                             :	in    STD_ULOGIC;
      P                              :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_BTH_UNS_LSB : entity is TRUE;
end CCU_BTH_UNS_LSB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_BTH_UNS_LSB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B1_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A0_ipd, A0, tipd_A0);
   VitalWireDelay (A1_ipd, A1, tipd_A1);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (B1_ipd, B1, tipd_B1);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A0_ipd, A1_ipd, CIN_ipd, B0_ipd, B1_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS P_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE P_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      P_zd :=
       ((B1_ipd) AND (A1_ipd)) XOR ((B0_ipd) AND (A0_ipd)) XOR (CIN_ipd);
      COUT_zd :=
       ((B1_ipd) AND (A1_ipd) AND (CIN_ipd)) OR ((B0_ipd) AND (A0_ipd) AND
         (CIN_ipd)) OR ((B1_ipd) AND (A1_ipd) AND (B0_ipd) AND (A0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => P,
       GlitchData => P_GlitchData,
       OutSignalName => "P",
       OutTemp => P_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_P, TRUE),
                 1 => (A1_ipd'last_event, tpd_A1_P, TRUE),
                 2 => (B0_ipd'last_event, tpd_B0_P, TRUE),
                 3 => (B1_ipd'last_event, tpd_B1_P, TRUE),
                 4 => (CIN_ipd'last_event, tpd_CIN_P, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (A0_ipd'last_event, tpd_A0_COUT, TRUE),
                 1 => (A1_ipd'last_event, tpd_A1_COUT, TRUE),
                 2 => (B0_ipd'last_event, tpd_B0_COUT, TRUE),
                 3 => (B1_ipd'last_event, tpd_B1_COUT, TRUE),
                 4 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_BTH_UNS_LSB_VITAL of CCU_BTH_UNS_LSB is
   for VITAL
   end for;
end CFG_CCU_BTH_UNS_LSB_VITAL;


----- CELL CCU_BTH_UNS_MSB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_BTH_UNS_MSB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_D0_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_P                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_AS_P                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_NOP_P                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_AS_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_NOP_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AS                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_NOP                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D0                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      AS                             :	in    STD_ULOGIC;
      NOP                            :	in    STD_ULOGIC;
      P                              :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_BTH_UNS_MSB : entity is TRUE;
end CCU_BTH_UNS_MSB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_BTH_UNS_MSB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';
   SIGNAL AS_ipd	 : STD_ULOGIC := 'X';
   SIGNAL NOP_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D0_ipd, D0, tipd_D0);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   VitalWireDelay (AS_ipd, AS, tipd_AS);
   VitalWireDelay (NOP_ipd, NOP, tipd_NOP);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D0_ipd, CIN_ipd, AS_ipd, NOP_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS P_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE P_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      P_zd :=
       (((D0_ipd) XOR (AS_ipd) XOR (CIN_ipd)) AND ((NOT NOP_ipd))) OR
         ((NOP_ipd) AND (D0_ipd));
      COUT_zd :=
       ((CIN_ipd) AND (AS_ipd)) OR ((CIN_ipd) AND (D0_ipd)) OR ((D0_ipd) AND
         (AS_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => P,
       GlitchData => P_GlitchData,
       OutSignalName => "P",
       OutTemp => P_zd,
       Paths => (0 => (D0_ipd'last_event, tpd_D0_P, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_P, TRUE),
                 2 => (AS_ipd'last_event, tpd_AS_P, TRUE),
                 3 => (NOP_ipd'last_event, tpd_NOP_P, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (D0_ipd'last_event, tpd_D0_COUT, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE),
                 2 => (AS_ipd'last_event, tpd_AS_COUT, TRUE),
                 3 => (NOP_ipd'last_event, tpd_NOP_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_BTH_UNS_MSB_VITAL of CCU_BTH_UNS_MSB is
   for VITAL
   end for;
end CFG_CCU_BTH_UNS_MSB_VITAL;


----- CELL CCU_DC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_DC is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_DC : entity is TRUE;
end CCU_DC;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_DC is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := (NOT((CIN_ipd) XOR (D_ipd)));
      COUT_zd := (CIN_ipd) OR (D_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_DC_VITAL of CCU_DC is
   for VITAL
   end for;
end CFG_CCU_DC_VITAL;

----- CELL CCU_UC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_UC is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_UC : entity is TRUE;
end CCU_UC;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_UC is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := ((CIN_ipd) XOR (D_ipd));
      COUT_zd := (CIN_ipd) AND (D_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_UC_VITAL of CCU_UC is
   for VITAL
   end for;
end CFG_CCU_UC_VITAL;


----- CELL CCU_DCP -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_DCP is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_SD_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LOAD_S0                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_SD_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LOAD_COUT                  :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LOAD                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SD                             :	in    STD_ULOGIC;
      LOAD                           :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_DCP : entity is TRUE;
end CCU_DCP;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_DCP is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LOAD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SD_ipd, SD, tipd_SD);
   VitalWireDelay (LOAD_ipd, LOAD, tipd_LOAD);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, SD_ipd, LOAD_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd :=
       (NOT((CIN_ipd) XOR  (((NOT LOAD_ipd) AND (D_ipd)) OR ((LOAD_ipd)
         AND (SD_ipd)))));
      COUT_zd :=((CIN_ipd) OR (((NOT LOAD_ipd) AND (D_ipd)) OR ((LOAD_ipd)
         AND (SD_ipd))));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (SD_ipd'last_event, tpd_SD_S0, TRUE),
                 1 => (LOAD_ipd'last_event, tpd_LOAD_S0, TRUE),
                 2 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 3 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (LOAD_ipd'last_event, tpd_LOAD_COUT, TRUE),
                 1 => (SD_ipd'last_event, tpd_SD_COUT, TRUE),
                 2 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 3 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_DCP_VITAL of CCU_DCP is
   for VITAL
   end for;
end CFG_CCU_DCP_VITAL;

----- CELL CCU_RCD_AS -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_RCD_AS is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_B2_COUT                    :	VitalDelayType01 := (0.010 ns, 0.010 ns);
      tpd_B2_AS                      :	VitalDelayType01 := (0.010 ns, 0.010 ns);
      tipd_B2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      B2                             :	in    STD_ULOGIC;
      AS                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of CCU_RCD_AS : entity is TRUE;
end CCU_RCD_AS;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_RCD_AS is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL B2_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (B2_ipd, B2, tipd_B2);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior_AS : process (B2_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(B2_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------

      VitalPathDelay01 (
       OutSignal => AS,
       GlitchData => O_GlitchData,
       OutSignalName => "AS",
       OutTemp => O_zd,
       Paths => (0 => (B2_ipd'last_event, tpd_B2_AS, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

   VITALBehavior_COUT : process (B2_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(B2_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------

      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => O_GlitchData,
       OutSignalName => "COUT",
       OutTemp => O_zd,
       Paths => (0 => (B2_ipd'last_event, tpd_B2_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_RCD_AS_VITAL of CCU_RCD_AS is
   for VITAL
   end for;
end CFG_CCU_RCD_AS_VITAL;

----- CELL CCU_RCD -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_RCD is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_B0_AS                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B1_AS                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B2_AS                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_SH                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B1_SH                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B2_SH                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B0_NOP                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B1_NOP                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B2_NOP                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      B0                             :	in    STD_ULOGIC;
      B1                             :	in    STD_ULOGIC;
      B2                             :	in    STD_ULOGIC;
      AS                             :	out   STD_ULOGIC;
      SH                             :	out   STD_ULOGIC;
      NOP                            :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_RCD : entity is TRUE;
end CCU_RCD;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_RCD is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL B0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B2_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (B0_ipd, B0, tipd_B0);
   VitalWireDelay (B1_ipd, B1, tipd_B1);
   VitalWireDelay (B2_ipd, B2, tipd_B2);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (B0_ipd, B1_ipd, B2_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 3) := (others => 'X');
   ALIAS AS_zd : STD_LOGIC is Results(1);
   ALIAS SH_zd : STD_LOGIC is Results(2);
   ALIAS NOP_zd : STD_LOGIC is Results(3);

   -- output glitch detection variables
   VARIABLE AS_GlitchData	: VitalGlitchDataType;
   VARIABLE SH_GlitchData	: VitalGlitchDataType;
   VARIABLE NOP_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      AS_zd := TO_X01(B2_ipd);
      SH_zd :=
       ((B1_ipd) AND ((NOT B2_ipd)) AND (B0_ipd)) OR (((NOT B1_ipd)) AND
         (B2_ipd) AND ((NOT B0_ipd)));
      NOP_zd :=
       ((B1_ipd) AND (B2_ipd) AND (B0_ipd)) OR (((NOT B1_ipd)) AND ((NOT
         B2_ipd)) AND ((NOT B0_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => AS,
       GlitchData => AS_GlitchData,
       OutSignalName => "AS",
       OutTemp => AS_zd,
       Paths => (0 => (B0_ipd'last_event, tpd_B0_AS, TRUE),
                 1 => (B1_ipd'last_event, tpd_B1_AS, TRUE),
                 2 => (B2_ipd'last_event, tpd_B2_AS, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => SH,
       GlitchData => SH_GlitchData,
       OutSignalName => "SH",
       OutTemp => SH_zd,
       Paths => (0 => (B2_ipd'last_event, tpd_B2_SH, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_SH, TRUE),
                 2 => (B1_ipd'last_event, tpd_B1_SH, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => NOP,
       GlitchData => NOP_GlitchData,
       OutSignalName => "NOP",
       OutTemp => NOP_zd,
       Paths => (0 => (B2_ipd'last_event, tpd_B2_NOP, TRUE),
                 1 => (B0_ipd'last_event, tpd_B0_NOP, TRUE),
                 2 => (B1_ipd'last_event, tpd_B1_NOP, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_RCD_VITAL of CCU_RCD is
   for VITAL
   end for;
end CFG_CCU_RCD_VITAL;


----- CELL CCU_RCD_LSB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_RCD_LSB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_B2_AS                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B1_AS                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B2_SH                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B1_SH                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B2_NOP                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_B1_NOP                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      B1                             :	in    STD_ULOGIC;
      B2                             :	in    STD_ULOGIC;
      AS                             :	out   STD_ULOGIC;
      SH                             :	out   STD_ULOGIC;
      NOP                            :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_RCD_LSB : entity is TRUE;
end CCU_RCD_LSB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_RCD_LSB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL B1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B2_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (B1_ipd, B1, tipd_B1);
   VitalWireDelay (B2_ipd, B2, tipd_B2);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (B1_ipd, B2_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 3) := (others => 'X');
   ALIAS AS_zd : STD_LOGIC is Results(1);
   ALIAS SH_zd : STD_LOGIC is Results(2);
   ALIAS NOP_zd : STD_LOGIC is Results(3);

   -- output glitch detection variables
   VARIABLE AS_GlitchData	: VitalGlitchDataType;
   VARIABLE SH_GlitchData	: VitalGlitchDataType;
   VARIABLE NOP_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      AS_zd := TO_X01(B2_ipd);
      SH_zd := ((NOT B1_ipd)) AND (B2_ipd);
      NOP_zd := ((NOT B1_ipd)) AND ((NOT B2_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => AS,
       GlitchData => AS_GlitchData,
       OutSignalName => "AS",
       OutTemp => AS_zd,
       Paths => (0 => (B2_ipd'last_event, tpd_B2_AS, TRUE),
                 1 => (B1_ipd'last_event, tpd_B1_AS, TRUE)),

       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => SH,
       GlitchData => SH_GlitchData,
       OutSignalName => "SH",
       OutTemp => SH_zd,
       Paths => (0 => (B2_ipd'last_event, tpd_B2_SH, TRUE),
                 1 => (B1_ipd'last_event, tpd_B1_SH, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => NOP,
       GlitchData => NOP_GlitchData,
       OutSignalName => "NOP",
       OutTemp => NOP_zd,
       Paths => (0 => (B2_ipd'last_event, tpd_B2_NOP, TRUE),
                 1 => (B1_ipd'last_event, tpd_B1_NOP, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_RCD_LSB_VITAL of CCU_RCD_LSB is
   for VITAL
   end for;
end CFG_CCU_RCD_LSB_VITAL;


----- CELL CCU_UCP -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_UCP is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_SD_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_SD_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LOAD_S0                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LOAD_COUT                  :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LOAD                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SD                             :	in    STD_ULOGIC;
      LOAD                           :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_UCP : entity is TRUE;
end CCU_UCP;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_UCP is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LOAD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SD_ipd, SD, tipd_SD);
   VitalWireDelay (LOAD_ipd, LOAD, tipd_LOAD);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, SD_ipd, LOAD_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd :=
       (CIN_ipd) XOR ((((NOT LOAD_ipd)) AND (D_ipd)) OR ((LOAD_ipd) AND
         (SD_ipd)));
      COUT_zd := ((((NOT LOAD_ipd)) AND (D_ipd)) OR ((LOAD_ipd) AND
         (SD_ipd))) AND (CIN_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (SD_ipd'last_event, tpd_SD_S0, TRUE),
                 1 => (LOAD_ipd'last_event, tpd_LOAD_S0, TRUE),
                 2 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 3 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (LOAD_ipd'last_event, tpd_LOAD_COUT, TRUE),
                 1 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE),
       		 3 => (SD_ipd'last_event, tpd_SD_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_UCP_VITAL of CCU_UCP is
   for VITAL
   end for;
end CFG_CCU_UCP_VITAL;


----- CELL CCU_UDC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_UDC is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_UD_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_UD_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_UD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      UD                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_UDC : entity is TRUE;
end CCU_UDC;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_UDC is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL UD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (UD_ipd, UD, tipd_UD);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, UD_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := ((NOT UD_ipd)) XOR (D_ipd) XOR (CIN_ipd);
      COUT_zd :=
       ((CIN_ipd) AND (D_ipd)) OR (((NOT UD_ipd)) AND (D_ipd)) OR ((CIN_ipd)
         AND ((NOT UD_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 1 => (UD_ipd'last_event, tpd_UD_S0, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 1 => (UD_ipd'last_event, tpd_UD_COUT, TRUE),
                 2 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_UDC_VITAL of CCU_UDC is
   for VITAL
   end for;
end CFG_CCU_UDC_VITAL;


----- CELL CCU_UDCP -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CCU_UDCP is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := False;
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LOAD_S0                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LOAD_COUT                  :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_UD_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_UD_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_SD_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_SD_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                   :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LOAD                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_UD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SD                             :	in    STD_ULOGIC;
      LOAD                           :	in    STD_ULOGIC;
      UD                             :	in    STD_ULOGIC;
      CIN                            :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CCU_UDCP : entity is TRUE;
end CCU_UDCP;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CCU_UDCP is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LOAD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL UD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SD_ipd, SD, tipd_SD);
   VitalWireDelay (LOAD_ipd, LOAD, tipd_LOAD);
   VitalWireDelay (UD_ipd, UD, tipd_UD);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, SD_ipd, LOAD_ipd, UD_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd :=
       (((CIN_ipd) XOR (NOT (UD_ipd)) XOR (D_ipd)) AND (NOT (LOAD_ipd))) OR
         ((SD_ipd) AND (LOAD_ipd));
      COUT_zd :=
       (((CIN_ipd) AND (D_ipd)) OR (((NOT UD_ipd)) AND (D_ipd)) OR (((NOT
         UD_ipd)) AND (CIN_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 1 => (LOAD_ipd'last_event, tpd_LOAD_S0, TRUE),
                 2 => (UD_ipd'last_event, tpd_UD_S0, TRUE),
                 3 => (SD_ipd'last_event, tpd_SD_S0, TRUE),
                 4 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 1 => (LOAD_ipd'last_event, tpd_LOAD_COUT, TRUE),
                 2 => (UD_ipd'last_event, tpd_UD_COUT, TRUE),
                 3 => (SD_ipd'last_event, tpd_SD_COUT, TRUE),
                 4 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CCU_UDCP_VITAL of CCU_UDCP is
   for VITAL
   end for;
end CFG_CCU_UDCP_VITAL;


----- CELL GCLKBUF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity GCLKBUF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_CI_O                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CI                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CI                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of GCLKBUF : entity is TRUE;
end GCLKBUF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of GCLKBUF is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CI_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CI_ipd, CI, tipd_CI);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CI_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(CI_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (CI_ipd'last_event, tpd_CI_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_GCLKBUF_VITAL of GCLKBUF is
   for VITAL
   end for;
end CFG_GCLKBUF_VITAL;

----- CELL GCLKBUFI -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity GCLKBUFI is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of GCLKBUFI : entity is TRUE;
end GCLKBUFI;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of GCLKBUFI is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_GCLKBUFI_VITAL of GCLKBUFI is
   for VITAL
   end for;
end CFG_GCLKBUFI_VITAL;

----- CELL GSRBUF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity GSRBUF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_SRI_O                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SRI                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      SRI                            :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of GSRBUF : entity is TRUE;
end GSRBUF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of GSRBUF is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL SRI_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (SRI_ipd, SRI, tipd_SRI);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (SRI_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(SRI_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (SRI_ipd'last_event, tpd_SRI_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_GSRBUF_VITAL of GSRBUF is
   for VITAL
   end for;
end CFG_GSRBUF_VITAL;

----- CELL GSRBUFINV -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity GSRBUFINV is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_SRI_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SRI                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      SRI                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of GSRBUFINV : entity is TRUE;
end GSRBUFINV;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of GSRBUFINV is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL SRI_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (SRI_ipd, SRI, tipd_SRI);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (SRI_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (NOT SRI_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (SRI_ipd'last_event, tpd_SRI_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_GSRBUFINV_VITAL of GSRBUFINV is
   for VITAL
   end for;
end CFG_GSRBUFINV_VITAL;

----- CELL GSRBUFI -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity GSRBUFI is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of GSRBUFI : entity is TRUE;
end GSRBUFI;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of GSRBUFI is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_GSRBUFI_VITAL of GSRBUFI is
   for VITAL
   end for;
end CFG_GSRBUFI_VITAL;

----- CELL GSRBUFIINV -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity GSRBUFIINV is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of GSRBUFIINV : entity is TRUE;
end GSRBUFIINV;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of GSRBUFIINV is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (NOT I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_GSRBUFIINV_VITAL of GSRBUFIINV is
   for VITAL
   end for;
end CFG_GSRBUFIINV_VITAL;

----- CELL SRBUF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity SRBUF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_CI_O                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CI                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CI                            :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of SRBUF : entity is TRUE;
end SRBUF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of SRBUF is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CI_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CI_ipd, CI, tipd_CI);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CI_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(CI_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (CI_ipd'last_event, tpd_CI_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_SRBUF_VITAL of SRBUF is
   for VITAL
   end for;
end CFG_SRBUF_VITAL;

----- CELL SRBUFINV -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity SRBUFINV is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_CI_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CI                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      CI                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of SRBUFINV : entity is TRUE;
end SRBUFINV;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of SRBUFINV is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL CI_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (CI_ipd, CI, tipd_CI);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (CI_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (NOT CI_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (CI_ipd'last_event, tpd_CI_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_SRBUFINV_VITAL of SRBUFINV is
   for VITAL
   end for;
end CFG_SRBUFINV_VITAL;


----- CELL SRBUFI -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity SRBUFI is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of SRBUFI : entity is TRUE;
end SRBUFI;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of SRBUFI is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_SRBUFI_VITAL of SRBUFI is
   for VITAL
   end for;
end CFG_SRBUFI_VITAL;

----- CELL SRBUFIINV -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity SRBUFIINV is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of SRBUFIINV : entity is TRUE;
end SRBUFIINV;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of SRBUFIINV is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (NOT I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_SRBUFIINV_VITAL of SRBUFIINV is
   for VITAL
   end for;
end CFG_SRBUFIINV_VITAL;


----- CELL CYAND2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CYAND2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CYAND2 : entity is TRUE;
end CYAND2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CYAND2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (I1_ipd) AND (I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CYAND2_VITAL of CYAND2 is
   for VITAL
   end for;
end CFG_CYAND2_VITAL;


----- CELL CYXOR2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity CYXOR2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CYXOR2 : entity is TRUE;
end CYXOR2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of CYXOR2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (I1_ipd) XOR (I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_CYXOR2_VITAL of CYXOR2 is
   for VITAL
   end for;
end CFG_CYXOR2_VITAL;


----- CELL DC_LSB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity DC_LSB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                  :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                    :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CIN                         :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of DC_LSB : entity is TRUE;
end DC_LSB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of DC_LSB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := (CIN_ipd) XOR (D_ipd);
      COUT_zd := (CIN_ipd) AND (D_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_DC_LSB_VITAL of DC_LSB is
   for VITAL
   end for;
end CFG_DC_LSB_VITAL;

----- CELL GND -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity GND is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True);

   port(
      X                              :	out   STD_ULOGIC := '0');
attribute VITAL_LEVEL0 of GND : entity is TRUE;
end GND;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of GND is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;


begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   --  empty
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   X <= '0';


end VITAL;

configuration CFG_GND_VITAL of GND is
   for VITAL
   end for;
end CFG_GND_VITAL;

----- CELL GSROR2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity GSROR2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of GSROR2 : entity is TRUE;
end GSROR2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of GSROR2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (I1_ipd) OR (I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_GSROR2_VITAL of GSROR2 is
   for VITAL
   end for;
end CFG_GSROR2_VITAL;


----- CELL IBUF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity IBUF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.010 ns, 0.010 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of IBUF : entity is TRUE;
end IBUF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of IBUF is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_IBUF_VITAL of IBUF is
   for VITAL
   end for;
end CFG_IBUF_VITAL;

----- CELL IBUFINV -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity IBUFINV is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of IBUFINV : entity is TRUE;
end IBUFINV;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of IBUFINV is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (NOT I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_IBUFINV_VITAL of IBUFINV is
   for VITAL
   end for;
end CFG_IBUFINV_VITAL;

----- VITAL model for cell LVDSIN -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LVDSIN is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_P_IN_O                      :	VitalDelayType01 := ( 0.00 ns, 0.00 ns);
      tpd_N_IN_O                      :	VitalDelayType01 := ( 0.00 ns, 0.00 ns);
      tipd_N_IN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_P_IN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      N_IN                            :	in    STD_ULOGIC;
      P_IN                            :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LVDSIN : entity is FALSE;
end LVDSIN;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
-- -- use MACH.VTABLES.all;
architecture VITAL of LVDSIN is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL P_IN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (P_IN_ipd, P_IN, tipd_P_IN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (P_IN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(P_IN_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (P_IN_ipd'last_event, tpd_P_IN_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_LVDSIN_VITAL of LVDSIN is 
        for VITAL
        end for; 
end CFG_LVDSIN_VITAL;

----- VITAL model for cell LVDSOUT -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;

-- entity declaration --
entity LVDSOUT is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I_P_OUT                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I_N_OUT                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I                             :	in    STD_ULOGIC;
      P_OUT                             :	out   STD_ULOGIC;
      N_OUT                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LVDSOUT : entity is FALSE;
end LVDSOUT;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
-- use MACH.VTABLES.all;
architecture VITAL of LVDSOUT is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL I_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I_ipd, I, tipd_I);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(I_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => P_OUT,
       GlitchData => O_GlitchData,
       OutSignalName => "P_OUT",
       OutTemp => O_zd,
       Paths => (0 => (I_ipd'last_event, tpd_I_P_OUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_LVDSOUT_VITAL of LVDSOUT is 
        for VITAL
        end for; 
end CFG_LVDSOUT_VITAL;

----- VITAL model for cell LVDSTRI -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LVDSTRI is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_OE_P_OUT                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_I_P_OUT                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I_N_OUT                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_OE                        :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      I                             :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      P_OUT                          :	out   STD_ULOGIC;
      N_OUT                          :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LVDSTRI : entity is FALSE;
end LVDSTRI;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
--use MACH.VTABLES.all;
architecture VITAL of LVDSTRI is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL I_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I_ipd, I, tipd_I);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I_ipd, OE_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalBUFIF0 (data => I_ipd,
              enable => (NOT OE_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => P_OUT,
       GlitchData => O_GlitchData,
       OutSignalName => "P_OUT",
       OutTemp => O_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_P_OUT), TRUE),
                 1 => (I_ipd'last_event, VitalExtendToFillDelay(tpd_I_P_OUT), TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;
end VITAL;

configuration CFG_LVDSTRI_VITAL of LVDSTRI is 
        for VITAL
        end for; 
end CFG_LVDSTRI_VITAL;

----- VITAL model for cell LVDSIO -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity LVDSIO is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_OE_P_IO                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_N_IO                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_I_P_IO                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I_N_IO                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_P_IO_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_N_IO_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_OE                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_P_IO                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_N_IO                        :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      I                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      P_IO                             :	inout STD_ULOGIC;
      N_IO                             :	inout STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LVDSIO : entity is FALSE;
end LVDSIO;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
--use MACH.VTABLES.all;
architecture VITAL of LVDSIO is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL I_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL P_IO_ipd	 : STD_ULOGIC := 'X';
   SIGNAL N_IO_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I_ipd, I, tipd_I);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   VitalWireDelay (P_IO_ipd, P_IO, tipd_P_IO);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I_ipd, OE_ipd, P_IO_ipd)


   -- functionality results
--   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
     VARIABLE IO_zd : std_ulogic ;
     VARIABLE O_zd : std_ulogic ;

   -- output glitch detection variables
   VARIABLE IO_GlitchData	: VitalGlitchDataType;
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      IO_zd := VitalBUFIF1 (I_ipd, OE_ipd);
      O_zd := VitalBUF(P_IO_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => P_IO,
       GlitchData => IO_GlitchData,
       OutSignalName => "P_IO",
       OutTemp => IO_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_P_IO), TRUE),
                 1 => (I_ipd'last_event, VitalExtendToFillDelay(tpd_I_P_IO), TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (P_IO_ipd'last_event, tpd_P_IO_O, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_LVDSIO_VITAL of LVDSIO is 
        for VITAL
        end for; 
end CFG_LVDSIO_VITAL;

----- VITAL model for cell LVPECLIN -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LVPECLIN is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_P_IN_O                      :	VitalDelayType01 := ( 0.00 ns, 0.00 ns);
      tpd_N_IN_O                      :	VitalDelayType01 := ( 0.00 ns, 0.00 ns);
      tipd_N_IN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_P_IN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      N_IN                            :	in    STD_ULOGIC;
      P_IN                            :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LVPECLIN : entity is FALSE;
end LVPECLIN;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
-- -- use MACH.VTABLES.all;
architecture VITAL of LVPECLIN is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL P_IN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (P_IN_ipd, P_IN, tipd_P_IN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (P_IN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(P_IN_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (P_IN_ipd'last_event, tpd_P_IN_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_LVPECLIN_VITAL of LVPECLIN is 
        for VITAL
        end for; 
end CFG_LVPECLIN_VITAL;

----- VITAL model for cell LVPECLOUT -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;

-- entity declaration --
entity LVPECLOUT is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I_P_OUT                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I_N_OUT                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I                             :	in    STD_ULOGIC;
      P_OUT                             :	out   STD_ULOGIC;
      N_OUT                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LVPECLOUT : entity is FALSE;
end LVPECLOUT;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
-- use MACH.VTABLES.all;
architecture VITAL of LVPECLOUT is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL I_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I_ipd, I, tipd_I);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(I_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => P_OUT,
       GlitchData => O_GlitchData,
       OutSignalName => "P_OUT",
       OutTemp => O_zd,
       Paths => (0 => (I_ipd'last_event, tpd_I_P_OUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_LVPECLOUT_VITAL of LVPECLOUT is 
        for VITAL
        end for; 
end CFG_LVPECLOUT_VITAL;

----- VITAL model for cell LVPECLTRI -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LVPECLTRI is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_OE_P_OUT                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_I_P_OUT                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I_N_OUT                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_OE                        :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      I                             :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      P_OUT                          :	out   STD_ULOGIC;
      N_OUT                          :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LVPECLTRI : entity is FALSE;
end LVPECLTRI;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
--use MACH.VTABLES.all;
architecture VITAL of LVPECLTRI is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL I_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I_ipd, I, tipd_I);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I_ipd, OE_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalBUFIF0 (data => I_ipd,
              enable => (NOT OE_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => P_OUT,
       GlitchData => O_GlitchData,
       OutSignalName => "P_OUT",
       OutTemp => O_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_P_OUT), TRUE),
                 1 => (I_ipd'last_event, VitalExtendToFillDelay(tpd_I_P_OUT), TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;
end VITAL;

configuration CFG_LVPECLTRI_VITAL of LVPECLTRI is 
        for VITAL
        end for; 
end CFG_LVPECLTRI_VITAL;

----- VITAL model for cell BLVDSIN -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BLVDSIN is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_P_IN_O                      :	VitalDelayType01 := ( 0.00 ns, 0.00 ns);
      tpd_N_IN_O                      :	VitalDelayType01 := ( 0.00 ns, 0.00 ns);
      tipd_N_IN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_P_IN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      N_IN                            :	in    STD_ULOGIC;
      P_IN                            :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BLVDSIN : entity is FALSE;
end BLVDSIN;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
-- -- use MACH.VTABLES.all;
architecture VITAL of BLVDSIN is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL P_IN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (P_IN_ipd, P_IN, tipd_P_IN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (P_IN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(P_IN_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (P_IN_ipd'last_event, tpd_P_IN_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_BLVDSIN_VITAL of BLVDSIN is 
        for VITAL
        end for; 
end CFG_BLVDSIN_VITAL;

----- VITAL model for cell BLVDSOUT -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1 ;
use LAVA1.VLOGTOVITAL_TABLES.all;

-- entity declaration --
entity BLVDSOUT is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_I_P_OUT                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I_N_OUT                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I                             :	in    STD_ULOGIC;
      P_OUT                             :	out   STD_ULOGIC;
      N_OUT                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BLVDSOUT : entity is FALSE;
end BLVDSOUT;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
-- use MACH.VTABLES.all;
architecture VITAL of BLVDSOUT is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL I_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I_ipd, I, tipd_I);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(I_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => P_OUT,
       GlitchData => O_GlitchData,
       OutSignalName => "P_OUT",
       OutTemp => O_zd,
       Paths => (0 => (I_ipd'last_event, tpd_I_P_OUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_BLVDSOUT_VITAL of BLVDSOUT is 
        for VITAL
        end for; 
end CFG_BLVDSOUT_VITAL;

----- VITAL model for cell BLVDSTRI -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity BLVDSTRI is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_OE_P_OUT                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_I_P_OUT                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I_N_OUT                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_OE                        :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      I                             :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      P_OUT                          :	out   STD_ULOGIC;
      N_OUT                          :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BLVDSTRI : entity is FALSE;
end BLVDSTRI;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
--use MACH.VTABLES.all;
architecture VITAL of BLVDSTRI is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL I_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I_ipd, I, tipd_I);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I_ipd, OE_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalBUFIF0 (data => I_ipd,
              enable => (NOT OE_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => P_OUT,
       GlitchData => O_GlitchData,
       OutSignalName => "P_OUT",
       OutTemp => O_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_P_OUT), TRUE),
                 1 => (I_ipd'last_event, VitalExtendToFillDelay(tpd_I_P_OUT), TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;
end VITAL;

configuration CFG_BLVDSTRI_VITAL of BLVDSTRI is 
        for VITAL
        end for; 
end CFG_BLVDSTRI_VITAL;

----- VITAL model for cell BLVDSIO -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

-- entity declaration --
entity BLVDSIO is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_OE_P_IO                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_N_IO                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_I_P_IO                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_I_N_IO                      :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_P_IO_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_N_IO_O                       :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_I                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_OE                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_P_IO                        :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tipd_N_IO                        :	VitalDelayType01 := (0.0 ns, 0.0 ns));

   port(
      I                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      P_IO                             :	inout STD_ULOGIC;
      N_IO                             :	inout STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of BLVDSIO : entity is FALSE;
end BLVDSIO;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library LAVA1;
--use MACH.VTABLES.all;
architecture VITAL of BLVDSIO is
   attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

   SIGNAL I_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';
   SIGNAL P_IO_ipd	 : STD_ULOGIC := 'X';
   SIGNAL N_IO_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I_ipd, I, tipd_I);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   VitalWireDelay (P_IO_ipd, P_IO, tipd_P_IO);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I_ipd, OE_ipd, P_IO_ipd)


   -- functionality results
--   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
     VARIABLE IO_zd : std_ulogic ;
     VARIABLE O_zd : std_ulogic ;

   -- output glitch detection variables
   VARIABLE IO_GlitchData	: VitalGlitchDataType;
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      IO_zd := VitalBUFIF1 (I_ipd, OE_ipd);
      O_zd := VitalBUF(P_IO_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => P_IO,
       GlitchData => IO_GlitchData,
       OutSignalName => "P_IO",
       OutTemp => IO_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_P_IO), TRUE),
                 1 => (I_ipd'last_event, VitalExtendToFillDelay(tpd_I_P_IO), TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (P_IO_ipd'last_event, tpd_P_IO_O, TRUE)),
       Mode => VitalInertial,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;
end VITAL;

configuration CFG_BLVDSIO_VITAL of BLVDSIO is 
        for VITAL
        end for; 
end CFG_BLVDSIO_VITAL;

----- CELL INV -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity INV is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of INV : entity is TRUE;
end INV;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of INV is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (NOT I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_INV_VITAL of INV is
   for VITAL
   end for;
end CFG_INV_VITAL;


----- CELL INVTH -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity INVTH is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_OE_O                       :	VitalDelayType01z := (0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns);
      tpd_I0_O                       :	VitalDelayType01 := (0.010 ns, 0.010 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of INVTH : entity is TRUE;
end INVTH;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of INVTH is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, OE_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalBUFIF0 (data => (NOT I0_ipd),
              enable => (NOT OE_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_O), TRUE),
                 1 => (I0_ipd'last_event, VitalExtendToFillDelay(tpd_I0_O), TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;

end VITAL;

configuration CFG_INVTH_VITAL of INVTH is
   for VITAL
   end for;
end CFG_INVTH_VITAL;


----- CELL INVTL -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity INVTL is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_OE_O                       :	VitalDelayType01z := (0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns, 0.010 ns);
      tpd_I0_O                       :	VitalDelayType01 := (0.010 ns, 0.010 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      OE                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of INVTL : entity is TRUE;
end INVTL;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of INVTL is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL OE_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (OE_ipd, OE, tipd_OE);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, OE_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalBUFIF0 (data => (NOT I0_ipd),
              enable => OE_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01Z (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (OE_ipd'last_event, VitalExtendToFillDelay(tpd_OE_O), TRUE),
                 1 => (I0_ipd'last_event, VitalExtendToFillDelay(tpd_I0_O), TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING,
       OutputMap => "UX01ZWLH-");

end process;

end VITAL;

configuration CFG_INVTL_VITAL of INVTL is
   for VITAL
   end for;
end CFG_INVTL_VITAL;


----- CELL LSB_CY -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LSB_CY is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LSB_CY : entity is TRUE;
end LSB_CY;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of LSB_CY is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS COUT_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      COUT_zd := TO_X01(I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_LSB_CY_VITAL of LSB_CY is
   for VITAL
   end for;
end CFG_LSB_CY_VITAL;


----- CELL LSB_CYI -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity LSB_CYI is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_COUT                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of LSB_CYI : entity is TRUE;
end LSB_CYI;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of LSB_CYI is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS COUT_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      COUT_zd := (NOT I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_LSB_CYI_VITAL of LSB_CYI is
   for VITAL
   end for;
end CFG_LSB_CYI_VITAL;

----- CELL MULTAND2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity MULTAND2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of MULTAND2 : entity is TRUE;
end MULTAND2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of MULTAND2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (I1_ipd) AND (I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_MULTAND2_VITAL of MULTAND2 is
   for VITAL
   end for;
end CFG_MULTAND2_VITAL;


----- CELL MUX2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity MUX2 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      S0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of MUX2 : entity is TRUE;
end MUX2;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of MUX2 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (S0_ipd, S0, tipd_S0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, S0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalMUX
                 (data => (I1_ipd, I0_ipd),
                  dselect => (0 => S0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (S0_ipd'last_event, tpd_S0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_MUX2_VITAL of MUX2 is
   for VITAL
   end for;
end CFG_MUX2_VITAL;

----- CELL MUXL6C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity MUXL6C is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      S0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of MUXL6C : entity is TRUE;
end MUXL6C;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of MUXL6C is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (S0_ipd, S0, tipd_S0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, S0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalMUX
                 (data => (I1_ipd, I0_ipd),
                  dselect => (0 => S0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (S0_ipd'last_event, tpd_S0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_MUXL6C_VITAL of MUXL6C is
   for VITAL
   end for;
end CFG_MUXL6C_VITAL;


----- CELL MUX2A -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity MUX2A is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      S0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of MUX2A : entity is TRUE;
end MUX2A;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of MUX2A is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (S0_ipd, S0, tipd_S0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, S0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       ((S0_ipd) AND (I1_ipd)) OR (((NOT S0_ipd)) AND ((NOT I0_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (S0_ipd'last_event, tpd_S0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_MUX2A_VITAL of MUX2A is
   for VITAL
   end for;
end CFG_MUX2A_VITAL;


----- CELL MUX2B -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity MUX2B is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      S0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of MUX2B : entity is TRUE;
end MUX2B;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of MUX2B is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (S0_ipd, S0, tipd_S0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, S0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       ((S0_ipd) AND ((NOT I1_ipd))) OR (((NOT S0_ipd)) AND (I0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (S0_ipd'last_event, tpd_S0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_MUX2B_VITAL of MUX2B is
   for VITAL
   end for;
end CFG_MUX2B_VITAL;


----- CELL MUX4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity MUX4 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      S0                             :	in    STD_ULOGIC;
      S1                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of MUX4 : entity is TRUE;
end MUX4;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of MUX4 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S1_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (S0_ipd, S0, tipd_S0);
   VitalWireDelay (S1_ipd, S1, tipd_S1);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, S0_ipd, S1_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalMUX
                 (data => (I3_ipd, I2_ipd, I1_ipd, I0_ipd),
                  dselect => (S1_ipd, S0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (S0_ipd'last_event, tpd_S0_O, TRUE),
                 5 => (S1_ipd'last_event, tpd_S1_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_MUX4_VITAL of MUX4 is
   for VITAL
   end for;
end CFG_MUX4_VITAL;


----- CELL MUX8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity MUX8 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I6_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I7_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC;
      I6                             :	in    STD_ULOGIC;
      I7                             :	in    STD_ULOGIC;
      S0                             :	in    STD_ULOGIC;
      S1                             :	in    STD_ULOGIC;
      S2                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of MUX8 : entity is TRUE;
end MUX8;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of MUX8 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I6_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I7_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S2_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   VitalWireDelay (I6_ipd, I6, tipd_I6);
   VitalWireDelay (I7_ipd, I7, tipd_I7);
   VitalWireDelay (S0_ipd, S0, tipd_S0);
   VitalWireDelay (S1_ipd, S1, tipd_S1);
   VitalWireDelay (S2_ipd, S2, tipd_S2);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd, I6_ipd, I7_ipd, S0_ipd, S1_ipd, S2_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalMUX
                 (data => (I7_ipd, I6_ipd, I5_ipd, I4_ipd, I3_ipd, I2_ipd, I1_ipd, I0_ipd),
                  dselect => (S2_ipd, S1_ipd, S0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE),
                 6 => (I6_ipd'last_event, tpd_I6_O, TRUE),
                 7 => (I7_ipd'last_event, tpd_I7_O, TRUE),
                 8 => (S0_ipd'last_event, tpd_S0_O, TRUE),
                 9 => (S1_ipd'last_event, tpd_S1_O, TRUE),
                 10 => (S2_ipd'last_event, tpd_S2_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_MUX8_VITAL of MUX8 is
   for VITAL
   end for;
end CFG_MUX8_VITAL;


----- CELL MUX8C -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity MUX8C is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I6_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I7_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_MI_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S3_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_MI                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC;
      I6                             :	in    STD_ULOGIC;
      I7                             :	in    STD_ULOGIC;
      MI                             :	in    STD_ULOGIC;
      S0                             :	in    STD_ULOGIC;
      S1                             :	in    STD_ULOGIC;
      S2                             :	in    STD_ULOGIC;
      S3                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of MUX8C : entity is TRUE;
end MUX8C;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of MUX8C is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I6_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I7_ipd	 : STD_ULOGIC := 'X';
   SIGNAL MI_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S3_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   VitalWireDelay (I6_ipd, I6, tipd_I6);
   VitalWireDelay (I7_ipd, I7, tipd_I7);
   VitalWireDelay (MI_ipd, MI, tipd_MI);
   VitalWireDelay (S0_ipd, S0, tipd_S0);
   VitalWireDelay (S1_ipd, S1, tipd_S1);
   VitalWireDelay (S2_ipd, S2, tipd_S2);
   VitalWireDelay (S3_ipd, S3, tipd_S3);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd, I6_ipd, I7_ipd, MI_ipd, S0_ipd, S1_ipd, S2_ipd, S3_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       ((S3_ipd) AND (MI_ipd)) OR ((((S0_ipd) AND (I1_ipd) AND ((NOT
         S1_ipd)) AND ((NOT S2_ipd))) OR (((NOT S0_ipd)) AND (I0_ipd) AND
         ((NOT S1_ipd)) AND ((NOT S2_ipd))) OR (((NOT S0_ipd)) AND (I2_ipd)
         AND (S1_ipd) AND ((NOT S2_ipd))) OR ((S0_ipd) AND (I3_ipd) AND
         (S1_ipd) AND ((NOT S2_ipd))) OR (((NOT S0_ipd)) AND (I4_ipd) AND
         ((NOT S1_ipd)) AND (S2_ipd)) OR ((S0_ipd) AND (I5_ipd) AND ((NOT
         S1_ipd)) AND (S2_ipd)) OR (((NOT S0_ipd)) AND (I6_ipd) AND (S1_ipd)
         AND (S2_ipd)) OR ((S0_ipd) AND (I7_ipd) AND (S1_ipd) AND (S2_ipd)))
         AND ((NOT S3_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE),
                 6 => (I6_ipd'last_event, tpd_I6_O, TRUE),
                 7 => (I7_ipd'last_event, tpd_I7_O, TRUE),
                 8 => (MI_ipd'last_event, tpd_MI_O, TRUE),
                 9 => (S0_ipd'last_event, tpd_S0_O, TRUE),
                 10 => (S1_ipd'last_event, tpd_S1_O, TRUE),
                 11 => (S2_ipd'last_event, tpd_S2_O, TRUE),
                 12 => (S3_ipd'last_event, tpd_S3_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_MUX8C_VITAL of MUX8C is
   for VITAL
   end for;
end CFG_MUX8C_VITAL;


----- CELL MUX16 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity MUX16 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I3_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I4_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I5_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I6_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I7_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I8_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I9_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I10_O                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I11_O                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I12_O                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I13_O                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I14_O                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I15_O                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S2_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S3_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I9                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I10                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I11                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I12                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I13                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I14                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I15                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      I2                             :	in    STD_ULOGIC;
      I3                             :	in    STD_ULOGIC;
      I4                             :	in    STD_ULOGIC;
      I5                             :	in    STD_ULOGIC;
      I6                             :	in    STD_ULOGIC;
      I7                             :	in    STD_ULOGIC;
      I8                             :	in    STD_ULOGIC;
      I9                             :	in    STD_ULOGIC;
      I10                            :	in    STD_ULOGIC;
      I11                            :	in    STD_ULOGIC;
      I12                            :	in    STD_ULOGIC;
      I13                            :	in    STD_ULOGIC;
      I14                            :	in    STD_ULOGIC;
      I15                            :	in    STD_ULOGIC;
      S0                             :	in    STD_ULOGIC;
      S1                             :	in    STD_ULOGIC;
      S2                             :	in    STD_ULOGIC;
      S3                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of MUX16 : entity is TRUE;
end MUX16;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of MUX16 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I4_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I5_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I6_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I7_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I8_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I9_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I10_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I11_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I12_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I13_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I14_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I15_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S3_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (I2_ipd, I2, tipd_I2);
   VitalWireDelay (I3_ipd, I3, tipd_I3);
   VitalWireDelay (I4_ipd, I4, tipd_I4);
   VitalWireDelay (I5_ipd, I5, tipd_I5);
   VitalWireDelay (I6_ipd, I6, tipd_I6);
   VitalWireDelay (I7_ipd, I7, tipd_I7);
   VitalWireDelay (I8_ipd, I8, tipd_I8);
   VitalWireDelay (I9_ipd, I9, tipd_I9);
   VitalWireDelay (I10_ipd, I10, tipd_I10);
   VitalWireDelay (I11_ipd, I11, tipd_I11);
   VitalWireDelay (I12_ipd, I12, tipd_I12);
   VitalWireDelay (I13_ipd, I13, tipd_I13);
   VitalWireDelay (I14_ipd, I14, tipd_I14);
   VitalWireDelay (I15_ipd, I15, tipd_I15);
   VitalWireDelay (S0_ipd, S0, tipd_S0);
   VitalWireDelay (S1_ipd, S1, tipd_S1);
   VitalWireDelay (S2_ipd, S2, tipd_S2);
   VitalWireDelay (S3_ipd, S3, tipd_S3);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, I2_ipd, I3_ipd, I4_ipd, I5_ipd, I6_ipd, I7_ipd, I8_ipd, I9_ipd, I10_ipd, I11_ipd, I12_ipd, I13_ipd, I14_ipd, I15_ipd, S0_ipd, S1_ipd, S2_ipd, S3_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd :=
       ((((S0_ipd) AND (I9_ipd) AND ((NOT S1_ipd)) AND ((NOT S2_ipd))) OR
         (((NOT S0_ipd)) AND (I8_ipd) AND ((NOT S1_ipd)) AND ((NOT S2_ipd)))
         OR (((NOT S0_ipd)) AND (I10_ipd) AND (S1_ipd) AND (S2_ipd)) OR
         ((S0_ipd) AND (I11_ipd) AND (S1_ipd) AND (S2_ipd)) OR (((NOT
         S0_ipd)) AND (I12_ipd) AND ((NOT S1_ipd)) AND (S2_ipd)) OR ((S0_ipd)
         AND (I13_ipd) AND ((NOT S1_ipd)) AND (S2_ipd)) OR (((NOT S0_ipd))
         AND (I14_ipd) AND (S1_ipd) AND (S2_ipd)) OR ((S0_ipd) AND (I15_ipd)
         AND (S1_ipd) AND (S2_ipd))) AND (S3_ipd)) OR ((((S0_ipd) AND
         (I1_ipd) AND ((NOT S1_ipd)) AND ((NOT S2_ipd))) OR (((NOT S0_ipd))
         AND (I0_ipd) AND ((NOT S1_ipd)) AND ((NOT S2_ipd))) OR (((NOT
         S0_ipd)) AND (I2_ipd) AND (S1_ipd) AND (S2_ipd)) OR ((S0_ipd) AND
         (I3_ipd) AND (S1_ipd) AND (S2_ipd)) OR (((NOT S0_ipd)) AND (I4_ipd)
         AND ((NOT S1_ipd)) AND (S2_ipd)) OR ((S0_ipd) AND (I5_ipd) AND ((NOT
         S1_ipd)) AND (S2_ipd)) OR (((NOT S0_ipd)) AND (I6_ipd) AND (S1_ipd)
         AND (S2_ipd)) OR ((S0_ipd) AND (I7_ipd) AND (S1_ipd) AND (S2_ipd)))
         AND ((NOT S3_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (I2_ipd'last_event, tpd_I2_O, TRUE),
                 3 => (I3_ipd'last_event, tpd_I3_O, TRUE),
                 4 => (I4_ipd'last_event, tpd_I4_O, TRUE),
                 5 => (I5_ipd'last_event, tpd_I5_O, TRUE),
                 6 => (I6_ipd'last_event, tpd_I6_O, TRUE),
                 7 => (I7_ipd'last_event, tpd_I7_O, TRUE),
                 8 => (I8_ipd'last_event, tpd_I8_O, TRUE),
                 9 => (I9_ipd'last_event, tpd_I9_O, TRUE),
                 10 => (I10_ipd'last_event, tpd_I10_O, TRUE),
                 11 => (I11_ipd'last_event, tpd_I11_O, TRUE),
                 12 => (I12_ipd'last_event, tpd_I12_O, TRUE),
                 13 => (I13_ipd'last_event, tpd_I13_O, TRUE),
                 14 => (I14_ipd'last_event, tpd_I14_O, TRUE),
                 15 => (I15_ipd'last_event, tpd_I15_O, TRUE),
                 16 => (S0_ipd'last_event, tpd_S0_O, TRUE),
                 17 => (S1_ipd'last_event, tpd_S1_O, TRUE),
                 18 => (S2_ipd'last_event, tpd_S2_O, TRUE),
                 19 => (S3_ipd'last_event, tpd_S3_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_MUX16_VITAL of MUX16 is
   for VITAL
   end for;
end CFG_MUX16_VITAL;


----- CELL MUXL5 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity MUXL5 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      S0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of MUXL5 : entity is TRUE;
end MUXL5;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of MUXL5 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (S0_ipd, S0, tipd_S0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, S0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalMUX
                 (data => (I1_ipd, I0_ipd),
                  dselect => (0 => S0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (S0_ipd'last_event, tpd_S0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_MUXL5_VITAL of MUXL5 is
   for VITAL
   end for;
end CFG_MUXL5_VITAL;


----- CELL MUXL6 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity MUXL6 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_I1_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_S0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_S0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      I1                             :	in    STD_ULOGIC;
      S0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of MUXL6 : entity is TRUE;
end MUXL6;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of MUXL6 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';
   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL S0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   VitalWireDelay (I1_ipd, I1, tipd_I1);
   VitalWireDelay (S0_ipd, S0, tipd_S0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd, I1_ipd, S0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := VitalMUX
                 (data => (I1_ipd, I0_ipd),
                  dselect => (0 => S0_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE),
                 1 => (I1_ipd'last_event, tpd_I1_O, TRUE),
                 2 => (S0_ipd'last_event, tpd_S0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_MUXL6_VITAL of MUXL6 is
   for VITAL
   end for;
end CFG_MUXL6_VITAL;


----- CELL OBUF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity OBUF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of OBUF : entity is TRUE;
end OBUF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of OBUF is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := TO_X01(I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_OBUF_VITAL of OBUF is
   for VITAL
   end for;
end CFG_OBUF_VITAL;

----- CELL OBUFINV -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity OBUFINV is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_I0_O                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      I0                             :	in    STD_ULOGIC;
      O                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of OBUFINV : entity is TRUE;
end OBUFINV;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of OBUFINV is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (I0_ipd, I0, tipd_I0);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (I0_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS O_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE O_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      O_zd := (NOT I0_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => O,
       GlitchData => O_GlitchData,
       OutSignalName => "O",
       OutTemp => O_zd,
       Paths => (0 => (I0_ipd'last_event, tpd_I0_O, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_OBUFINV_VITAL of OBUFINV is
   for VITAL
   end for;
end CFG_OBUFINV_VITAL;

----- CELL RAM16X1D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.VITAL_Timing.all; 
use IEEE.VITAL_Primitives.all;

library lava1;
use lava1.RAM_PACKAGE.all;

entity RAM16X1D is

  generic (
       TimingChecksOn: Boolean := TRUE;
       InstancePath:   STRING  := "*";
       Xon:  Boolean := True;
       MsgOn:  Boolean := False;

       tipd_AD0                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_AD1                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_AD2                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_AD3                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD0                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD1                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD2                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD3                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_WDATA                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_WE                           :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_WCLK                         :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tpd_AD0_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_AD1_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_AD2_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_AD3_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_WCLK_RDATA                    :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_DPAD0_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_DPAD1_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns); 
       tpd_DPAD2_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_DPAD3_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_WCLK_DPRDATA                  :      VitalDelayType01 := (0.0 ns, 0.0 ns); 
       tsetup_WDATA_WCLK_noedge_posedge  :      VitalDelayType := 0.1 ns;
       thold_WDATA_WCLK_noedge_posedge   :      VitalDelayType := 0.0 ns;
       tsetup_WE_WCLK_noedge_posedge     :      VitalDelayType := 0.1 ns;
       thold_WE_WCLK_noedge_posedge      :      VitalDelayType := 0.0 ns;
       tsetup_AD0_WCLK_noedge_posedge    :      VitalDelayType := 0.1 ns;
       thold_AD0_WCLK_noedge_posedge     :      VitalDelayType := 0.0 ns;
       tsetup_AD1_WCLK_noedge_posedge    :      VitalDelayType := 0.1 ns;
       thold_AD1_WCLK_noedge_posedge     :      VitalDelayType := 0.0 ns;
       tsetup_AD2_WCLK_noedge_posedge    :      VitalDelayType := 0.1 ns;
       thold_AD2_WCLK_noedge_posedge     :      VitalDelayType := 0.0 ns;
       tsetup_AD3_WCLK_noedge_posedge    :      VitalDelayType := 0.1 ns;
       thold_AD3_WCLK_noedge_posedge     :      VitalDelayType := 0.0 ns;
       tpw_WCLK_posedge                  :      VitalDelayType := 2.0 ns;
       tpw_WCLK_negedge                  :      VitalDelayType := 2.0 ns;

       INIT                              :      bit_vector(15 downto 0) := X"FFFF"
  );

  port (WDATA   : in std_ulogic;
        WE      : in std_ulogic;
        WCLK    : in std_ulogic;
        AD0     : in std_ulogic;
        AD1     : in std_ulogic;
        AD2     : in std_ulogic;
        AD3     : in std_ulogic;
        DPAD0   : in std_ulogic;
        DPAD1   : in std_ulogic;
        DPAD2   : in std_ulogic;
        DPAD3   : in std_ulogic;

        RDATA   : out std_ulogic;
        DPRDATA : out std_ulogic
       ); 
attribute VITAL_LEVEL0 of RAM16X1D : entity is TRUE;

end RAM16X1D;

-----------------------------------------------------------------------------

architecture VITAL of RAM16X1D is

  attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

  -- Local signals used to propagate input wire delay

    signal AD0_ipd    : std_ulogic := 'X';
    signal AD1_ipd    : std_ulogic := 'X';
    signal AD2_ipd    : std_ulogic := 'X';
    signal AD3_ipd    : std_ulogic := 'X';

    signal DPAD0_ipd  : std_ulogic := 'X';
    signal DPAD1_ipd  : std_ulogic := 'X';
    signal DPAD2_ipd  : std_ulogic := 'X';
    signal DPAD3_ipd  : std_ulogic := 'X';

    signal WDATA_ipd  : std_ulogic := 'X';
    signal WE_ipd     : std_ulogic := 'X';
    signal WCLK_ipd   : std_ulogic := 'X';
    signal MEM        : std_logic_vector( 15 downto 0 ) := To_StdLogicVector(INIT);
    signal WE_AD      : std_ulogic := 'X';
    signal AD         : std_ulogic_vector(3 downto 0);
    signal DPAD       : std_ulogic_vector(3 downto 0);
    signal WDATA_c    : std_ulogic := '0';

begin -- architecture

	AD <= AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd ;
	DPAD <= DPAD3_ipd & DPAD2_ipd & DPAD1_ipd & DPAD0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
  WireDelay : block
  begin
    VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
    VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
    VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
    VitalWireDelay (AD3_ipd, AD3, tipd_AD3);

    VitalWireDelay (DPAD0_ipd, DPAD0, tipd_DPAD0);
    VitalWireDelay (DPAD1_ipd, DPAD1, tipd_DPAD1);
    VitalWireDelay (DPAD2_ipd, DPAD2, tipd_DPAD2);
    VitalWireDelay (DPAD3_ipd, DPAD3, tipd_DPAD3);

    VitalWireDelay (WDATA_ipd, WDATA, tipd_WDATA);
    VitalWireDelay (WE_ipd,    WE,    tipd_WE);
    VitalWireDelay (WCLK_ipd,  WCLK,  tipd_WCLK);
  end block;

process(WE_ipd,AD,WCLK_ipd,DPAD)
begin
if (WE_ipd = '1' and WCLK_ipd'event and WCLK_ipd='1' and AD = DPAD) then
	  WE_AD <= '1';
else
	  WE_AD <= '0';
end if;
end process;

process(WE_ipd, WCLK_ipd, WDATA_ipd)
begin
if (WCLK_ipd'event and WCLK_ipd='1') then
    if (WE_ipd = '1') then
	  WDATA_c <= WDATA_ipd;
    end if;
end if;
end process;


 VITALBehavior_Write : process

    -- Local variables used for functionality
    variable Index_A       : integer := 16;
    variable Index_B       : integer := 16;
    variable PrevData      : std_logic_vector(0 to 4) := (others => '0');
    variable WE_prev       : std_ulogic := 'X';
    variable WCLK_prev     : std_ulogic := 'X';
    variable WDATA_prev    : std_ulogic := 'X';
    variable Initial       : boolean := TRUE;

    -- Local variables used for timing checks
    variable Tviol_WDATA_WCLK_posedge  : std_ulogic := '0';
    variable Tviol_WE_WCLK_posedge     : std_ulogic := '0';
    variable Tviol_AD0_WCLK_posedge    : std_ulogic := '0';
    variable Tviol_AD1_WCLK_posedge    : std_ulogic := '0';
    variable Tviol_AD2_WCLK_posedge    : std_ulogic := '0';
    variable Tviol_AD3_WCLK_posedge    : std_ulogic := '0';

    variable Tmkr_WDATA_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

    variable PViol_WCLK                : std_ulogic := '0';
    variable PInfo_WCLK                : VitalPeriodDataType := VitalPeriodDataInit;

    -- Local variables used for functionality
    variable OA_zd                     : std_ulogic := 'X';
    variable OB_zd                     : std_ulogic := 'X';
    variable WE_inverted               : std_ulogic := 'X';
    variable Violation                 : std_ulogic := '0';

  begin -- process

    if (Initial) then
        wait until ( (WCLK_ipd = '0' or WCLK_ipd = '1') and
                    (WE_ipd  = '0' or WE_ipd = '1') and
                    (AD3_ipd = '0' or AD3_ipd = '1') and
                    (AD2_ipd = '0' or AD2_ipd = '1') and
                    (AD1_ipd = '0' or AD1_ipd = '1') and
                    (AD0_ipd = '0' or AD0_ipd = '1') );
        WCLK_prev   := WCLK_ipd;
        WE_prev     := WE_ipd;
        WDATA_prev  := WDATA_ipd;
        Index_A     := ADDR4_TO_INT(ADDRESS => (AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        OA_zd       := MEM(Index_A);
        Initial     := FALSE;

    end if;
    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn ) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WDATA_WCLK_posedge,
          TimingData              => Tmkr_WDATA_WCLK_posedge,
          TestSignal              => WDATA_ipd,
          TestSignalName          => "WDATA",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WDATA_WCLK_noedge_posedge,
          SetupLow                => tsetup_WDATA_WCLK_noedge_posedge,
          HoldLow                 => thold_WDATA_WCLK_noedge_posedge,
          HoldHigh                => thold_WDATA_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM16X1D",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM16X1D",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_WCLK_posedge,
          TimingData              => Tmkr_AD0_WCLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD0_WCLK_noedge_posedge,
          HoldLow                 => thold_AD0_WCLK_noedge_posedge,
          HoldHigh                => thold_AD0_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM16X1D",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_WCLK_posedge,
          TimingData              => Tmkr_AD1_WCLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD1_WCLK_noedge_posedge,
          HoldLow                 => thold_AD1_WCLK_noedge_posedge,
          HoldHigh                => thold_AD1_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM16X1D",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_WCLK_posedge,
          TimingData              => Tmkr_AD2_WCLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD2_WCLK_noedge_posedge,
          HoldLow                 => thold_AD2_WCLK_noedge_posedge,
          HoldHigh                => thold_AD2_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM16X1D",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_WCLK_posedge,
          TimingData              => Tmkr_AD3_WCLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD3_WCLK_noedge_posedge,
          HoldLow                 => thold_AD3_WCLK_noedge_posedge,
          HoldHigh                => thold_AD3_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM16X1D",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAM16X1D",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WDATA_WCLK_posedge or Tviol_WDATA_WCLK_posedge or 
                 Tviol_AD0_WCLK_posedge or Tviol_AD1_WCLK_posedge or 
                 Tviol_AD2_WCLK_posedge or Tviol_AD3_WCLK_posedge or 
                 Pviol_WCLK;

    -------------------------
    --  Functionality Section
    -------------------------
    Index_A := ADDR4_TO_INT(ADDRESS => (AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
    WE_inverted := (NOT WE_ipd);
    OA_zd   := MEM(Index_A);

    VitalStateTable(Result => OA_zd,
                    PreviousDataIn => PrevData,
                    StateTable => RAMS_RDATA_tab,
                    DataIn => (WCLK_prev, OA_zd, WDATA_prev, WE_inverted, WCLK_ipd));

    OA_zd := Violation XOR OA_zd;

    --WE_prev       :=   WE_ipd;
    WE_prev       :=   WE_inverted;
    WCLK_prev     :=   WCLK_ipd;
    WDATA_prev    :=   WDATA_ipd;

    MEM(Index_A) <= OA_zd;

    wait on AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, WDATA_ipd, WCLK_ipd, WE_ipd;

  end process VITALBehavior_Write;

  --------------------
  -- RAM16X1D Behavior
  --------------------
 VITALBehavior_Read : process(AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, 
    DPAD0_ipd, DPAD1_ipd, DPAD2_ipd, DPAD3_ipd, MEM, WDATA_c, WE_ipd, WE_AD)

    Variable Index_A       :   integer  := 15 ;
    Variable Index_B       :   integer  := 15 ;
    Variable OA_zd         :   std_ulogic := 'X';
    Variable OA_zd1        :   std_ulogic := 'X';
    Variable OB_zd         :   std_ulogic := 'X';
    Variable OB_zd1        :   std_ulogic := 'X';
    Variable OA_GlitchData :   VitalGlitchDataType;
    Variable OB_GlitchData :   VitalGlitchDataType;

    begin -- process

    Index_A := ADDR4_TO_INT (ADDRESS => (AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
    Index_B := ADDR4_TO_INT (ADDRESS => (DPAD3_ipd, DPAD2_ipd, DPAD1_ipd, DPAD0_ipd));

    OA_zd   := MEM(Index_A);
    OB_zd   := MEM(Index_B);

    OA_zd1 := VitalMUX2
		     (data0 => OA_zd, 
		      data1 => WDATA_c,
		      dselect => WE_ipd);

    OB_zd1 := VitalMUX2
		     (data0 => OB_zd, 
		      data1 => OA_zd,
		      dselect => WE_AD);

    VitalPathDelay01 (
     OutSignal => RDATA,
     GlitchData => OA_GlitchData,
     OutSignalName => "RDATA",
     OutTemp => OA_zd1,
     Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_RDATA, TRUE),
               1 => (AD0_ipd'last_event, tpd_AD0_RDATA, TRUE),
               2 => (AD1_ipd'last_event, tpd_AD1_RDATA, TRUE),
               3 => (AD2_ipd'last_event, tpd_AD2_RDATA, TRUE),
               4 => (AD3_ipd'last_event, tpd_AD3_RDATA, TRUE)),
     Mode => OnEvent,
     Xon => Xon,
     MsgOn => MsgOn,
     MsgSeverity => WARNING);

     VitalPathDelay01 (
     OutSignal => DPRDATA,
     GlitchData => OB_GlitchData,
     OutSignalName => "DPRDATA",
     OutTemp => OB_zd1,
     Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_DPRDATA, TRUE),
               1 => (DPAD0_ipd'last_event, tpd_DPAD0_DPRDATA, TRUE),
               2 => (DPAD1_ipd'last_event, tpd_DPAD1_DPRDATA, TRUE),
               3 => (DPAD2_ipd'last_event, tpd_DPAD2_DPRDATA, TRUE),
               4 => (DPAD3_ipd'last_event, tpd_DPAD3_DPRDATA, TRUE)),
     Mode => OnEvent,
     Xon => Xon,
     MsgOn => MsgOn,
     MsgSeverity => WARNING);
 end process VITALBehavior_Read;

end VITAL;
 
configuration CFG_RAM16X1D_VITAL of RAM16X1D is
   for VITAL
   end for;
end CFG_RAM16X1D_VITAL;


----- CELL RAM16X1D_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.VITAL_Timing.all; 
use IEEE.VITAL_Primitives.all;

library lava1;
use lava1.RAM_PACKAGE.all;

entity RAM16X1D_1 is

  generic (
       TimingChecksOn: Boolean := TRUE;
       InstancePath:   STRING  := "*";
       Xon:  Boolean := True;
       MsgOn:  Boolean := False;

       tipd_AD0                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_AD1                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_AD2                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_AD3                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD0                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD1                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD2                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD3                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_WDATA                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_WE                           :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_WCLK                         :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tpd_AD0_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_AD1_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_AD2_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_AD3_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_WCLK_RDATA                    :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_DPAD0_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_DPAD1_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns); 
       tpd_DPAD2_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_DPAD3_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_WCLK_DPRDATA                  :      VitalDelayType01 := (0.0 ns, 0.0 ns); 
       tsetup_WDATA_WCLK_noedge_negedge  :      VitalDelayType := 0.1 ns;
       thold_WDATA_WCLK_noedge_negedge   :      VitalDelayType := 0.0 ns;
       tsetup_WE_WCLK_noedge_negedge     :      VitalDelayType := 0.1 ns;
       thold_WE_WCLK_noedge_negedge      :      VitalDelayType := 0.0 ns;
       tsetup_AD0_WCLK_noedge_negedge    :      VitalDelayType := 0.1 ns;
       thold_AD0_WCLK_noedge_negedge     :      VitalDelayType := 0.0 ns;
       tsetup_AD1_WCLK_noedge_negedge    :      VitalDelayType := 0.1 ns;
       thold_AD1_WCLK_noedge_negedge     :      VitalDelayType := 0.0 ns;
       tsetup_AD2_WCLK_noedge_negedge    :      VitalDelayType := 0.1 ns;
       thold_AD2_WCLK_noedge_negedge     :      VitalDelayType := 0.0 ns;
       tsetup_AD3_WCLK_noedge_negedge    :      VitalDelayType := 0.1 ns;
       thold_AD3_WCLK_noedge_negedge     :      VitalDelayType := 0.0 ns;
       tpw_WCLK_posedge                  :      VitalDelayType := 2.0 ns;
       tpw_WCLK_negedge                  :      VitalDelayType := 2.0 ns;

       INIT                              :      bit_vector(15 downto 0) := X"FFFF"
  );

  port (WDATA   : in std_ulogic;
        WE      : in std_ulogic;
        WCLK    : in std_ulogic;
        AD0     : in std_ulogic;
        AD1     : in std_ulogic;
        AD2     : in std_ulogic;
        AD3     : in std_ulogic;
        DPAD0   : in std_ulogic;
        DPAD1   : in std_ulogic;
        DPAD2   : in std_ulogic;
        DPAD3   : in std_ulogic;

        RDATA   : out std_ulogic;
        DPRDATA : out std_ulogic
       ); 
attribute VITAL_LEVEL0 of RAM16X1D_1 : entity is TRUE;

end RAM16X1D_1;

-----------------------------------------------------------------------------

architecture VITAL of RAM16X1D_1 is

  attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

  -- Local signals used to propagate input wire delay

    signal AD0_ipd    : std_ulogic := 'X';
    signal AD1_ipd    : std_ulogic := 'X';
    signal AD2_ipd    : std_ulogic := 'X';
    signal AD3_ipd    : std_ulogic := 'X';

    signal DPAD0_ipd  : std_ulogic := 'X';
    signal DPAD1_ipd  : std_ulogic := 'X';
    signal DPAD2_ipd  : std_ulogic := 'X';
    signal DPAD3_ipd  : std_ulogic := 'X';

    signal WDATA_ipd  : std_ulogic := 'X';
    signal WE_ipd     : std_ulogic := 'X';
    signal WCLK_ipd   : std_ulogic := 'X';
    signal MEM        : std_logic_vector( 15 downto 0 ) := To_StdLogicVector(INIT);
    signal WE_AD      : std_ulogic := 'X';
    signal AD         : std_ulogic_vector(3 downto 0);
    signal DPAD         : std_ulogic_vector(3 downto 0);
    signal WDATA_c    : std_ulogic := '0';

begin -- architecture

	AD <= AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd ;
	DPAD <= DPAD3_ipd & DPAD2_ipd & DPAD1_ipd & DPAD0_ipd ;
  ----------------------
  --  Wire Delay Section
  ----------------------
  WireDelay : block
  begin
    VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
    VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
    VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
    VitalWireDelay (AD3_ipd, AD3, tipd_AD3);

    VitalWireDelay (DPAD0_ipd, DPAD0, tipd_DPAD0);
    VitalWireDelay (DPAD1_ipd, DPAD1, tipd_DPAD1);
    VitalWireDelay (DPAD2_ipd, DPAD2, tipd_DPAD2);
    VitalWireDelay (DPAD3_ipd, DPAD3, tipd_DPAD3);

    VitalWireDelay (WDATA_ipd, WDATA, tipd_WDATA);
    VitalWireDelay (WE_ipd,    WE,    tipd_WE);
    VitalWireDelay (WCLK_ipd,  WCLK,  tipd_WCLK);
  end block;


process(WE_ipd,AD,DPAD)
begin
if (WE_ipd = '1' and AD = DPAD) then
	  WE_AD <= '1';
else
	  WE_AD <= '0';
end if;
end process;

process(WE_ipd, WCLK_ipd, WDATA_ipd)
begin
if (WCLK_ipd'event and WCLK_ipd='1') then
    if (WE_ipd = '1') then
	  WDATA_c <= WDATA_ipd;
    end if;
end if;
end process;


 VITALBehavior_Write : process

    -- Local variables used for functionality
    variable Index_A       : integer := 16;
    variable Index_B       : integer := 16;
    variable PrevData      : std_logic_vector(0 to 4) := (others => '0');
    variable WE_prev       : std_ulogic := 'X';
    variable WCLK_prev     : std_ulogic := 'X';
    variable WDATA_prev    : std_ulogic := 'X';
    variable Initial       : boolean := TRUE;

    -- Local variables used for timing checks
    variable Tviol_WDATA_WCLK_posedge  : std_ulogic := '0';
    variable Tviol_WE_WCLK_posedge     : std_ulogic := '0';
    variable Tviol_AD0_WCLK_posedge    : std_ulogic := '0';
    variable Tviol_AD1_WCLK_posedge    : std_ulogic := '0';
    variable Tviol_AD2_WCLK_posedge    : std_ulogic := '0';
    variable Tviol_AD3_WCLK_posedge    : std_ulogic := '0';

    variable Tmkr_WDATA_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

    variable PViol_WCLK                : std_ulogic := '0';
    variable PInfo_WCLK                : VitalPeriodDataType := VitalPeriodDataInit;

    -- Local variables used for functionality
    variable OA_zd                     : std_ulogic := 'X';
    variable OB_zd                     : std_ulogic := 'X';
    variable WE_inverted               : std_ulogic := 'X';
    variable WCLK_inverted             : std_ulogic := 'X';
    variable Violation                 : std_ulogic := '0';

  begin -- process

    if (Initial) then
        wait until ( (WCLK_ipd = '0' or WCLK_ipd = '1') and
                    (WE_ipd  = '0' or WE_ipd = '1') and
                    (AD3_ipd = '0' or AD3_ipd = '1') and
                    (AD2_ipd = '0' or AD2_ipd = '1') and
                    (AD1_ipd = '0' or AD1_ipd = '1') and
                    (AD0_ipd = '0' or AD0_ipd = '1') );
        WCLK_prev   := WCLK_ipd;
        WE_prev     := WE_ipd;
        WDATA_prev  := WDATA_ipd;
        Index_A     := ADDR4_TO_INT(ADDRESS => (AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        OA_zd       := MEM(Index_A);
        Initial     := FALSE;

    end if;
    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn ) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WDATA_WCLK_posedge,
          TimingData              => Tmkr_WDATA_WCLK_posedge,
          TestSignal              => WDATA_ipd,
          TestSignalName          => "WDATA",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WDATA_WCLK_noedge_negedge,
          SetupLow                => tsetup_WDATA_WCLK_noedge_negedge,
          HoldLow                 => thold_WDATA_WCLK_noedge_negedge,
          HoldHigh                => thold_WDATA_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM16X1D_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_negedge,
          SetupLow                => tsetup_WE_WCLK_noedge_negedge,
          HoldLow                 => thold_WE_WCLK_noedge_negedge,
          HoldHigh                => thold_WE_WCLK_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM16X1D_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_WCLK_posedge,
          TimingData              => Tmkr_AD0_WCLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD0_WCLK_noedge_negedge,
          HoldLow                 => thold_AD0_WCLK_noedge_negedge,
          HoldHigh                => thold_AD0_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM16X1D_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_WCLK_posedge,
          TimingData              => Tmkr_AD1_WCLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD1_WCLK_noedge_negedge,
          HoldLow                 => thold_AD1_WCLK_noedge_negedge,
          HoldHigh                => thold_AD1_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM16X1D_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_WCLK_posedge,
          TimingData              => Tmkr_AD2_WCLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD2_WCLK_noedge_negedge,
          HoldLow                 => thold_AD2_WCLK_noedge_negedge,
          HoldHigh                => thold_AD2_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM16X1D_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_WCLK_posedge,
          TimingData              => Tmkr_AD3_WCLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD3_WCLK_noedge_negedge,
          HoldLow                 => thold_AD3_WCLK_noedge_negedge,
          HoldHigh                => thold_AD3_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM16X1D_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAM16X1D_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WDATA_WCLK_posedge or Tviol_WDATA_WCLK_posedge or 
                 Tviol_AD0_WCLK_posedge or Tviol_AD1_WCLK_posedge or 
                 Tviol_AD2_WCLK_posedge or Tviol_AD3_WCLK_posedge or 
                 Pviol_WCLK;

    -------------------------
    --  Functionality Section
    -------------------------
    Index_A := ADDR4_TO_INT(ADDRESS => (AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
    WE_inverted := (NOT WE_ipd);
    WCLK_inverted := (NOT WCLK_ipd);
    OA_zd   := MEM(Index_A);

    VitalStateTable(Result => OA_zd,
                    PreviousDataIn => PrevData,
                    StateTable => RAMS_RDATA_tab,
                    DataIn => (WCLK_prev, OA_zd, WDATA_prev, WE_inverted, WCLK_inverted));

    OA_zd := Violation XOR OA_zd;

    --WE_prev       :=   WE_ipd;
    WE_prev       :=   WE_inverted;
--    WCLK_prev     :=   WCLK_ipd;
    WCLK_prev     :=   WCLK_inverted;
    WDATA_prev    :=   WDATA_ipd;

    MEM(Index_A) <= OA_zd;

    wait on AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, WDATA_ipd, WCLK_ipd, WE_ipd;

  end process VITALBehavior_Write;

  --------------------
  -- RAM16X1D_1 Behavior
  --------------------
 VITALBehavior_Read : process(AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, 
    DPAD0_ipd, DPAD1_ipd, DPAD2_ipd, DPAD3_ipd, MEM, WDATA_c, WE_ipd, WE_AD)

    Variable Index_A       :   integer  := 15 ;
    Variable Index_B       :   integer  := 15 ;
    Variable OA_zd         :   std_ulogic := 'X';
    Variable OA_zd1        :   std_ulogic := 'X';
    Variable OB_zd         :   std_ulogic := 'X';
    Variable OB_zd1        :   std_ulogic := 'X';
    Variable OA_GlitchData :   VitalGlitchDataType;
    Variable OB_GlitchData :   VitalGlitchDataType;

    begin -- process

    Index_A := ADDR4_TO_INT (ADDRESS => (AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
    Index_B := ADDR4_TO_INT (ADDRESS => (DPAD3_ipd, DPAD2_ipd, DPAD1_ipd, DPAD0_ipd));

    OA_zd   := MEM(Index_A);
    OB_zd   := MEM(Index_B);

    OA_zd1 := VitalMUX2
		     (data0 => OA_zd, 
		      data1 => WDATA_c,
		      dselect => WE_ipd);

    OB_zd1 := VitalMUX2
		     (data0 => OB_zd, 
		      data1 => OA_zd,
		      dselect => WE_AD);

    VitalPathDelay01 (
     OutSignal => RDATA,
     GlitchData => OA_GlitchData,
     OutSignalName => "RDATA",
     OutTemp => OA_zd1,
     Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_RDATA, TRUE),
               1 => (AD0_ipd'last_event, tpd_AD0_RDATA, TRUE),
               2 => (AD1_ipd'last_event, tpd_AD1_RDATA, TRUE),
               3 => (AD2_ipd'last_event, tpd_AD2_RDATA, TRUE),
               4 => (AD3_ipd'last_event, tpd_AD3_RDATA, TRUE)),
     Mode => OnEvent,
     Xon => Xon,
     MsgOn => MsgOn,
     MsgSeverity => WARNING);

     VitalPathDelay01 (
     OutSignal => DPRDATA,
     GlitchData => OB_GlitchData,
     OutSignalName => "DPRDATA",
     OutTemp => OB_zd1,
     Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_DPRDATA, TRUE),
               1 => (DPAD0_ipd'last_event, tpd_DPAD0_DPRDATA, TRUE),
               2 => (DPAD1_ipd'last_event, tpd_DPAD1_DPRDATA, TRUE),
               3 => (DPAD2_ipd'last_event, tpd_DPAD2_DPRDATA, TRUE),
               4 => (DPAD3_ipd'last_event, tpd_DPAD3_DPRDATA, TRUE)),
     Mode => OnEvent,
     Xon => Xon,
     MsgOn => MsgOn,
     MsgSeverity => WARNING);
 end process VITALBehavior_Read;

end VITAL;
 
configuration CFG_RAM16X1D_1_VITAL of RAM16X1D_1 is
   for VITAL
   end for;
end CFG_RAM16X1D_1_VITAL;


----- CELL RAM16X1S -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


library lava1;
use lava1.RAM_PACKAGE.all;


-- entity declaration --
entity RAM16X1S is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_AD0_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_RDATA                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WE_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WDATA_WCLK_noedge_posedge :	VitalDelayType   := 0.1 ns;
      thold_WDATA_WCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_AD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tpw_WCLK_posedge                 :	VitalDelayType   := 2.0 ns;
      tipd_WE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WDATA                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT                             :	bit_vector := X"FFFF");

   port(
      WE                             :	in    STD_ULOGIC;
      WDATA                          :	in    STD_ULOGIC;
      WCLK                           :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      RDATA                          :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAM16X1S : entity is TRUE;
end RAM16X1S;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAM16X1S is
  attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';

      signal WDATA_ipd    : std_ulogic := 'X';
      signal WE_ipd       : std_ulogic := 'X';
      signal WCLK_ipd     : std_ulogic := 'X';

      signal MEM          : std_logic_vector( 15 downto 0 ) := ( To_StdLogicVector(INIT)) ;

begin 

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin
        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);

        VitalWireDelay (WDATA_ipd,  WDATA, tipd_WDATA);
        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
      end block;

      --------------------
      -- RAM16X1S Write Behavior
      --------------------
      VITALBehavior_Write : process
        -- Local variables used for timing checks

        variable Tviol_WDATA_WCLK_posedge  : std_ulogic  := '0';
        variable Tviol_WE_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_AD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_WCLK_posedge    : std_ulogic  := '0';

        variable Tmkr_WDATA_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        variable Initial          : boolean := TRUE;
        variable Violation        : std_ulogic := '0';
        variable INIT_BITS        : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT);
        variable Index            : integer := 16;
        variable PrevData         : std_logic_vector(0 to 4) := (others => '0');
        variable WE_prev          : std_ulogic := 'X';
        variable WCLK_prev        : std_ulogic := 'X';
        variable WDATA_prev       : std_ulogic := 'X';
        variable O_zd             : std_ulogic := 'X';
        variable O_GlitchData     : VitalGlitchDataType;
        variable WE_inverted      : std_ulogic := 'X';

        begin


        if (Initial) then
        wait until ((WCLK_ipd = '0' or WCLK_ipd = '1') and
                    (AD3_ipd = '0' or AD3_ipd = '1') and
                    (AD2_ipd = '0' or AD2_ipd = '1') and
                    (AD1_ipd = '0' or AD1_ipd = '1') and
                    (AD0_ipd = '0' or AD0_ipd = '1'));
        WCLK_prev  := WCLK_ipd;
        WE_prev    := WE_ipd;
        WDATA_prev := WDATA_ipd;
        Index      := ADDR4_TO_INT(ADDRESS => (AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        O_zd       := MEM(Index);
        Initial    := FALSE;
    end if;

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WDATA_WCLK_posedge,
          TimingData              => Tmkr_WDATA_WCLK_posedge,
          TestSignal              => WDATA_ipd,
          TestSignalName          => "WDATA",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WDATA_WCLK_noedge_posedge,
          SetupLow                => tsetup_WDATA_WCLK_noedge_posedge,
          HoldLow                 => thold_WDATA_WCLK_noedge_posedge,
          HoldHigh                => thold_WDATA_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM16X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM16X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_WCLK_posedge,
          TimingData              => Tmkr_AD0_WCLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD0_WCLK_noedge_posedge,
          HoldLow                 => thold_AD0_WCLK_noedge_posedge,
          HoldHigh                => thold_AD0_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM16X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_WCLK_posedge,
          TimingData              => Tmkr_AD1_WCLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD1_WCLK_noedge_posedge,
          HoldLow                 => thold_AD1_WCLK_noedge_posedge,
          HoldHigh                => thold_AD1_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM16X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_WCLK_posedge,
          TimingData              => Tmkr_AD2_WCLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD2_WCLK_noedge_posedge,
          HoldLow                 => thold_AD2_WCLK_noedge_posedge,
          HoldHigh                => thold_AD2_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM16X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_WCLK_posedge,
          TimingData              => Tmkr_AD3_WCLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD3_WCLK_noedge_posedge,
          HoldLow                 => thold_AD3_WCLK_noedge_posedge,
          HoldHigh                => thold_AD3_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM16X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAM16X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WDATA_WCLK_posedge  or Tviol_WE_WCLK_posedge or 
                 Tviol_AD0_WCLK_posedge or Tviol_AD1_WCLK_posedge or 
                 Tviol_AD2_WCLK_posedge or Tviol_AD3_WCLK_posedge or 
                 Pviol_WCLK;

    -------------------------
    --  Functionality Section
    -------------------------
    Index := ADDR4_TO_INT(ADDRESS => (AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
    WE_inverted := (NOT WE_ipd);
    O_zd := MEM(Index);

    VitalStateTable(Result => O_zd,
                    PreviousDataIn => PrevData,
                    StateTable => RAMS_RDATA_tab,
                    DataIn => (WCLK_prev, O_zd, WDATA_prev, WE_inverted, WCLK_ipd));
      
    O_zd := Violation XOR O_zd;

    --WE_prev       := WE_ipd;
    WE_prev       := WE_inverted;
    WCLK_prev     := WCLK_ipd;
    WDATA_prev    := WDATA_ipd;

    MEM(Index) <= O_zd;

    wait on AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, WDATA_ipd, WE_ipd, WCLK_ipd;

    end process VitalBehavior_Write;

    VITALBehavior_Read : process(AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, MEM, WDATA_ipd, WE_ipd)
         Variable Index      : integer  := 15 ;
         variable O_zd      : std_ulogic := 'X';
         variable O_zd1      : std_ulogic := 'X';
         variable O_GlitchData : VitalGlitchDataType;
    begin

        Index      := ADDR4_TO_INT(ADDRESS => (AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        O_zd       := MEM(Index);

	O_zd1 := VitalMUX2
		     (data0 => O_zd, 
		      data1 => WDATA_ipd,
		      dselect => WE_ipd);

    VitalPathDelay01 (
      OutSignal => RDATA,
      GlitchData => O_GlitchData,
      OutSignalName => "RDATA",
      OutTemp => O_zd1,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_RDATA, TRUE),
                1 => (AD0_ipd'last_event, tpd_AD0_RDATA, TRUE),
                2 => (AD1_ipd'last_event, tpd_AD1_RDATA, TRUE),
                3 => (AD2_ipd'last_event, tpd_AD2_RDATA, TRUE),
                4 => (AD3_ipd'last_event, tpd_AD3_RDATA, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

    end process VITALBehavior_Read;

end VITAL;

configuration CFG_RAM16X1S_VITAL of RAM16X1S is
   for VITAL
   end for;
end CFG_RAM16X1S_VITAL;


----- CELL RAM16X1S_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


library lava1;
use lava1.RAM_PACKAGE.all;


-- entity declaration --
entity RAM16X1S_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_AD0_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_RDATA                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WE_WCLK_noedge_negedge    :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_negedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WDATA_WCLK_noedge_negedge :	VitalDelayType   := 0.1 ns;
      thold_WDATA_WCLK_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_AD0_WCLK_noedge_negedge   :	VitalDelayType   := 0.1 ns;
      thold_AD0_WCLK_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_WCLK_noedge_negedge   :	VitalDelayType   := 0.1 ns;
      thold_AD1_WCLK_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_WCLK_noedge_negedge   :	VitalDelayType   := 0.1 ns;
      thold_AD2_WCLK_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_WCLK_noedge_negedge   :	VitalDelayType   := 0.1 ns;
      thold_AD3_WCLK_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tpw_WCLK_negedge                 :	VitalDelayType   := 2.0 ns;
      tipd_WE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WDATA                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT                             :	bit_vector := X"FFFF");

   port(
      WE                             :	in    STD_ULOGIC;
      WDATA                          :	in    STD_ULOGIC;
      WCLK                           :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      RDATA                          :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAM16X1S_1 : entity is TRUE;
end RAM16X1S_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAM16X1S_1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';

      signal WDATA_ipd    : std_ulogic := 'X';
      signal WE_ipd       : std_ulogic := 'X';
      signal WCLK_ipd     : std_ulogic := 'X';

      signal MEM          : std_logic_vector( 15 downto 0 ) := ( To_StdLogicVector(INIT)) ;

begin 

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin
        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);

        VitalWireDelay (WDATA_ipd,  WDATA, tipd_WDATA);
        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
      end block;

      --------------------
      -- RAM16X1S_1 Write Behavior
      --------------------
      VITALBehavior_Write : process
        -- Local variables used for timing checks

        variable Tviol_WDATA_WCLK_posedge  : std_ulogic  := '0';
        variable Tviol_WE_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_AD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_WCLK_posedge    : std_ulogic  := '0';

        variable Tmkr_WDATA_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        variable Initial          : boolean := TRUE;
        variable Violation        : std_ulogic := '0';
        variable INIT_BITS        : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT);
        variable Index            : integer := 16;
        variable PrevData         : std_logic_vector(0 to 4) := (others => '0');
        variable WE_prev          : std_ulogic := 'X';
        variable WCLK_prev        : std_ulogic := 'X';
        variable WDATA_prev       : std_ulogic := 'X';
        variable O_zd             : std_ulogic := 'X';
        variable WE_inverted      : std_ulogic := 'X';
        variable WCLK_inverted    : std_ulogic := 'X';
        variable O_GlitchData     : VitalGlitchDataType;

        begin


        if (Initial) then
        wait until ((WCLK_ipd = '0' or WCLK_ipd = '1') and
                    (AD3_ipd = '0' or AD3_ipd = '1') and
                    (AD2_ipd = '0' or AD2_ipd = '1') and
                    (AD1_ipd = '0' or AD1_ipd = '1') and
                    (AD0_ipd = '0' or AD0_ipd = '1'));
        WCLK_prev  := WCLK_ipd;
        WE_prev    := WE_ipd;
        WDATA_prev := WDATA_ipd;
        Index      := ADDR4_TO_INT(ADDRESS => (AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        O_zd       := MEM(Index);
        Initial    := FALSE;
    end if;

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WDATA_WCLK_posedge,
          TimingData              => Tmkr_WDATA_WCLK_posedge,
          TestSignal              => WDATA_ipd,
          TestSignalName          => "WDATA",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WDATA_WCLK_noedge_negedge,
          SetupLow                => tsetup_WDATA_WCLK_noedge_negedge,
          HoldLow                 => thold_WDATA_WCLK_noedge_negedge,
          HoldHigh                => thold_WDATA_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM16X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_negedge,
          SetupLow                => tsetup_WE_WCLK_noedge_negedge,
          HoldLow                 => thold_WE_WCLK_noedge_negedge,
          HoldHigh                => thold_WE_WCLK_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM16X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_WCLK_posedge,
          TimingData              => Tmkr_AD0_WCLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD0_WCLK_noedge_negedge,
          HoldLow                 => thold_AD0_WCLK_noedge_negedge,
          HoldHigh                => thold_AD0_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM16X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_WCLK_posedge,
          TimingData              => Tmkr_AD1_WCLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD1_WCLK_noedge_negedge,
          HoldLow                 => thold_AD1_WCLK_noedge_negedge,
          HoldHigh                => thold_AD1_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM16X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_WCLK_posedge,
          TimingData              => Tmkr_AD2_WCLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD2_WCLK_noedge_negedge,
          HoldLow                 => thold_AD2_WCLK_noedge_negedge,
          HoldHigh                => thold_AD2_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM16X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_WCLK_posedge,
          TimingData              => Tmkr_AD3_WCLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD3_WCLK_noedge_negedge,
          HoldLow                 => thold_AD3_WCLK_noedge_negedge,
          HoldHigh                => thold_AD3_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM16X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_negedge,
          PulseWidthLow           => tpw_WCLK_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAM16X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WDATA_WCLK_posedge  or Tviol_WE_WCLK_posedge or 
                 Tviol_AD0_WCLK_posedge or Tviol_AD1_WCLK_posedge or 
                 Tviol_AD2_WCLK_posedge or Tviol_AD3_WCLK_posedge or 
                 Pviol_WCLK;

    -------------------------
    --  Functionality Section
    -------------------------
    Index := ADDR4_TO_INT(ADDRESS => (AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
    WE_inverted := (NOT WE_ipd);
    WCLK_inverted := (NOT WCLK_ipd);
    O_zd := MEM(Index);

    VitalStateTable(Result => O_zd,
                    PreviousDataIn => PrevData,
                    StateTable => RAMS_RDATA_tab,
                    DataIn => (WCLK_prev, O_zd, WDATA_prev, WE_inverted, WCLK_inverted));
      
    O_zd := Violation XOR O_zd;

--    WE_prev       := WE_ipd;
    WE_prev       := WE_inverted;
--    WCLK_prev     := WCLK_ipd;
    WCLK_prev     := WCLK_inverted;
    WDATA_prev    := WDATA_ipd;

    MEM(Index) <= O_zd;

    wait on AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, WDATA_ipd, WE_ipd, WCLK_ipd;

    end process VitalBehavior_Write;

    VITALBehavior_Read : process(AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, MEM, WDATA_ipd, WE_ipd)
         Variable Index      : integer  := 15 ;
         variable O_zd       : std_ulogic := 'X';
         variable O_zd1      : std_ulogic := 'X';
         variable O_GlitchData : VitalGlitchDataType;
    begin

        Index      := ADDR4_TO_INT(ADDRESS => (AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        O_zd       := MEM(Index);

	O_zd1 := VitalMUX2
		     (data0 => O_zd, 
		      data1 => WDATA_ipd,
		      dselect => WE_ipd);

    VitalPathDelay01 (
      OutSignal => RDATA,
      GlitchData => O_GlitchData,
      OutSignalName => "RDATA",
      OutTemp => O_zd1,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_RDATA, TRUE),
                1 => (AD0_ipd'last_event, tpd_AD0_RDATA, TRUE),
                2 => (AD1_ipd'last_event, tpd_AD1_RDATA, TRUE),
                3 => (AD2_ipd'last_event, tpd_AD2_RDATA, TRUE),
                4 => (AD3_ipd'last_event, tpd_AD3_RDATA, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

    end process VITALBehavior_Read;

end VITAL;

configuration CFG_RAM16X1S_1_VITAL of RAM16X1S_1 is
   for VITAL
   end for;
end CFG_RAM16X1S_1_VITAL;


----- CELL RAM32X1D -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.VITAL_Timing.all; 
use IEEE.VITAL_Primitives.all;

library lava1;
use lava1.RAM_PACKAGE.all;

entity RAM32X1D is

  generic (
       TimingChecksOn: Boolean := TRUE;
       InstancePath:   STRING  := "*";
       Xon:  Boolean := True;
       MsgOn:  Boolean := False;

       tipd_AD0                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_AD1                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_AD2                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_AD3                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_AD4                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD0                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD1                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD2                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD3                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD4                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_WDATA                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_WE                           :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_WCLK                         :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tpd_AD0_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_AD1_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_AD2_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_AD3_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_AD4_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_WCLK_RDATA                    :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_DPAD0_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_DPAD1_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns); 
       tpd_DPAD2_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_DPAD3_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_DPAD4_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_WCLK_DPRDATA                  :      VitalDelayType01 := (0.0 ns, 0.0 ns); 
       tsetup_WDATA_WCLK_noedge_posedge  :      VitalDelayType := 0.1 ns;
       thold_WDATA_WCLK_noedge_posedge   :      VitalDelayType := 0.0 ns;
       tsetup_WE_WCLK_noedge_posedge     :      VitalDelayType := 0.1 ns;
       thold_WE_WCLK_noedge_posedge      :      VitalDelayType := 0.0 ns;
       tsetup_AD0_WCLK_noedge_posedge    :      VitalDelayType := 0.1 ns;
       thold_AD0_WCLK_noedge_posedge     :      VitalDelayType := 0.0 ns;
       tsetup_AD1_WCLK_noedge_posedge    :      VitalDelayType := 0.1 ns;
       thold_AD1_WCLK_noedge_posedge     :      VitalDelayType := 0.0 ns;
       tsetup_AD2_WCLK_noedge_posedge    :      VitalDelayType := 0.1 ns;
       thold_AD2_WCLK_noedge_posedge     :      VitalDelayType := 0.0 ns;
       tsetup_AD3_WCLK_noedge_posedge    :      VitalDelayType := 0.1 ns;
       thold_AD3_WCLK_noedge_posedge     :      VitalDelayType := 0.0 ns;
       tsetup_AD4_WCLK_noedge_posedge    :      VitalDelayType := 0.1 ns;
       thold_AD4_WCLK_noedge_posedge     :      VitalDelayType := 0.0 ns;
       tpw_WCLK_posedge                  :      VitalDelayType := 2.0 ns;
       tpw_WCLK_negedge                  :      VitalDelayType := 2.0 ns;

       INIT                              :      bit_vector := X"FFFFFFFF"
  );

  port (WDATA   : in std_ulogic;
        WE      : in std_ulogic;
        WCLK    : in std_ulogic;
        AD0     : in std_ulogic;
        AD1     : in std_ulogic;
        AD2     : in std_ulogic;
        AD3     : in std_ulogic;
        AD4     : in std_ulogic;
        DPAD0   : in std_ulogic;
        DPAD1   : in std_ulogic;
        DPAD2   : in std_ulogic;
        DPAD3   : in std_ulogic;
        DPAD4   : in std_ulogic;

        RDATA   : out std_ulogic;
        DPRDATA : out std_ulogic
       ); 
attribute VITAL_LEVEL0 of RAM32X1D : entity is TRUE;

end RAM32X1D;

-----------------------------------------------------------------------------

architecture VITAL of RAM32X1D is

  attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

  -- Local signals used to propagate input wire delay

    signal AD0_ipd    : std_ulogic := 'X';
    signal AD1_ipd    : std_ulogic := 'X';
    signal AD2_ipd    : std_ulogic := 'X';
    signal AD3_ipd    : std_ulogic := 'X';
    signal AD4_ipd    : std_ulogic := 'X';

    signal DPAD0_ipd  : std_ulogic := 'X';
    signal DPAD1_ipd  : std_ulogic := 'X';
    signal DPAD2_ipd  : std_ulogic := 'X';
    signal DPAD3_ipd  : std_ulogic := 'X';
    signal DPAD4_ipd  : std_ulogic := 'X';

    signal WDATA_ipd  : std_ulogic := 'X';
    signal WE_ipd     : std_ulogic := 'X';
    signal WCLK_ipd   : std_ulogic := 'X';
    signal MEM        : std_logic_vector( 31 downto 0 ) := To_StdLogicVector(INIT);
    signal WE_AD      : std_ulogic := 'X';
    signal AD         : std_ulogic_vector(4 downto 0);
    signal DPAD         : std_ulogic_vector(4 downto 0);
    signal WDATA_c    : std_ulogic := '0';

begin -- architecture

	AD <= AD4_ipd & AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd ;
	DPAD <= DPAD4_ipd & DPAD3_ipd & DPAD2_ipd & DPAD1_ipd & DPAD0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
  WireDelay : block
  begin
    VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
    VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
    VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
    VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
    VitalWireDelay (AD4_ipd, AD4, tipd_AD4);

    VitalWireDelay (DPAD0_ipd, DPAD0, tipd_DPAD0);
    VitalWireDelay (DPAD1_ipd, DPAD1, tipd_DPAD1);
    VitalWireDelay (DPAD2_ipd, DPAD2, tipd_DPAD2);
    VitalWireDelay (DPAD3_ipd, DPAD3, tipd_DPAD3);
    VitalWireDelay (DPAD4_ipd, DPAD4, tipd_DPAD4);

    VitalWireDelay (WDATA_ipd, WDATA, tipd_WDATA);
    VitalWireDelay (WE_ipd,    WE,    tipd_WE);
    VitalWireDelay (WCLK_ipd,  WCLK,  tipd_WCLK);
  end block;

process(WE_ipd,AD,DPAD)
begin
if (WE_ipd = '1' and AD = DPAD) then
	  WE_AD <= '1';
else
	  WE_AD <= '0';
end if;
end process;

process(WE_ipd, WCLK_ipd, WDATA_ipd)
begin
if (WCLK_ipd'event and WCLK_ipd='1') then
    if (WE_ipd = '1') then
	  WDATA_c <= WDATA_ipd;
    end if;
end if;
end process;

 VITALBehavior_Write : process

    -- Local variables used for functionality
    variable Index_A       : integer := 32;
    variable Index_B       : integer := 32;
    variable PrevData      : std_logic_vector(0 to 5) := (others => '0');
    variable WE_prev       : std_ulogic := 'X';
    variable WCLK_prev     : std_ulogic := 'X';
    variable WDATA_prev    : std_ulogic := 'X';
    variable Initial       : boolean := TRUE;

    -- Local variables used for timing checks
    variable Tviol_WDATA_WCLK_posedge  : std_ulogic := '0';
    variable Tviol_WE_WCLK_posedge     : std_ulogic := '0';
    variable Tviol_AD0_WCLK_posedge    : std_ulogic := '0';
    variable Tviol_AD1_WCLK_posedge    : std_ulogic := '0';
    variable Tviol_AD2_WCLK_posedge    : std_ulogic := '0';
    variable Tviol_AD3_WCLK_posedge    : std_ulogic := '0';
    variable Tviol_AD4_WCLK_posedge    : std_ulogic := '0';

    variable Tmkr_WDATA_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

    variable PViol_WCLK                : std_ulogic := '0';
    variable PInfo_WCLK                : VitalPeriodDataType := VitalPeriodDataInit;

    -- Local variables used for functionality
    variable OA_zd                     : std_ulogic := 'X';
    variable OB_zd                     : std_ulogic := 'X';
    variable WE_inverted               : std_ulogic := 'X';
    variable Violation                 : std_ulogic := '0';

  begin -- process

    if (Initial) then
        wait until ( (WCLK_ipd = '0' or WCLK_ipd = '1') and
                    (WE_ipd  = '0' or WE_ipd = '1') and
                    (AD4_ipd = '0' or AD4_ipd = '1') and
                    (AD3_ipd = '0' or AD3_ipd = '1') and
                    (AD2_ipd = '0' or AD2_ipd = '1') and
                    (AD1_ipd = '0' or AD1_ipd = '1') and
                    (AD0_ipd = '0' or AD0_ipd = '1') );
        WCLK_prev   := WCLK_ipd;
        WE_prev     := WE_ipd;
        WDATA_prev  := WDATA_ipd;
        Index_A     := ADDR5_TO_INT(ADDRESS => (AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        OA_zd       := MEM(Index_A);
        Initial     := FALSE;

    end if;
    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn ) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WDATA_WCLK_posedge,
          TimingData              => Tmkr_WDATA_WCLK_posedge,
          TestSignal              => WDATA_ipd,
          TestSignalName          => "WDATA",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WDATA_WCLK_noedge_posedge,
          SetupLow                => tsetup_WDATA_WCLK_noedge_posedge,
          HoldLow                 => thold_WDATA_WCLK_noedge_posedge,
          HoldHigh                => thold_WDATA_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM32X1D",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM32X1D",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_WCLK_posedge,
          TimingData              => Tmkr_AD0_WCLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD0_WCLK_noedge_posedge,
          HoldLow                 => thold_AD0_WCLK_noedge_posedge,
          HoldHigh                => thold_AD0_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM32X1D",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_WCLK_posedge,
          TimingData              => Tmkr_AD1_WCLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD1_WCLK_noedge_posedge,
          HoldLow                 => thold_AD1_WCLK_noedge_posedge,
          HoldHigh                => thold_AD1_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM32X1D",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_WCLK_posedge,
          TimingData              => Tmkr_AD2_WCLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD2_WCLK_noedge_posedge,
          HoldLow                 => thold_AD2_WCLK_noedge_posedge,
          HoldHigh                => thold_AD2_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM32X1D",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_WCLK_posedge,
          TimingData              => Tmkr_AD3_WCLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD3_WCLK_noedge_posedge,
          HoldLow                 => thold_AD3_WCLK_noedge_posedge,
          HoldHigh                => thold_AD3_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM32X1D",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_WCLK_posedge,
          TimingData              => Tmkr_AD3_WCLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD4_WCLK_noedge_posedge,
          HoldLow                 => thold_AD4_WCLK_noedge_posedge,
          HoldHigh                => thold_AD4_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM32X1D",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAM32X1D",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WDATA_WCLK_posedge or Tviol_WDATA_WCLK_posedge or 
                 Tviol_AD0_WCLK_posedge or Tviol_AD1_WCLK_posedge or 
                 Tviol_AD2_WCLK_posedge or Tviol_AD3_WCLK_posedge or 
                 Tviol_AD4_WCLK_posedge or 
                 Pviol_WCLK;

    -------------------------
    --  Functionality Section
    -------------------------
    Index_A := ADDR5_TO_INT(ADDRESS => (AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
    WE_inverted := (NOT WE_ipd);
    OA_zd   := MEM(Index_A);

    VitalStateTable(Result => OA_zd,
                    PreviousDataIn => PrevData,
                    StateTable => RAMS_RDATA_tab,
                    DataIn => (WCLK_prev, OA_zd, WDATA_prev, WE_inverted, WCLK_ipd));

    OA_zd := Violation XOR OA_zd;

--    WE_prev       :=   WE_ipd;
    WE_prev       :=   WE_inverted;
    WCLK_prev     :=   WCLK_ipd;
    WDATA_prev    :=   WDATA_ipd;

    MEM(Index_A) <= OA_zd;

    wait on AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, AD4_ipd, WDATA_ipd, WCLK_ipd, WE_ipd;

  end process VITALBehavior_Write;

  --------------------
  -- RAM32X1D Behavior
  --------------------
 VITALBehavior_Read : process(AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, AD4_ipd,
    DPAD0_ipd, DPAD1_ipd, DPAD2_ipd, DPAD3_ipd, DPAD4_ipd, MEM, WDATA_c, WE_ipd, WE_AD)

    Variable Index_A       :   integer  := 31 ;
    Variable Index_B       :   integer  := 31 ;
    Variable OA_zd         :   std_ulogic := 'X';
    Variable OA_zd1        :   std_ulogic := 'X';
    Variable OB_zd         :   std_ulogic := 'X';
    Variable OB_zd1        :   std_ulogic := 'X';
    Variable OA_GlitchData :   VitalGlitchDataType;
    Variable OB_GlitchData :   VitalGlitchDataType;

    begin -- process

    Index_A := ADDR5_TO_INT (ADDRESS => (AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
    Index_B := ADDR5_TO_INT (ADDRESS => (DPAD4_ipd, DPAD3_ipd, DPAD2_ipd, DPAD1_ipd, DPAD0_ipd));

    OA_zd   := MEM(Index_A);
    OB_zd   := MEM(Index_B);

    OA_zd1 := VitalMUX2
		     (data0 => OA_zd, 
		      data1 => WDATA_c,
		      dselect => WE_ipd);

    OB_zd1 := VitalMUX2
		     (data0 => OB_zd, 
		      data1 => OA_zd,
		      dselect => WE_AD);

    VitalPathDelay01 (
     OutSignal => RDATA,
     GlitchData => OA_GlitchData,
     OutSignalName => "RDATA",
     OutTemp => OA_zd1,
     Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_RDATA, TRUE),
               1 => (AD0_ipd'last_event, tpd_AD0_RDATA, TRUE),
               2 => (AD1_ipd'last_event, tpd_AD1_RDATA, TRUE),
               3 => (AD2_ipd'last_event, tpd_AD2_RDATA, TRUE),
               4 => (AD3_ipd'last_event, tpd_AD3_RDATA, TRUE),
               5 => (AD4_ipd'last_event, tpd_AD4_RDATA, TRUE)),
     Mode => OnEvent,
     Xon => Xon,
     MsgOn => MsgOn,
     MsgSeverity => WARNING);

     VitalPathDelay01 (
     OutSignal => DPRDATA,
     GlitchData => OB_GlitchData,
     OutSignalName => "DPRDATA",
     OutTemp => OB_zd1,
     Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_DPRDATA, TRUE),
               1 => (DPAD0_ipd'last_event, tpd_DPAD0_DPRDATA, TRUE),
               2 => (DPAD1_ipd'last_event, tpd_DPAD1_DPRDATA, TRUE),
               3 => (DPAD2_ipd'last_event, tpd_DPAD2_DPRDATA, TRUE),
               4 => (DPAD3_ipd'last_event, tpd_DPAD3_DPRDATA, TRUE),
               5 => (DPAD4_ipd'last_event, tpd_DPAD4_DPRDATA, TRUE)),
     Mode => OnEvent,
     Xon => Xon,
     MsgOn => MsgOn,
     MsgSeverity => WARNING);
 end process VITALBehavior_Read;

end VITAL;
 
configuration CFG_RAM32X1D_VITAL of RAM32X1D is
   for VITAL
   end for;
end CFG_RAM32X1D_VITAL;


----- CELL RAM32X1D_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.VITAL_Timing.all; 
use IEEE.VITAL_Primitives.all;

library lava1;
use lava1.RAM_PACKAGE.all;

entity RAM32X1D_1 is

  generic (
       TimingChecksOn: Boolean := TRUE;
       InstancePath:   STRING  := "*";
       Xon:  Boolean := True;
       MsgOn:  Boolean := False;

       tipd_AD0                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_AD1                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_AD2                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_AD3                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_AD4                          :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD0                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD1                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD2                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD3                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_DPAD4                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_WDATA                        :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_WE                           :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tipd_WCLK                         :      VitalDelayType01 := ( 0.0 ns,  0.0 ns);
       tpd_AD0_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_AD1_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_AD2_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_AD3_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_AD4_RDATA                     :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_WCLK_RDATA                    :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_DPAD0_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_DPAD1_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns); 
       tpd_DPAD2_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_DPAD3_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_DPAD4_DPRDATA                 :      VitalDelayType01 := (0.0 ns, 0.0 ns);
       tpd_WCLK_DPRDATA                  :      VitalDelayType01 := (0.0 ns, 0.0 ns); 
       tsetup_WDATA_WCLK_noedge_negedge  :      VitalDelayType := 0.1 ns;
       thold_WDATA_WCLK_noedge_negedge   :      VitalDelayType := 0.0 ns;
       tsetup_WE_WCLK_noedge_negedge     :      VitalDelayType := 0.1 ns;
       thold_WE_WCLK_noedge_negedge      :      VitalDelayType := 0.0 ns;
       tsetup_AD0_WCLK_noedge_negedge    :      VitalDelayType := 0.1 ns;
       thold_AD0_WCLK_noedge_negedge     :      VitalDelayType := 0.0 ns;
       tsetup_AD1_WCLK_noedge_negedge    :      VitalDelayType := 0.1 ns;
       thold_AD1_WCLK_noedge_negedge     :      VitalDelayType := 0.0 ns;
       tsetup_AD2_WCLK_noedge_negedge    :      VitalDelayType := 0.1 ns;
       thold_AD2_WCLK_noedge_negedge     :      VitalDelayType := 0.0 ns;
       tsetup_AD3_WCLK_noedge_negedge    :      VitalDelayType := 0.1 ns;
       thold_AD3_WCLK_noedge_negedge     :      VitalDelayType := 0.0 ns;
       tsetup_AD4_WCLK_noedge_negedge    :      VitalDelayType := 0.1 ns;
       thold_AD4_WCLK_noedge_negedge     :      VitalDelayType := 0.0 ns;
       tpw_WCLK_posedge                  :      VitalDelayType := 2.0 ns;
       tpw_WCLK_negedge                  :      VitalDelayType := 2.0 ns;

       INIT                              :      bit_vector := X"FFFFFFFF"
  );

  port (WDATA   : in std_ulogic;
        WE      : in std_ulogic;
        WCLK    : in std_ulogic;
        AD0     : in std_ulogic;
        AD1     : in std_ulogic;
        AD2     : in std_ulogic;
        AD3     : in std_ulogic;
        AD4     : in std_ulogic;
        DPAD0   : in std_ulogic;
        DPAD1   : in std_ulogic;
        DPAD2   : in std_ulogic;
        DPAD3   : in std_ulogic;
        DPAD4   : in std_ulogic;

        RDATA   : out std_ulogic;
        DPRDATA : out std_ulogic
       ); 
attribute VITAL_LEVEL0 of RAM32X1D_1 : entity is TRUE;

end RAM32X1D_1;

-----------------------------------------------------------------------------

architecture VITAL of RAM32X1D_1 is

  attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

  -- Local signals used to propagate input wire delay

    signal AD0_ipd    : std_ulogic := 'X';
    signal AD1_ipd    : std_ulogic := 'X';
    signal AD2_ipd    : std_ulogic := 'X';
    signal AD3_ipd    : std_ulogic := 'X';
    signal AD4_ipd    : std_ulogic := 'X';

    signal DPAD0_ipd  : std_ulogic := 'X';
    signal DPAD1_ipd  : std_ulogic := 'X';
    signal DPAD2_ipd  : std_ulogic := 'X';
    signal DPAD3_ipd  : std_ulogic := 'X';
    signal DPAD4_ipd  : std_ulogic := 'X';

    signal WDATA_ipd  : std_ulogic := 'X';
    signal WE_ipd     : std_ulogic := 'X';
    signal WCLK_ipd   : std_ulogic := 'X';
    signal MEM        : std_logic_vector( 31 downto 0 ) := To_StdLogicVector(INIT);
    signal WE_AD      : std_ulogic := 'X';
    signal AD         : std_ulogic_vector(4 downto 0);
    signal DPAD         : std_ulogic_vector(4 downto 0);
    signal WDATA_c    : std_ulogic := '0';

begin -- architecture

	AD <= AD4_ipd & AD3_ipd & AD2_ipd & AD1_ipd & AD0_ipd ;
	DPAD <= DPAD4_ipd & DPAD3_ipd & DPAD2_ipd & DPAD1_ipd & DPAD0_ipd ;

  ----------------------
  --  Wire Delay Section
  ----------------------
  WireDelay : block
  begin
    VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
    VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
    VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
    VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
    VitalWireDelay (AD4_ipd, AD4, tipd_AD4);

    VitalWireDelay (DPAD0_ipd, DPAD0, tipd_DPAD0);
    VitalWireDelay (DPAD1_ipd, DPAD1, tipd_DPAD1);
    VitalWireDelay (DPAD2_ipd, DPAD2, tipd_DPAD2);
    VitalWireDelay (DPAD3_ipd, DPAD3, tipd_DPAD3);
    VitalWireDelay (DPAD4_ipd, DPAD4, tipd_DPAD4);

    VitalWireDelay (WDATA_ipd, WDATA, tipd_WDATA);
    VitalWireDelay (WE_ipd,    WE,    tipd_WE);
    VitalWireDelay (WCLK_ipd,  WCLK,  tipd_WCLK);
  end block;

process(WE_ipd,AD,DPAD)
begin
if (WE_ipd = '1' and AD = DPAD) then
	  WE_AD <= '1';
else
	  WE_AD <= '0';
end if;
end process;

process(WE_ipd, WCLK_ipd, WDATA_ipd)
begin
if (WCLK_ipd'event and WCLK_ipd='1') then
    if (WE_ipd = '1') then
	  WDATA_c <= WDATA_ipd;
    end if;
end if;
end process;

 VITALBehavior_Write : process

    -- Local variables used for functionality
    variable Index_A       : integer := 32;
    variable Index_B       : integer := 32;
    variable PrevData      : std_logic_vector(0 to 5) := (others => '0');
    variable WE_prev       : std_ulogic := 'X';
    variable WCLK_prev     : std_ulogic := 'X';
    variable WDATA_prev    : std_ulogic := 'X';
    variable Initial       : boolean := TRUE;

    -- Local variables used for timing checks
    variable Tviol_WDATA_WCLK_posedge  : std_ulogic := '0';
    variable Tviol_WE_WCLK_posedge     : std_ulogic := '0';
    variable Tviol_AD0_WCLK_posedge    : std_ulogic := '0';
    variable Tviol_AD1_WCLK_posedge    : std_ulogic := '0';
    variable Tviol_AD2_WCLK_posedge    : std_ulogic := '0';
    variable Tviol_AD3_WCLK_posedge    : std_ulogic := '0';
    variable Tviol_AD4_WCLK_posedge    : std_ulogic := '0';

    variable Tmkr_WDATA_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_AD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

    variable PViol_WCLK                : std_ulogic := '0';
    variable PInfo_WCLK                : VitalPeriodDataType := VitalPeriodDataInit;

    -- Local variables used for functionality
    variable OA_zd                     : std_ulogic := 'X';
    variable OB_zd                     : std_ulogic := 'X';
    variable WE_inverted               : std_ulogic := 'X';
    variable WCLK_inverted             : std_ulogic := 'X';
    variable Violation                 : std_ulogic := '0';

  begin -- process

    if (Initial) then
        wait until ( (WCLK_ipd = '0' or WCLK_ipd = '1') and
                    (WE_ipd  = '0' or WE_ipd = '1') and
                    (AD4_ipd = '0' or AD4_ipd = '1') and
                    (AD3_ipd = '0' or AD3_ipd = '1') and
                    (AD2_ipd = '0' or AD2_ipd = '1') and
                    (AD1_ipd = '0' or AD1_ipd = '1') and
                    (AD0_ipd = '0' or AD0_ipd = '1') );
        WCLK_prev   := WCLK_ipd;
        WE_prev     := WE_ipd;
        WDATA_prev  := WDATA_ipd;
        Index_A     := ADDR5_TO_INT(ADDRESS => (AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        OA_zd       := MEM(Index_A);
        Initial     := FALSE;

    end if;
    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn ) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WDATA_WCLK_posedge,
          TimingData              => Tmkr_WDATA_WCLK_posedge,
          TestSignal              => WDATA_ipd,
          TestSignalName          => "WDATA",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WDATA_WCLK_noedge_negedge,
          SetupLow                => tsetup_WDATA_WCLK_noedge_negedge,
          HoldLow                 => thold_WDATA_WCLK_noedge_negedge,
          HoldHigh                => thold_WDATA_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM32X1D_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_negedge,
          SetupLow                => tsetup_WE_WCLK_noedge_negedge,
          HoldLow                 => thold_WE_WCLK_noedge_negedge,
          HoldHigh                => thold_WE_WCLK_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM32X1D_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_WCLK_posedge,
          TimingData              => Tmkr_AD0_WCLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD0_WCLK_noedge_negedge,
          HoldLow                 => thold_AD0_WCLK_noedge_negedge,
          HoldHigh                => thold_AD0_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM32X1D_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_WCLK_posedge,
          TimingData              => Tmkr_AD1_WCLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD1_WCLK_noedge_negedge,
          HoldLow                 => thold_AD1_WCLK_noedge_negedge,
          HoldHigh                => thold_AD1_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM32X1D_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_WCLK_posedge,
          TimingData              => Tmkr_AD2_WCLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD2_WCLK_noedge_negedge,
          HoldLow                 => thold_AD2_WCLK_noedge_negedge,
          HoldHigh                => thold_AD2_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM32X1D_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_WCLK_posedge,
          TimingData              => Tmkr_AD3_WCLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD3_WCLK_noedge_negedge,
          HoldLow                 => thold_AD3_WCLK_noedge_negedge,
          HoldHigh                => thold_AD3_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM32X1D_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_WCLK_posedge,
          TimingData              => Tmkr_AD3_WCLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD4_WCLK_noedge_negedge,
          HoldLow                 => thold_AD4_WCLK_noedge_negedge,
          HoldHigh                => thold_AD4_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM32X1D_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAM32X1D_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WDATA_WCLK_posedge or Tviol_WDATA_WCLK_posedge or 
                 Tviol_AD0_WCLK_posedge or Tviol_AD1_WCLK_posedge or 
                 Tviol_AD2_WCLK_posedge or Tviol_AD3_WCLK_posedge or 
                 Tviol_AD4_WCLK_posedge or 
                 Pviol_WCLK;

    -------------------------
    --  Functionality Section
    -------------------------
    Index_A := ADDR5_TO_INT(ADDRESS => (AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
    WE_inverted := (NOT WE_ipd);
    WCLK_inverted := (NOT WCLK_ipd);
    OA_zd   := MEM(Index_A);

    VitalStateTable(Result => OA_zd,
                    PreviousDataIn => PrevData,
                    StateTable => RAMS_RDATA_tab,
                    DataIn => (WCLK_prev, OA_zd, WDATA_prev, WE_inverted, WCLK_inverted));

    OA_zd := Violation XOR OA_zd;

--    WE_prev       :=   WE_ipd;
    WE_prev       :=   WE_inverted;
    WCLK_prev     :=   WCLK_inverted;
    WDATA_prev    :=   WDATA_ipd;

    MEM(Index_A) <= OA_zd;

    wait on AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, AD4_ipd, WDATA_ipd, WCLK_ipd, WE_ipd;

  end process VITALBehavior_Write;

  --------------------
  -- RAM32X1D_1 Behavior
  --------------------
 VITALBehavior_Read : process(AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, AD4_ipd,
    DPAD0_ipd, DPAD1_ipd, DPAD2_ipd, DPAD3_ipd, DPAD4_ipd, MEM, WDATA_c, WE_ipd, WE_AD)

    Variable Index_A       :   integer  := 31 ;
    Variable Index_B       :   integer  := 31 ;
    Variable OA_zd         :   std_ulogic := 'X';
    Variable OA_zd1        :   std_ulogic := 'X';
    Variable OB_zd         :   std_ulogic := 'X';
    Variable OB_zd1        :   std_ulogic := 'X';
    Variable OA_GlitchData :   VitalGlitchDataType;
    Variable OB_GlitchData :   VitalGlitchDataType;

    begin -- process

    Index_A := ADDR5_TO_INT (ADDRESS => (AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
    Index_B := ADDR5_TO_INT (ADDRESS => (DPAD4_ipd, DPAD3_ipd, DPAD2_ipd, DPAD1_ipd, DPAD0_ipd));

    OA_zd   := MEM(Index_A);
    OB_zd   := MEM(Index_B);

    OA_zd1 := VitalMUX2
		     (data0 => OA_zd, 
		      data1 => WDATA_c,
		      dselect => WE_ipd);

    OB_zd1 := VitalMUX2
		     (data0 => OB_zd, 
		      data1 => OA_zd,
		      dselect => WE_AD);

    VitalPathDelay01 (
     OutSignal => RDATA,
     GlitchData => OA_GlitchData,
     OutSignalName => "RDATA",
     OutTemp => OA_zd1,
     Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_RDATA, TRUE),
               1 => (AD0_ipd'last_event, tpd_AD0_RDATA, TRUE),
               2 => (AD1_ipd'last_event, tpd_AD1_RDATA, TRUE),
               3 => (AD2_ipd'last_event, tpd_AD2_RDATA, TRUE),
               4 => (AD3_ipd'last_event, tpd_AD3_RDATA, TRUE),
               5 => (AD4_ipd'last_event, tpd_AD4_RDATA, TRUE)),
     Mode => OnEvent,
     Xon => Xon,
     MsgOn => MsgOn,
     MsgSeverity => WARNING);

     VitalPathDelay01 (
     OutSignal => DPRDATA,
     GlitchData => OB_GlitchData,
     OutSignalName => "DPRDATA",
     OutTemp => OB_zd1,
     Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_DPRDATA, TRUE),
               1 => (DPAD0_ipd'last_event, tpd_DPAD0_DPRDATA, TRUE),
               2 => (DPAD1_ipd'last_event, tpd_DPAD1_DPRDATA, TRUE),
               3 => (DPAD2_ipd'last_event, tpd_DPAD2_DPRDATA, TRUE),
               4 => (DPAD3_ipd'last_event, tpd_DPAD3_DPRDATA, TRUE),
               5 => (DPAD4_ipd'last_event, tpd_DPAD4_DPRDATA, TRUE)),
     Mode => OnEvent,
     Xon => Xon,
     MsgOn => MsgOn,
     MsgSeverity => WARNING);
 end process VITALBehavior_Read;

end VITAL;
 
configuration CFG_RAM32X1D_1_VITAL of RAM32X1D_1 is
   for VITAL
   end for;
end CFG_RAM32X1D_1_VITAL;


----- CELL RAM32X1S -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lava1;
use lava1.RAM_PACKAGE.all;

-- entity declaration --
entity RAM32X1S is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_AD0_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_RDATA                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WE_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WDATA_WCLK_noedge_posedge :	VitalDelayType   := 0.1 ns;
      thold_WDATA_WCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_AD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tpw_WCLK_posedge                 :	VitalDelayType   := 2.0 ns;
      tipd_WE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WDATA                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT                             :	bit_vector := X"FFFFFFFF");

   port(
      WE                             :	in    STD_ULOGIC;
      WDATA                          :	in    STD_ULOGIC;
      WCLK                           :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      RDATA                          :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAM32X1S : entity is TRUE;
end RAM32X1S;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAM32X1S is
  attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';

      signal WDATA_ipd    : std_ulogic := 'X';
      signal WE_ipd       : std_ulogic := 'X';
      signal WCLK_ipd     : std_ulogic := 'X';

      signal MEM          : std_logic_vector( 31 downto 0 ) := ( To_StdLogicVector(INIT)) ;

begin 

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin
        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);

        VitalWireDelay (WDATA_ipd,  WDATA, tipd_WDATA);
        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
      end block;

      --------------------
      -- RAM32X1S Write Behavior
      --------------------
      VITALBehavior_Write : process
        -- Local variables used for timing checks

        variable Tviol_WDATA_WCLK_posedge  : std_ulogic  := '0';
        variable Tviol_WE_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_AD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_WCLK_posedge    : std_ulogic  := '0';

        variable Tmkr_WDATA_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        variable Initial          : boolean := TRUE;
        variable Violation        : std_ulogic := '0';
        variable INIT_BITS        : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT);
        variable Index            : integer := 32;
        variable PrevData         : std_logic_vector(0 to 4) := (others => '0');
        variable WE_prev          : std_ulogic := 'X';
        variable WCLK_prev        : std_ulogic := 'X';
        variable WDATA_prev       : std_ulogic := 'X';
        variable O_zd             : std_ulogic := 'X';
        variable O_GlitchData     : VitalGlitchDataType;
        variable WE_inverted      : std_ulogic := 'X';

        begin


        if (Initial) then
        wait until ((WCLK_ipd = '0' or WCLK_ipd = '1') and
                    (AD4_ipd = '0' or AD4_ipd = '1') and
                    (AD3_ipd = '0' or AD3_ipd = '1') and
                    (AD2_ipd = '0' or AD2_ipd = '1') and
                    (AD1_ipd = '0' or AD1_ipd = '1') and
                    (AD0_ipd = '0' or AD0_ipd = '1'));
        WCLK_prev  := WCLK_ipd;
        WE_prev    := WE_ipd;
        WDATA_prev := WDATA_ipd;
        Index      := ADDR5_TO_INT(ADDRESS => (AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        O_zd       := MEM(Index);
        Initial    := FALSE;
    end if;

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WDATA_WCLK_posedge,
          TimingData              => Tmkr_WDATA_WCLK_posedge,
          TestSignal              => WDATA_ipd,
          TestSignalName          => "WDATA",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WDATA_WCLK_noedge_posedge,
          SetupLow                => tsetup_WDATA_WCLK_noedge_posedge,
          HoldLow                 => thold_WDATA_WCLK_noedge_posedge,
          HoldHigh                => thold_WDATA_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM32X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM32X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_WCLK_posedge,
          TimingData              => Tmkr_AD0_WCLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD0_WCLK_noedge_posedge,
          HoldLow                 => thold_AD0_WCLK_noedge_posedge,
          HoldHigh                => thold_AD0_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM32X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_WCLK_posedge,
          TimingData              => Tmkr_AD1_WCLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD1_WCLK_noedge_posedge,
          HoldLow                 => thold_AD1_WCLK_noedge_posedge,
          HoldHigh                => thold_AD1_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM32X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_WCLK_posedge,
          TimingData              => Tmkr_AD2_WCLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD2_WCLK_noedge_posedge,
          HoldLow                 => thold_AD2_WCLK_noedge_posedge,
          HoldHigh                => thold_AD2_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM32X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_WCLK_posedge,
          TimingData              => Tmkr_AD3_WCLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD3_WCLK_noedge_posedge,
          HoldLow                 => thold_AD3_WCLK_noedge_posedge,
          HoldHigh                => thold_AD3_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM32X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_WCLK_posedge,
          TimingData              => Tmkr_AD4_WCLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD4_WCLK_noedge_posedge,
          HoldLow                 => thold_AD4_WCLK_noedge_posedge,
          HoldHigh                => thold_AD4_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM32X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAM32X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WDATA_WCLK_posedge  or Tviol_WE_WCLK_posedge or 
                 Tviol_AD0_WCLK_posedge or Tviol_AD1_WCLK_posedge or 
                 Tviol_AD2_WCLK_posedge or Tviol_AD3_WCLK_posedge or 
                 Tviol_AD4_WCLK_posedge or 
                 Pviol_WCLK;

    -------------------------
    --  Functionality Section
    -------------------------
    Index := ADDR5_TO_INT(ADDRESS => (AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
    WE_inverted := (NOT WE_ipd);
    O_zd := MEM(Index);

    VitalStateTable(Result => O_zd,
                    PreviousDataIn => PrevData,
                    StateTable => RAMS_RDATA_tab,
                    DataIn => (WCLK_prev, O_zd, WDATA_prev, WE_inverted, WCLK_ipd));
      
    O_zd := Violation XOR O_zd;

--    WE_prev       := WE_ipd;
    WE_prev       := WE_inverted;
    WCLK_prev     := WCLK_ipd;
    WDATA_prev    := WDATA_ipd;

    MEM(Index) <= O_zd;

    wait on AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, AD4_ipd, WDATA_ipd, WE_ipd, WCLK_ipd;

    end process VitalBehavior_Write;

    VITALBehavior_Read : process(AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, AD4_ipd, MEM, WDATA_ipd, WE_ipd)
         Variable Index        : integer  := 31 ;
         variable O_zd         : std_ulogic := 'X';
         variable O_zd1        : std_ulogic := 'X';
         variable O_GlitchData : VitalGlitchDataType;
    begin

        Index      := ADDR5_TO_INT(ADDRESS => (AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        O_zd       := MEM(Index);

	O_zd1 := VitalMUX2
		     (data0 => O_zd, 
		      data1 => WDATA_ipd,
		      dselect => WE_ipd);

    VitalPathDelay01 (
      OutSignal => RDATA,
      GlitchData => O_GlitchData,
      OutSignalName => "RDATA",
      OutTemp => O_zd1,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_RDATA, TRUE),
                1 => (AD0_ipd'last_event, tpd_AD0_RDATA, TRUE),
                2 => (AD1_ipd'last_event, tpd_AD1_RDATA, TRUE),
                3 => (AD2_ipd'last_event, tpd_AD2_RDATA, TRUE),
                4 => (AD3_ipd'last_event, tpd_AD3_RDATA, TRUE),
                5 => (AD4_ipd'last_event, tpd_AD4_RDATA, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

    end process VITALBehavior_Read;

end VITAL;

configuration CFG_RAM32X1S_VITAL of RAM32X1S is
   for VITAL
   end for;
end CFG_RAM32X1S_VITAL;

----- CELL RAM32X1S_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lava1;
use lava1.RAM_PACKAGE.all;

-- entity declaration --
entity RAM32X1S_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_AD0_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_RDATA                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WE_WCLK_noedge_negedge    :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_negedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WDATA_WCLK_noedge_negedge :	VitalDelayType   := 0.1 ns;
      thold_WDATA_WCLK_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_AD0_WCLK_noedge_negedge   :	VitalDelayType   := 0.1 ns;
      thold_AD0_WCLK_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_WCLK_noedge_negedge   :	VitalDelayType   := 0.1 ns;
      thold_AD1_WCLK_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_WCLK_noedge_negedge   :	VitalDelayType   := 0.1 ns;
      thold_AD2_WCLK_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_WCLK_noedge_negedge   :	VitalDelayType   := 0.1 ns;
      thold_AD3_WCLK_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_WCLK_noedge_negedge   :	VitalDelayType   := 0.1 ns;
      thold_AD4_WCLK_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tpw_WCLK_negedge                 :	VitalDelayType   := 2.0 ns;
      tipd_WE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WDATA                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT                             :	bit_vector := X"FFFFFFFF");

   port(
      WE                             :	in    STD_ULOGIC;
      WDATA                          :	in    STD_ULOGIC;
      WCLK                           :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      RDATA                          :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAM32X1S_1 : entity is TRUE;
end RAM32X1S_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAM32X1S_1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';

      signal WDATA_ipd    : std_ulogic := 'X';
      signal WE_ipd       : std_ulogic := 'X';
      signal WCLK_ipd     : std_ulogic := 'X';

      signal MEM          : std_logic_vector( 31 downto 0 ) := ( To_StdLogicVector(INIT)) ;

begin 

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin
        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);

        VitalWireDelay (WDATA_ipd,  WDATA, tipd_WDATA);
        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
      end block;

      --------------------
      -- RAM32X1S_1 Write Behavior
      --------------------
      VITALBehavior_Write : process
        -- Local variables used for timing checks

        variable Tviol_WDATA_WCLK_posedge  : std_ulogic  := '0';
        variable Tviol_WE_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_AD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_WCLK_posedge    : std_ulogic  := '0';

        variable Tmkr_WDATA_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        variable Initial          : boolean := TRUE;
        variable Violation        : std_ulogic := '0';
        variable INIT_BITS        : std_logic_vector(31 downto 0) := To_StdLogicVector(INIT);
        variable Index            : integer := 32;
        variable PrevData         : std_logic_vector(0 to 4) := (others => '0');
        variable WE_prev          : std_ulogic := 'X';
        variable WCLK_prev        : std_ulogic := 'X';
        variable WDATA_prev       : std_ulogic := 'X';
        variable O_zd             : std_ulogic := 'X';
        variable WE_inverted      : std_ulogic := 'X';
        variable WCLK_inverted    : std_ulogic := 'X';
        variable O_GlitchData     : VitalGlitchDataType;

        begin


        if (Initial) then
        wait until ((WCLK_ipd = '0' or WCLK_ipd = '1') and
                    (AD4_ipd = '0' or AD4_ipd = '1') and
                    (AD3_ipd = '0' or AD3_ipd = '1') and
                    (AD2_ipd = '0' or AD2_ipd = '1') and
                    (AD1_ipd = '0' or AD1_ipd = '1') and
                    (AD0_ipd = '0' or AD0_ipd = '1'));
        WCLK_prev  := WCLK_ipd;
        WE_prev    := WE_ipd;
        WDATA_prev := WDATA_ipd;
        Index      := ADDR5_TO_INT(ADDRESS => (AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        O_zd       := MEM(Index);
        Initial    := FALSE;
    end if;

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WDATA_WCLK_posedge,
          TimingData              => Tmkr_WDATA_WCLK_posedge,
          TestSignal              => WDATA_ipd,
          TestSignalName          => "WDATA",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WDATA_WCLK_noedge_negedge,
          SetupLow                => tsetup_WDATA_WCLK_noedge_negedge,
          HoldLow                 => thold_WDATA_WCLK_noedge_negedge,
          HoldHigh                => thold_WDATA_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM32X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_negedge,
          SetupLow                => tsetup_WE_WCLK_noedge_negedge,
          HoldLow                 => thold_WE_WCLK_noedge_negedge,
          HoldHigh                => thold_WE_WCLK_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM32X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_WCLK_posedge,
          TimingData              => Tmkr_AD0_WCLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD0_WCLK_noedge_negedge,
          HoldLow                 => thold_AD0_WCLK_noedge_negedge,
          HoldHigh                => thold_AD0_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM32X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_WCLK_posedge,
          TimingData              => Tmkr_AD1_WCLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD1_WCLK_noedge_negedge,
          HoldLow                 => thold_AD1_WCLK_noedge_negedge,
          HoldHigh                => thold_AD1_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM32X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_WCLK_posedge,
          TimingData              => Tmkr_AD2_WCLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD2_WCLK_noedge_negedge,
          HoldLow                 => thold_AD2_WCLK_noedge_negedge,
          HoldHigh                => thold_AD2_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM32X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_WCLK_posedge,
          TimingData              => Tmkr_AD3_WCLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD3_WCLK_noedge_negedge,
          HoldLow                 => thold_AD3_WCLK_noedge_negedge,
          HoldHigh                => thold_AD3_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM32X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_WCLK_posedge,
          TimingData              => Tmkr_AD4_WCLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD4_WCLK_noedge_negedge,
          HoldLow                 => thold_AD4_WCLK_noedge_negedge,
          HoldHigh                => thold_AD4_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM32X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_negedge,
          PulseWidthLow           => tpw_WCLK_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAM32X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WDATA_WCLK_posedge  or Tviol_WE_WCLK_posedge or 
                 Tviol_AD0_WCLK_posedge or Tviol_AD1_WCLK_posedge or 
                 Tviol_AD2_WCLK_posedge or Tviol_AD3_WCLK_posedge or 
                 Tviol_AD4_WCLK_posedge or 
                 Pviol_WCLK;

    -------------------------
    --  Functionality Section
    -------------------------
    Index := ADDR5_TO_INT(ADDRESS => (AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
    WE_inverted := (NOT WE_ipd);
    WCLK_inverted := (NOT WCLK_ipd);
    O_zd := MEM(Index);

    VitalStateTable(Result => O_zd,
                    PreviousDataIn => PrevData,
                    StateTable => RAMS_RDATA_tab,
                    DataIn => (WCLK_prev, O_zd, WDATA_prev, WE_inverted, WCLK_inverted));
      
    O_zd := Violation XOR O_zd;

--    WE_prev       := WE_ipd;
    WE_prev       := WE_inverted;
    WCLK_prev     := WCLK_inverted;
    WDATA_prev    := WDATA_ipd;

    MEM(Index) <= O_zd;

    wait on AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, AD4_ipd, WDATA_ipd, WE_ipd, WCLK_ipd;

    end process VitalBehavior_Write;

    VITALBehavior_Read : process(AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, AD4_ipd, MEM, WDATA_ipd,WE_ipd)
         Variable Index        : integer  := 31 ;
         variable O_zd         : std_ulogic := 'X';
         variable O_zd1        : std_ulogic := 'X';
         variable O_GlitchData : VitalGlitchDataType;
    begin

        Index      := ADDR5_TO_INT(ADDRESS => (AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        O_zd       := MEM(Index);
	O_zd1 := VitalMUX2
		     (data0 => O_zd, 
		      data1 => WDATA_ipd,
		      dselect => WE_ipd);

    VitalPathDelay01 (
      OutSignal => RDATA,
      GlitchData => O_GlitchData,
      OutSignalName => "RDATA",
      OutTemp => O_zd1,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_RDATA, TRUE),
                1 => (AD0_ipd'last_event, tpd_AD0_RDATA, TRUE),
                2 => (AD1_ipd'last_event, tpd_AD1_RDATA, TRUE),
                3 => (AD2_ipd'last_event, tpd_AD2_RDATA, TRUE),
                4 => (AD3_ipd'last_event, tpd_AD3_RDATA, TRUE),
                5 => (AD4_ipd'last_event, tpd_AD4_RDATA, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

    end process VITALBehavior_Read;

end VITAL;

configuration CFG_RAM32X1S_1_VITAL of RAM32X1S_1 is
   for VITAL
   end for;
end CFG_RAM32X1S_1_VITAL;


----- CELL RAM64X1S -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lava1;
use lava1.RAM_PACKAGE.all;

-- entity declaration --
entity RAM64X1S is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_AD0_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_RDATA                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WE_WCLK_noedge_posedge    :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WDATA_WCLK_noedge_posedge :	VitalDelayType   := 0.1 ns;
      thold_WDATA_WCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_AD0_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD0_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD1_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD2_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD3_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD4_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD5_WCLK_noedge_posedge   :	VitalDelayType   := 0.1 ns;
      thold_AD5_WCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tpw_WCLK_posedge                 :	VitalDelayType   := 2.0 ns;
      tipd_WE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WDATA                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT                             :	bit_vector := X"FFFFFFFFFFFFFFFF");

   port(
      WE                             :	in    STD_ULOGIC;
      WDATA                          :	in    STD_ULOGIC;
      WCLK                           :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      AD5                            :	in    STD_ULOGIC;
      RDATA                          :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAM64X1S : entity is TRUE;
end RAM64X1S;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAM64X1S is
  attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';
      signal AD5_ipd      : std_ulogic := 'X';

      signal WDATA_ipd    : std_ulogic := 'X';
      signal WE_ipd       : std_ulogic := 'X';
      signal WCLK_ipd     : std_ulogic := 'X';

      signal MEM          : std_logic_vector( 63 downto 0 ) := ( To_StdLogicVector(INIT)) ;

begin 

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin
        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);
        VitalWireDelay (AD5_ipd, AD5, tipd_AD5);

        VitalWireDelay (WDATA_ipd,  WDATA, tipd_WDATA);
        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
      end block;

      --------------------
      -- RAM64X1S Write Behavior
      --------------------
      VITALBehavior_Write : process
        -- Local variables used for timing checks

        variable Tviol_WDATA_WCLK_posedge  : std_ulogic  := '0';
        variable Tviol_WE_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_AD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD5_WCLK_posedge    : std_ulogic  := '0';

        variable Tmkr_WDATA_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        variable Initial          : boolean := TRUE;
        variable Violation        : std_ulogic := '0';
        variable INIT_BITS        : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT);
        variable Index            : integer := 64;
        variable PrevData         : std_logic_vector(0 to 4) := (others => '0');
        variable WE_prev          : std_ulogic := 'X';
        variable WCLK_prev        : std_ulogic := 'X';
        variable WDATA_prev       : std_ulogic := 'X';
        variable O_zd             : std_ulogic := 'X';
        variable O_GlitchData     : VitalGlitchDataType;
        variable WE_inverted      : std_ulogic := 'X';

        begin


        if (Initial) then
        wait until ((WCLK_ipd = '0' or WCLK_ipd = '1') and
                    (AD5_ipd = '0' or AD5_ipd = '1') and
                    (AD4_ipd = '0' or AD4_ipd = '1') and
                    (AD3_ipd = '0' or AD3_ipd = '1') and
                    (AD2_ipd = '0' or AD2_ipd = '1') and
                    (AD1_ipd = '0' or AD1_ipd = '1') and
                    (AD0_ipd = '0' or AD0_ipd = '1'));
        WCLK_prev  := WCLK_ipd;
        WE_prev    := WE_ipd;
        WDATA_prev := WDATA_ipd;
        Index      := ADDR6_TO_INT(ADDRESS => (AD5_ipd, AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        O_zd       := MEM(Index);
        Initial    := FALSE;
    end if;

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WDATA_WCLK_posedge,
          TimingData              => Tmkr_WDATA_WCLK_posedge,
          TestSignal              => WDATA_ipd,
          TestSignalName          => "WDATA",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WDATA_WCLK_noedge_posedge,
          SetupLow                => tsetup_WDATA_WCLK_noedge_posedge,
          HoldLow                 => thold_WDATA_WCLK_noedge_posedge,
          HoldHigh                => thold_WDATA_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM64X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_posedge,
          SetupLow                => tsetup_WE_WCLK_noedge_posedge,
          HoldLow                 => thold_WE_WCLK_noedge_posedge,
          HoldHigh                => thold_WE_WCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM64X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_WCLK_posedge,
          TimingData              => Tmkr_AD0_WCLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD0_WCLK_noedge_posedge,
          HoldLow                 => thold_AD0_WCLK_noedge_posedge,
          HoldHigh                => thold_AD0_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM64X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_WCLK_posedge,
          TimingData              => Tmkr_AD1_WCLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD1_WCLK_noedge_posedge,
          HoldLow                 => thold_AD1_WCLK_noedge_posedge,
          HoldHigh                => thold_AD1_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM64X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_WCLK_posedge,
          TimingData              => Tmkr_AD2_WCLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD2_WCLK_noedge_posedge,
          HoldLow                 => thold_AD2_WCLK_noedge_posedge,
          HoldHigh                => thold_AD2_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM64X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_WCLK_posedge,
          TimingData              => Tmkr_AD3_WCLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD3_WCLK_noedge_posedge,
          HoldLow                 => thold_AD3_WCLK_noedge_posedge,
          HoldHigh                => thold_AD3_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM64X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_WCLK_posedge,
          TimingData              => Tmkr_AD4_WCLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD4_WCLK_noedge_posedge,
          HoldLow                 => thold_AD4_WCLK_noedge_posedge,
          HoldHigh                => thold_AD4_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM64X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD5_WCLK_posedge,
          TimingData              => Tmkr_AD5_WCLK_posedge,
          TestSignal              => AD5_ipd,
          TestSignalName          => "AD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD5_WCLK_noedge_posedge,
          SetupLow                => tsetup_AD5_WCLK_noedge_posedge,
          HoldLow                 => thold_AD5_WCLK_noedge_posedge,
          HoldHigh                => thold_AD5_WCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAM64X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_posedge,
          PulseWidthLow           => tpw_WCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAM64X1S",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WDATA_WCLK_posedge  or Tviol_WE_WCLK_posedge or 
                 Tviol_AD0_WCLK_posedge or Tviol_AD1_WCLK_posedge or 
                 Tviol_AD2_WCLK_posedge or Tviol_AD3_WCLK_posedge or 
                 Tviol_AD4_WCLK_posedge or Tviol_AD5_WCLK_posedge or 
                 Pviol_WCLK;

    -------------------------
    --  Functionality Section
    -------------------------
    Index := ADDR6_TO_INT(ADDRESS => (AD5_ipd, AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
    WE_inverted := (NOT WE_ipd);
    O_zd := MEM(Index);

    VitalStateTable(Result => O_zd,
                    PreviousDataIn => PrevData,
                    StateTable => RAMS_RDATA_tab,
                    DataIn => (WCLK_prev, O_zd, WDATA_prev, WE_inverted, WCLK_ipd));
      
    O_zd := Violation XOR O_zd;

--    WE_prev       := WE_ipd;
    WE_prev       := WE_inverted;
    WCLK_prev     := WCLK_ipd;
    WDATA_prev    := WDATA_ipd;

    MEM(Index) <= O_zd;

    wait on AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, AD4_ipd, AD5_ipd, WDATA_ipd, WE_ipd, WCLK_ipd;

    end process VitalBehavior_Write;

    VITALBehavior_Read : process(AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, AD4_ipd, AD5_ipd, MEM, WDATA_ipd, WE_ipd)
         Variable Index        : integer  := 63 ;
         variable O_zd         : std_ulogic := 'X';
         variable O_zd1         : std_ulogic := 'X';
         variable O_GlitchData : VitalGlitchDataType;
    begin

        Index      := ADDR6_TO_INT(ADDRESS => (AD5_ipd, AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        O_zd       := MEM(Index);
	O_zd1 := VitalMUX2
		     (data0 => O_zd, 
		      data1 => WDATA_ipd,
		      dselect => WE_ipd);

    VitalPathDelay01 (
      OutSignal => RDATA,
      GlitchData => O_GlitchData,
      OutSignalName => "RDATA",
      OutTemp => O_zd1,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_RDATA, TRUE),
                1 => (AD0_ipd'last_event, tpd_AD0_RDATA, TRUE),
                2 => (AD1_ipd'last_event, tpd_AD1_RDATA, TRUE),
                3 => (AD2_ipd'last_event, tpd_AD2_RDATA, TRUE),
                4 => (AD3_ipd'last_event, tpd_AD3_RDATA, TRUE),
                5 => (AD4_ipd'last_event, tpd_AD4_RDATA, TRUE),
                6 => (AD5_ipd'last_event, tpd_AD5_RDATA, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

    end process VITALBehavior_Read;

end VITAL;

configuration CFG_RAM64X1S_VITAL of RAM64X1S is
   for VITAL
   end for;
end CFG_RAM64X1S_VITAL;


----- CELL RAM64X1S_1 -----

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lava1;
use lava1.RAM_PACKAGE.all;

-- entity declaration --
entity RAM64X1S_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_AD0_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD1_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD2_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD3_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD4_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_AD5_RDATA                    :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tpd_WCLK_RDATA                   :	VitalDelayType01 := (0.0 ns, 0.0 ns);
      tsetup_WE_WCLK_noedge_negedge    :	VitalDelayType   := 0.1 ns;
      thold_WE_WCLK_noedge_negedge     :	VitalDelayType   := 0.0 ns;
      tsetup_WDATA_WCLK_noedge_negedge :	VitalDelayType   := 0.1 ns;
      thold_WDATA_WCLK_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_AD0_WCLK_noedge_negedge   :	VitalDelayType   := 0.1 ns;
      thold_AD0_WCLK_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD1_WCLK_noedge_negedge   :	VitalDelayType   := 0.1 ns;
      thold_AD1_WCLK_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD2_WCLK_noedge_negedge   :	VitalDelayType   := 0.1 ns;
      thold_AD2_WCLK_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD3_WCLK_noedge_negedge   :	VitalDelayType   := 0.1 ns;
      thold_AD3_WCLK_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD4_WCLK_noedge_negedge   :	VitalDelayType   := 0.1 ns;
      thold_AD4_WCLK_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_AD5_WCLK_noedge_negedge   :	VitalDelayType   := 0.1 ns;
      thold_AD5_WCLK_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tpw_WCLK_negedge                 :	VitalDelayType   := 2.0 ns;
      tipd_WE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WDATA                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WCLK                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD2                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD3                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD4                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_AD5                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT                             :	bit_vector := X"FFFFFFFFFFFFFFFF");

   port(
      WE                             :	in    STD_ULOGIC;
      WDATA                          :	in    STD_ULOGIC;
      WCLK                           :	in    STD_ULOGIC;
      AD0                            :	in    STD_ULOGIC;
      AD1                            :	in    STD_ULOGIC;
      AD2                            :	in    STD_ULOGIC;
      AD3                            :	in    STD_ULOGIC;
      AD4                            :	in    STD_ULOGIC;
      AD5                            :	in    STD_ULOGIC;
      RDATA                          :	out   STD_ULOGIC);

attribute VITAL_LEVEL0 of RAM64X1S_1 : entity is TRUE;
end RAM64X1S_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAM64X1S_1 is
  attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

      signal AD0_ipd      : std_ulogic := 'X';
      signal AD1_ipd      : std_ulogic := 'X';
      signal AD2_ipd      : std_ulogic := 'X';
      signal AD3_ipd      : std_ulogic := 'X';
      signal AD4_ipd      : std_ulogic := 'X';
      signal AD5_ipd      : std_ulogic := 'X';

      signal WDATA_ipd    : std_ulogic := 'X';
      signal WE_ipd       : std_ulogic := 'X';
      signal WCLK_ipd     : std_ulogic := 'X';

      signal MEM          : std_logic_vector( 63 downto 0 ) := ( To_StdLogicVector(INIT)) ;

begin 

  ----------------------
  --  Wire Delay Section
  ----------------------
      WireDelay : block
      begin
        VitalWireDelay (AD0_ipd, AD0, tipd_AD0);
        VitalWireDelay (AD1_ipd, AD1, tipd_AD1);
        VitalWireDelay (AD2_ipd, AD2, tipd_AD2);
        VitalWireDelay (AD3_ipd, AD3, tipd_AD3);
        VitalWireDelay (AD4_ipd, AD4, tipd_AD4);
        VitalWireDelay (AD5_ipd, AD5, tipd_AD5);

        VitalWireDelay (WDATA_ipd,  WDATA, tipd_WDATA);
        VitalWireDelay (WE_ipd, WE, tipd_WE);
        VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
      end block;

      --------------------
      -- RAM64X1S_1 Write Behavior
      --------------------
      VITALBehavior_Write : process
        -- Local variables used for timing checks

        variable Tviol_WDATA_WCLK_posedge  : std_ulogic  := '0';
        variable Tviol_WE_WCLK_posedge     : std_ulogic  := '0';
        variable Tviol_AD0_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD1_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD2_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD3_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD4_WCLK_posedge    : std_ulogic  := '0';
        variable Tviol_AD5_WCLK_posedge    : std_ulogic  := '0';

        variable Tmkr_WDATA_WCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WE_WCLK_posedge      : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD0_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD1_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD2_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD3_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD4_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_AD5_WCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_WCLK       : std_ulogic := '0';
        variable PInfo_WCLK       : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        variable Initial          : boolean := TRUE;
        variable Violation        : std_ulogic := '0';
        variable INIT_BITS        : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT);
        variable Index            : integer := 64;
        variable PrevData         : std_logic_vector(0 to 4) := (others => '0');
        variable WE_prev          : std_ulogic := 'X';
        variable WCLK_prev        : std_ulogic := 'X';
        variable WDATA_prev       : std_ulogic := 'X';
        variable O_zd             : std_ulogic := 'X';
        variable WE_inverted      : std_ulogic := 'X';
        variable WCLK_inverted    : std_ulogic := 'X';
        variable O_GlitchData     : VitalGlitchDataType;

        begin


        if (Initial) then
        wait until ((WCLK_ipd = '0' or WCLK_ipd = '1') and
                    (AD5_ipd = '0' or AD5_ipd = '1') and
                    (AD4_ipd = '0' or AD4_ipd = '1') and
                    (AD3_ipd = '0' or AD3_ipd = '1') and
                    (AD2_ipd = '0' or AD2_ipd = '1') and
                    (AD1_ipd = '0' or AD1_ipd = '1') and
                    (AD0_ipd = '0' or AD0_ipd = '1'));
        WCLK_prev  := WCLK_ipd;
        WE_prev    := WE_ipd;
        WDATA_prev := WDATA_ipd;
        Index      := ADDR6_TO_INT(ADDRESS => (AD5_ipd, AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        O_zd       := MEM(Index);
        Initial    := FALSE;
    end if;

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WDATA_WCLK_posedge,
          TimingData              => Tmkr_WDATA_WCLK_posedge,
          TestSignal              => WDATA_ipd,
          TestSignalName          => "WDATA",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WDATA_WCLK_noedge_negedge,
          SetupLow                => tsetup_WDATA_WCLK_noedge_negedge,
          HoldLow                 => thold_WDATA_WCLK_noedge_negedge,
          HoldHigh                => thold_WDATA_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM64X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WE_WCLK_posedge,
          TimingData              => Tmkr_WE_WCLK_posedge,
          TestSignal              => WE_ipd,
          TestSignalName          => "WE",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WE_WCLK_noedge_negedge,
          SetupLow                => tsetup_WE_WCLK_noedge_negedge,
          HoldLow                 => thold_WE_WCLK_noedge_negedge,
          HoldHigh                => thold_WE_WCLK_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM64X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD0_WCLK_posedge,
          TimingData              => Tmkr_AD0_WCLK_posedge,
          TestSignal              => AD0_ipd,
          TestSignalName          => "AD0",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD0_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD0_WCLK_noedge_negedge,
          HoldLow                 => thold_AD0_WCLK_noedge_negedge,
          HoldHigh                => thold_AD0_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM64X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD1_WCLK_posedge,
          TimingData              => Tmkr_AD1_WCLK_posedge,
          TestSignal              => AD1_ipd,
          TestSignalName          => "AD1",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD1_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD1_WCLK_noedge_negedge,
          HoldLow                 => thold_AD1_WCLK_noedge_negedge,
          HoldHigh                => thold_AD1_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM64X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD2_WCLK_posedge,
          TimingData              => Tmkr_AD2_WCLK_posedge,
          TestSignal              => AD2_ipd,
          TestSignalName          => "AD2",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD2_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD2_WCLK_noedge_negedge,
          HoldLow                 => thold_AD2_WCLK_noedge_negedge,
          HoldHigh                => thold_AD2_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM64X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD3_WCLK_posedge,
          TimingData              => Tmkr_AD3_WCLK_posedge,
          TestSignal              => AD3_ipd,
          TestSignalName          => "AD3",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD3_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD3_WCLK_noedge_negedge,
          HoldLow                 => thold_AD3_WCLK_noedge_negedge,
          HoldHigh                => thold_AD3_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM64X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD4_WCLK_posedge,
          TimingData              => Tmkr_AD4_WCLK_posedge,
          TestSignal              => AD4_ipd,
          TestSignalName          => "AD4",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD4_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD4_WCLK_noedge_negedge,
          HoldLow                 => thold_AD4_WCLK_noedge_negedge,
          HoldHigh                => thold_AD4_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM64X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_AD5_WCLK_posedge,
          TimingData              => Tmkr_AD5_WCLK_posedge,
          TestSignal              => AD5_ipd,
          TestSignalName          => "AD5",
          TestDelay               => 0 ns,
          RefSignal               => WCLK_ipd,
          RefSignalName           => "WCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_AD5_WCLK_noedge_negedge,
          SetupLow                => tsetup_AD5_WCLK_noedge_negedge,
          HoldLow                 => thold_AD5_WCLK_noedge_negedge,
          HoldHigh                => thold_AD5_WCLK_noedge_negedge,
          CheckEnabled            => TO_X01(WE_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAM64X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_WCLK,
          PeriodData              => PInfo_WCLK,
          TestSignal              => WCLK_ipd,
          TestSignalName          => "WCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_WCLK_negedge,
          PulseWidthLow           => tpw_WCLK_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAM64X1S_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_WDATA_WCLK_posedge  or Tviol_WE_WCLK_posedge or 
                 Tviol_AD0_WCLK_posedge or Tviol_AD1_WCLK_posedge or 
                 Tviol_AD2_WCLK_posedge or Tviol_AD3_WCLK_posedge or 
                 Tviol_AD4_WCLK_posedge or Tviol_AD5_WCLK_posedge or 
                 Pviol_WCLK;

    -------------------------
    --  Functionality Section
    -------------------------
    Index := ADDR6_TO_INT(ADDRESS => (AD5_ipd, AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
    WE_inverted := (NOT WE_ipd);
    WCLK_inverted := (NOT WCLK_ipd);
    O_zd := MEM(Index);

    VitalStateTable(Result => O_zd,
                    PreviousDataIn => PrevData,
                    StateTable => RAMS_RDATA_tab,
                    DataIn => (WCLK_prev, O_zd, WDATA_prev, WE_inverted, WCLK_inverted));
      
    O_zd := Violation XOR O_zd;

--    WE_prev       := WE_ipd;
    WE_prev       := WE_inverted;
    WCLK_prev     := WCLK_inverted;
    WDATA_prev    := WDATA_ipd;

    MEM(Index) <= O_zd;

    wait on AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, AD4_ipd, AD5_ipd, WDATA_ipd, WE_ipd, WCLK_ipd;

    end process VitalBehavior_Write;

    VITALBehavior_Read : process(AD0_ipd, AD1_ipd, AD2_ipd, AD3_ipd, AD4_ipd, AD5_ipd, MEM, WDATA_ipd, WE_ipd)
         Variable Index        : integer  := 63 ;
         variable O_zd         : std_ulogic := 'X';
         variable O_zd1         : std_ulogic := 'X';
         variable O_GlitchData : VitalGlitchDataType;
    begin

        Index      := ADDR6_TO_INT(ADDRESS => (AD5_ipd, AD4_ipd, AD3_ipd, AD2_ipd, AD1_ipd, AD0_ipd));
        O_zd       := MEM(Index);
	O_zd1 := VitalMUX2
		     (data0 => O_zd, 
		      data1 => WDATA_ipd,
		      dselect => WE_ipd);

    VitalPathDelay01 (
      OutSignal => RDATA,
      GlitchData => O_GlitchData,
      OutSignalName => "RDATA",
      OutTemp => O_zd1,
      Paths => (0 => (WCLK_ipd'last_event, tpd_WCLK_RDATA, TRUE),
                1 => (AD0_ipd'last_event, tpd_AD0_RDATA, TRUE),
                2 => (AD1_ipd'last_event, tpd_AD1_RDATA, TRUE),
                3 => (AD2_ipd'last_event, tpd_AD2_RDATA, TRUE),
                4 => (AD3_ipd'last_event, tpd_AD3_RDATA, TRUE),
                5 => (AD4_ipd'last_event, tpd_AD4_RDATA, TRUE),
                6 => (AD5_ipd'last_event, tpd_AD5_RDATA, TRUE)),
      Mode => OnEvent,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

    end process VITALBehavior_Read;

end VITAL;

configuration CFG_RAM64X1S_1_VITAL of RAM64X1S_1 is
   for VITAL
   end for;
end CFG_RAM64X1S_1_VITAL;

----- CELL RAMB256X18DSR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18DSR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK0_DA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA8                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA9                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA10                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA11                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA12                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA13                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA14                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA15                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_EDA0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_EDA1                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB8                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB9                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB10                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB11                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB12                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB13                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB14                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB15                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_EDB0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_EDB1                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE0_RWCLK0_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CE1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE1_RWCLK1_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA8_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA8_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA9_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA9_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA10_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA10_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA11_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA11_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA12_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA12_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA13_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA13_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA14_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA14_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA15_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA15_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA1_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB8_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB8_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB9_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB9_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB10_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB10_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB11_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB11_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB12_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB12_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB13_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB13_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB14_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB14_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB15_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB15_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB1_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;


      tpw_RWCLK0_posedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
      CE0                            :	in    STD_ULOGIC;
      CE1                            :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      DA8                            :	inout STD_ULOGIC;
      DA9                            :	inout STD_ULOGIC;
      DA10                           :	inout STD_ULOGIC;
      DA11                           :	inout STD_ULOGIC;
      DA12                           :	inout STD_ULOGIC;
      DA13                           :	inout STD_ULOGIC;
      DA14                           :	inout STD_ULOGIC;
      DA15                           :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      EDA1                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      DB8                            :	inout STD_ULOGIC;
      DB9                            :	inout STD_ULOGIC;
      DB10                           :	inout STD_ULOGIC;
      DB11                           :	inout STD_ULOGIC;
      DB12                           :	inout STD_ULOGIC;
      DB13                           :	inout STD_ULOGIC;
      DB14                           :	inout STD_ULOGIC;
      DB15                           :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC;
      EDB1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18DSR : entity is TRUE;
end RAMB256X18DSR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18DSR is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
      SIGNAL CE0_ipd                 :   std_logic :='X';
      SIGNAL CE1_ipd                 :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL DA8_ipd                 :   std_logic :='X';
      SIGNAL DA9_ipd                 :   std_logic :='X';
      SIGNAL DA10_ipd                :   std_logic :='X';
      SIGNAL DA11_ipd                :   std_logic :='X';
      SIGNAL DA12_ipd                :   std_logic :='X';
      SIGNAL DA13_ipd                :   std_logic :='X';
      SIGNAL DA14_ipd                :   std_logic :='X';
      SIGNAL DA15_ipd                :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL EDA1_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL DB8_ipd                 :   std_logic :='X';
      SIGNAL DB9_ipd                 :   std_logic :='X';
      SIGNAL DB10_ipd                :   std_logic :='X';
      SIGNAL DB11_ipd                :   std_logic :='X';
      SIGNAL DB12_ipd                :   std_logic :='X';
      SIGNAL DB13_ipd                :   std_logic :='X';
      SIGNAL DB14_ipd                :   std_logic :='X';
      SIGNAL DB15_ipd                :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';
      SIGNAL EDB1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;
      SIGNAL data_out_b              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL rd_clk0                 :   std_logic  := 'X';
      SIGNAL rd_clk1                 :   std_logic  := 'X';

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);
      SIGNAL din_b                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
	VitalWireDelay (CE0_ipd,      CE0,        tipd_CE0);
	VitalWireDelay (CE1_ipd,      CE1,        tipd_CE1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (DA8_ipd,      DA8,        tipd_DA8);
	VitalWireDelay (DA9_ipd,      DA9,        tipd_DA9);
	VitalWireDelay (DA10_ipd,     DA10,       tipd_DA10);
	VitalWireDelay (DA11_ipd,     DA11,       tipd_DA11);
	VitalWireDelay (DA12_ipd,     DA12,       tipd_DA12);
	VitalWireDelay (DA13_ipd,     DA13,       tipd_DA13);
	VitalWireDelay (DA14_ipd,     DA14,       tipd_DA14);
	VitalWireDelay (DA15_ipd,     DA15,       tipd_DA15);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);
	VitalWireDelay (EDA1_ipd,     EDA1,       tipd_EDA1);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (DB8_ipd,      DB8,        tipd_DB8);
	VitalWireDelay (DB9_ipd,      DB9,        tipd_DB9);
	VitalWireDelay (DB10_ipd,     DB10,       tipd_DB10);
	VitalWireDelay (DB11_ipd,     DB11,       tipd_DB11);
	VitalWireDelay (DB12_ipd,     DB12,       tipd_DB12);
	VitalWireDelay (DB13_ipd,     DB13,       tipd_DB13);
	VitalWireDelay (DB14_ipd,     DB14,       tipd_DB14);
	VitalWireDelay (DB15_ipd,     DB15,       tipd_DB15);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
	VitalWireDelay (EDB1_ipd,     EDB1,       tipd_EDB1);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '1' and WEN0_ipd = '1') then
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '1' and WEN1_ipd = '1') then
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_8;
   end if;
   end process wrapper_read_add_b;


   wrapper_read_clk_a : 
   --process(OE0_ipd, RWCLK0_ipd, CE0_ipd, WEN0_ipd) --071804
   process (RWCLK0_ipd)   --071804
   begin
    if rising_edge(RWCLK0_ipd) then  --071804
       if (OE0_ipd = '1' and WEN0_ipd = '1' and CE0_ipd ='0') then
	    rd_clk0 <= RWCLK0_ipd;
       end if;
    else
	rd_clk0 <= '0';
    end if;
   end process;

   wrapper_read_clk_b : 
   --process(OE1_ipd, RWCLK1_ipd, CE1_ipd,WEN1_ipd) --071804
   process (RWCLK1_ipd)  --071804

   begin
    if rising_edge(RWCLK1_ipd) then --071804
       if (OE1_ipd = '1' and WEN1_ipd = '1' and CE1_ipd ='0') then
	    rd_clk1 <= RWCLK1_ipd;
       end if;
    else
	rd_clk1 <= '0';
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd, CE0_ipd)
   -- wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd) --071804
   wrapper_write_clk_a : process(RWCLK0_ipd) --071804

   begin
--    if (WEN0_ipd = '0' and CE0_ipd = '0' ) then
    if rising_edge (RWCLK0_ipd) then  --071804
      --if (WEN0_ipd = '0' and CE0_ipd = '0' ) then --ct112304
      if (WEN0_ipd = '0'  ) then --ct061605
	  wr_clk0 <= RWCLK0_ipd;
      end if;
    else
	wr_clk0 <= '0';
    end if;
   end process;

--   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd, CE1_ipd)
   -- wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd) --071804
   wrapper_write_clk_b : process( RWCLK1_ipd) --071804

   begin
--    if (WEN1_ipd = '0'and CE1_ipd = '0') then
    if rising_edge (RWCLK1_ipd) then--071804
      --if (WEN1_ipd = '0'and CE1_ipd = '0') then --ct112304
      if (WEN1_ipd = '0'  ) then --ct061605
	  wr_clk1 <= RWCLK1_ipd;
      end if;
    else
	wr_clk1 <= '0';
    end if;
   end process;

   write_address_a : process(
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DA15_ipd, 
                                  DA14_ipd, 
                                  DA13_ipd, 
                                  DA12_ipd, 
                                  DA11_ipd, 
                                  DA10_ipd, 
                                  DA9_ipd, 
                                  DA8_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(17) <= EDA1_ipd;
        din_a(16) <= EDA0_ipd;
        din_a(15) <= DA15_ipd;
        din_a(14) <= DA14_ipd;
        din_a(13) <= DA13_ipd;
        din_a(12) <= DA12_ipd;
        din_a(11) <= DA11_ipd;
        din_a(10) <= DA10_ipd;
        din_a(9)  <= DA9_ipd;
        din_a(8)  <= DA8_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DB15_ipd, 
                                  DB14_ipd, 
                                  DB13_ipd, 
                                  DB12_ipd, 
                                  DB11_ipd, 
                                  DB10_ipd, 
                                  DB9_ipd, 
                                  DB8_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(17) <= EDB1_ipd;
        din_b(16) <= EDB0_ipd;
        din_b(15) <= DB15_ipd;
        din_b(14) <= DB14_ipd;
        din_b(13) <= DB13_ipd;
        din_b(12) <= DB12_ipd;
        din_b(11) <= DB11_ipd;
        din_b(10) <= DB10_ipd;
        din_b(9)  <= DB9_ipd;
        din_b(8)  <= DB8_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18DSR Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            rd_clk0, rd_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tviol_CE0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_CE1_RWCLK1_posedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_posedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_posedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA8_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA9_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA10_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA11_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA12_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA13_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA14_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA15_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_EDA1_RWCLK0_posedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB8_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB9_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB10_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB11_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB12_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB13_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB14_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB15_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_EDB1_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CE1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA8_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA9_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA10_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA11_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA12_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA13_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA14_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA15_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA1_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB8_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB9_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB10_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB11_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB12_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB13_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB14_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB15_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_posedge,
          TimingData              => Tmkr_WEN0_RWCLK0_posedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_posedge,
          TimingData              => Tmkr_WEN1_RWCLK1_posedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE0_RWCLK0_posedge,
          TimingData              => Tmkr_CE0_RWCLK0_posedge,
          TestSignal              => CE0_ipd,
          TestSignalName          => "CE0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_CE0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_CE0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_CE0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE1_RWCLK1_posedge,
          TimingData              => Tmkr_CE1_RWCLK1_posedge,
          TestSignal              => CE1_ipd,
          TestSignalName          => "CE1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_CE1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_CE1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_CE1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_posedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_posedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_posedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_posedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_posedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_posedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_posedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_posedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_posedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_posedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_posedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_posedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_posedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_posedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_posedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_posedge,
          TimingData              => Tmkr_DA0_RWCLK0_posedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_posedge,
          TimingData              => Tmkr_DA1_RWCLK0_posedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_posedge,
          TimingData              => Tmkr_DA2_RWCLK0_posedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_posedge,
          TimingData              => Tmkr_DA3_RWCLK0_posedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_posedge,
          TimingData              => Tmkr_DA4_RWCLK0_posedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_posedge,
          TimingData              => Tmkr_DA5_RWCLK0_posedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_posedge,
          TimingData              => Tmkr_DA6_RWCLK0_posedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_posedge,
          TimingData              => Tmkr_DA7_RWCLK0_posedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA8_RWCLK0_posedge,
          TimingData              => Tmkr_DA8_RWCLK0_posedge,
          TestSignal              => DA8_ipd,
          TestSignalName          => "DA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA8_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA8_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA8_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA8_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA9_RWCLK0_posedge,
          TimingData              => Tmkr_DA9_RWCLK0_posedge,
          TestSignal              => DA9_ipd,
          TestSignalName          => "DA9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA9_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA9_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA9_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA9_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA10_RWCLK0_posedge,
          TimingData              => Tmkr_DA10_RWCLK0_posedge,
          TestSignal              => DA10_ipd,
          TestSignalName          => "DA10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA10_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA10_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA10_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA10_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA11_RWCLK0_posedge,
          TimingData              => Tmkr_DA11_RWCLK0_posedge,
          TestSignal              => DA11_ipd,
          TestSignalName          => "DA11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA11_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA11_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA11_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA11_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA12_RWCLK0_posedge,
          TimingData              => Tmkr_DA12_RWCLK0_posedge,
          TestSignal              => DA12_ipd,
          TestSignalName          => "DA12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA12_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA12_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA12_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA12_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA13_RWCLK0_posedge,
          TimingData              => Tmkr_DA13_RWCLK0_posedge,
          TestSignal              => DA13_ipd,
          TestSignalName          => "DA13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA13_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA13_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA13_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA13_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA14_RWCLK0_posedge,
          TimingData              => Tmkr_DA14_RWCLK0_posedge,
          TestSignal              => DA14_ipd,
          TestSignalName          => "DA14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA14_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA14_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA14_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA14_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA15_RWCLK0_posedge,
          TimingData              => Tmkr_DA15_RWCLK0_posedge,
          TestSignal              => DA15_ipd,
          TestSignalName          => "DA15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA15_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA15_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_posedge,
          TimingData              => Tmkr_EDA0_RWCLK0_posedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA1_RWCLK0_posedge,
          TimingData              => Tmkr_EDA1_RWCLK0_posedge,
          TestSignal              => EDA1_ipd,
          TestSignalName          => "EDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_EDA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_EDA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_EDA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_posedge,
          TimingData              => Tmkr_DB0_RWCLK1_posedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_posedge,
          TimingData              => Tmkr_DB1_RWCLK1_posedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_posedge,
          TimingData              => Tmkr_DB2_RWCLK1_posedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_posedge,
          TimingData              => Tmkr_DB3_RWCLK1_posedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_posedge,
          TimingData              => Tmkr_DB4_RWCLK1_posedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_posedge,
          TimingData              => Tmkr_DB5_RWCLK1_posedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_posedge,
          TimingData              => Tmkr_DB6_RWCLK1_posedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_posedge,
          TimingData              => Tmkr_DB7_RWCLK1_posedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB8_RWCLK1_posedge,
          TimingData              => Tmkr_DB8_RWCLK1_posedge,
          TestSignal              => DB8_ipd,
          TestSignalName          => "DB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB8_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB8_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB8_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB8_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB9_RWCLK1_posedge,
          TimingData              => Tmkr_DB9_RWCLK1_posedge,
          TestSignal              => DB9_ipd,
          TestSignalName          => "DB9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB9_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB9_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB9_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB9_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB10_RWCLK1_posedge,
          TimingData              => Tmkr_DB10_RWCLK1_posedge,
          TestSignal              => DB10_ipd,
          TestSignalName          => "DB10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB10_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB10_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB10_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB10_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB11_RWCLK1_posedge,
          TimingData              => Tmkr_DB11_RWCLK1_posedge,
          TestSignal              => DB11_ipd,
          TestSignalName          => "DB11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB11_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB11_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB11_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB11_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB12_RWCLK1_posedge,
          TimingData              => Tmkr_DB12_RWCLK1_posedge,
          TestSignal              => DB12_ipd,
          TestSignalName          => "DB12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB12_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB12_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB12_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB12_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB13_RWCLK1_posedge,
          TimingData              => Tmkr_DB13_RWCLK1_posedge,
          TestSignal              => DB13_ipd,
          TestSignalName          => "DB13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB13_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB13_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB13_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB13_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB14_RWCLK1_posedge,
          TimingData              => Tmkr_DB14_RWCLK1_posedge,
          TestSignal              => DB14_ipd,
          TestSignalName          => "DB14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB14_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB14_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB14_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB14_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB15_RWCLK1_posedge,
          TimingData              => Tmkr_DB15_RWCLK1_posedge,
          TestSignal              => DB15_ipd,
          TestSignalName          => "DB15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB15_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB15_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_posedge,
          TimingData              => Tmkr_EDB0_RWCLK1_posedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB1_RWCLK1_posedge,
          TimingData              => Tmkr_EDB1_RWCLK1_posedge,
          TestSignal              => EDB1_ipd,
          TestSignalName          => "EDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_EDB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_EDB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_EDB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_posedge,
          PulseWidthLow           => tpw_RWCLK0_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_posedge,
          PulseWidthLow           => tpw_RWCLK1_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk0'EVENT and rd_clk0 = '1' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '1' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '1' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( (rd_clk1'EVENT and rd_clk1 = '1') and not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10 : std_logic := 'Z';
    VARIABLE DATA_A11 : std_logic := 'Z';
    VARIABLE DATA_A12 : std_logic := 'Z';
    VARIABLE DATA_A13 : std_logic := 'Z';
    VARIABLE DATA_A14 : std_logic := 'Z';
    VARIABLE DATA_A15 : std_logic := 'Z';
    VARIABLE DATA_A16 : std_logic := 'Z';
    VARIABLE DATA_A17 : std_logic := 'Z';


    BEGIN

      con_a := VitalAND2(OE0_ipd, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10 := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11 := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12 := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13 := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14 := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15 := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16 := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17 := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA1, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA2, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA3, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA4, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA5, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA6, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA7, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA8, GLITCH_DATA_A8, "DA8", DATA_A8,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA8, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA9, GLITCH_DATA_A9, "DA9", DATA_A9,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA9, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA10, GLITCH_DATA_A10, "DA10", DATA_A10,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA10, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA11, GLITCH_DATA_A11, "DA11", DATA_A11,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA11, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA12, GLITCH_DATA_A12, "DA12", DATA_A12,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA12, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA13, GLITCH_DATA_A13, "DA13", DATA_A13,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA13, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA14, GLITCH_DATA_A14, "DA14", DATA_A14,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA14, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA15, GLITCH_DATA_A15, "DA15", DATA_A15,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA15, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A16, "EDA0", DATA_A16,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_EDA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA1, GLITCH_DATA_A17, "EDA1", DATA_A17,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_EDA1, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B17 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';
    VARIABLE DATA_B9  : std_logic := 'Z';
    VARIABLE DATA_B10 : std_logic := 'Z';
    VARIABLE DATA_B11 : std_logic := 'Z';
    VARIABLE DATA_B12 : std_logic := 'Z';
    VARIABLE DATA_B13 : std_logic := 'Z';
    VARIABLE DATA_B14 : std_logic := 'Z';
    VARIABLE DATA_B15 : std_logic := 'Z';
    VARIABLE DATA_B16 : std_logic := 'Z';
    VARIABLE DATA_B17 : std_logic := 'Z';


    BEGIN

      con_b := VitalAND2(OE1_ipd, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);
      DATA_B9  := VITALBUFIF1(data_out_b(9),con_b);
      DATA_B10 := VITALBUFIF1(data_out_b(10),con_b);
      DATA_B11 := VITALBUFIF1(data_out_b(11),con_b);
      DATA_B12 := VITALBUFIF1(data_out_b(12),con_b);
      DATA_B13 := VITALBUFIF1(data_out_b(13),con_b);
      DATA_B14 := VITALBUFIF1(data_out_b(14),con_b);
      DATA_B15 := VITALBUFIF1(data_out_b(15),con_b);
      DATA_B16 := VITALBUFIF1(data_out_b(16),con_b);
      DATA_B17 := VITALBUFIF1(data_out_b(17),con_b);


      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB1, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB2, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB3, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB4, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB5, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB6, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB7, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB8, GLITCH_DATA_B8, "DB8", DATA_B8,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB8, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB9, GLITCH_DATA_B9, "DB9", DATA_B9,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB9, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB10, GLITCH_DATA_B10, "DB10", DATA_B10,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB10, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB11, GLITCH_DATA_B11, "DB11", DATA_B11,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB11, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB12, GLITCH_DATA_B12, "DB12", DATA_B12,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB12, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB13, GLITCH_DATA_B13, "DB13", DATA_B13,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB13, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB14, GLITCH_DATA_B14, "DB14", DATA_B14,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB14, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB15, GLITCH_DATA_B15, "DB15", DATA_B15,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB15, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B16, "EDB0", DATA_B16,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_EDB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB1, GLITCH_DATA_B17, "EDB1", DATA_B17,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_EDB1, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB256X18DSR_VITAL of RAMB256X18DSR is
   for VITAL
   end for;
end CFG_RAMB256X18DSR_VITAL;

----- CELL RAMB256X18DSR_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18DSR_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK0_DA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA8                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA9                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA10                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA11                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA12                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA13                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA14                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA15                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_EDA0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_EDA1                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB8                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB9                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB10                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB11                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB12                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB13                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB14                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB15                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_EDB0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_EDB1                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE0_RWCLK0_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CE1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE1_RWCLK1_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA8_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA8_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA9_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA9_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA10_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA10_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA11_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA11_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA12_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA12_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA13_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA13_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA14_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA14_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA15_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA15_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA1_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB8_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB8_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB9_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB9_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB10_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB10_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB11_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB11_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB12_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB12_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB13_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB13_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB14_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB14_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB15_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB15_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB1_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;


      tpw_RWCLK0_posedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
      CE0                            :	in    STD_ULOGIC;
      CE1                            :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      DA8                            :	inout STD_ULOGIC;
      DA9                            :	inout STD_ULOGIC;
      DA10                           :	inout STD_ULOGIC;
      DA11                           :	inout STD_ULOGIC;
      DA12                           :	inout STD_ULOGIC;
      DA13                           :	inout STD_ULOGIC;
      DA14                           :	inout STD_ULOGIC;
      DA15                           :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      EDA1                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      DB8                            :	inout STD_ULOGIC;
      DB9                            :	inout STD_ULOGIC;
      DB10                           :	inout STD_ULOGIC;
      DB11                           :	inout STD_ULOGIC;
      DB12                           :	inout STD_ULOGIC;
      DB13                           :	inout STD_ULOGIC;
      DB14                           :	inout STD_ULOGIC;
      DB15                           :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC;
      EDB1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18DSR_1 : entity is TRUE;
end RAMB256X18DSR_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18DSR_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
      SIGNAL CE0_ipd                 :   std_logic :='X';
      SIGNAL CE1_ipd                 :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL DA8_ipd                 :   std_logic :='X';
      SIGNAL DA9_ipd                 :   std_logic :='X';
      SIGNAL DA10_ipd                :   std_logic :='X';
      SIGNAL DA11_ipd                :   std_logic :='X';
      SIGNAL DA12_ipd                :   std_logic :='X';
      SIGNAL DA13_ipd                :   std_logic :='X';
      SIGNAL DA14_ipd                :   std_logic :='X';
      SIGNAL DA15_ipd                :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL EDA1_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL DB8_ipd                 :   std_logic :='X';
      SIGNAL DB9_ipd                 :   std_logic :='X';
      SIGNAL DB10_ipd                :   std_logic :='X';
      SIGNAL DB11_ipd                :   std_logic :='X';
      SIGNAL DB12_ipd                :   std_logic :='X';
      SIGNAL DB13_ipd                :   std_logic :='X';
      SIGNAL DB14_ipd                :   std_logic :='X';
      SIGNAL DB15_ipd                :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';
      SIGNAL EDB1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;
      SIGNAL data_out_b              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL rd_clk0                 :   std_logic  := 'X';
      SIGNAL rd_clk1                 :   std_logic  := 'X';

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);
      SIGNAL din_b                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
	VitalWireDelay (CE0_ipd,      CE0,        tipd_CE0);
	VitalWireDelay (CE1_ipd,      CE1,        tipd_CE1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (DA8_ipd,      DA8,        tipd_DA8);
	VitalWireDelay (DA9_ipd,      DA9,        tipd_DA9);
	VitalWireDelay (DA10_ipd,     DA10,       tipd_DA10);
	VitalWireDelay (DA11_ipd,     DA11,       tipd_DA11);
	VitalWireDelay (DA12_ipd,     DA12,       tipd_DA12);
	VitalWireDelay (DA13_ipd,     DA13,       tipd_DA13);
	VitalWireDelay (DA14_ipd,     DA14,       tipd_DA14);
	VitalWireDelay (DA15_ipd,     DA15,       tipd_DA15);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);
	VitalWireDelay (EDA1_ipd,     EDA1,       tipd_EDA1);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (DB8_ipd,      DB8,        tipd_DB8);
	VitalWireDelay (DB9_ipd,      DB9,        tipd_DB9);
	VitalWireDelay (DB10_ipd,     DB10,       tipd_DB10);
	VitalWireDelay (DB11_ipd,     DB11,       tipd_DB11);
	VitalWireDelay (DB12_ipd,     DB12,       tipd_DB12);
	VitalWireDelay (DB13_ipd,     DB13,       tipd_DB13);
	VitalWireDelay (DB14_ipd,     DB14,       tipd_DB14);
	VitalWireDelay (DB15_ipd,     DB15,       tipd_DB15);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
	VitalWireDelay (EDB1_ipd,     EDB1,       tipd_EDB1);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '0' and WEN0_ipd = '1') then
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '0' and WEN1_ipd = '1') then
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_8;
   end if;
   end process wrapper_read_add_b;


   wrapper_read_clk_a : process(OE0_ipd, RWCLK0_ipd, CE0_ipd, WEN0_ipd)

   begin
    if (OE0_ipd = '0' and WEN0_ipd = '1' and CE0_ipd ='0') then
	rd_clk0 <= RWCLK0_ipd;
    else
	rd_clk0 <= '0';
    end if;
   end process;

   wrapper_read_clk_b : process(OE1_ipd, RWCLK1_ipd, CE1_ipd,WEN1_ipd)

   begin
    if (OE1_ipd = '0' and WEN1_ipd = '1' and CE1_ipd ='0') then
	rd_clk1 <= RWCLK1_ipd;
    else
	rd_clk1 <= '0';
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd, CE0_ipd)
   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd)

   begin
--    if (WEN0_ipd = '0' and CE0_ipd = '0' ) then
    if (WEN0_ipd = '0') then
	wr_clk0 <= RWCLK0_ipd;
    else
	wr_clk0 <= '0';
    end if;
   end process;

--   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd, CE1_ipd)
   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd)

   begin
--    if (WEN1_ipd = '0'and CE1_ipd = '0') then
    if (WEN1_ipd = '0') then
	wr_clk1 <= RWCLK1_ipd;
    else
	wr_clk1 <= '0';
    end if;
   end process;

   write_address_a : process(
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DA15_ipd, 
                                  DA14_ipd, 
                                  DA13_ipd, 
                                  DA12_ipd, 
                                  DA11_ipd, 
                                  DA10_ipd, 
                                  DA9_ipd, 
                                  DA8_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(17) <= EDA1_ipd;
        din_a(16) <= EDA0_ipd;
        din_a(15) <= DA15_ipd;
        din_a(14) <= DA14_ipd;
        din_a(13) <= DA13_ipd;
        din_a(12) <= DA12_ipd;
        din_a(11) <= DA11_ipd;
        din_a(10) <= DA10_ipd;
        din_a(9)  <= DA9_ipd;
        din_a(8)  <= DA8_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DB15_ipd, 
                                  DB14_ipd, 
                                  DB13_ipd, 
                                  DB12_ipd, 
                                  DB11_ipd, 
                                  DB10_ipd, 
                                  DB9_ipd, 
                                  DB8_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(17) <= EDB1_ipd;
        din_b(16) <= EDB0_ipd;
        din_b(15) <= DB15_ipd;
        din_b(14) <= DB14_ipd;
        din_b(13) <= DB13_ipd;
        din_b(12) <= DB12_ipd;
        din_b(11) <= DB11_ipd;
        din_b(10) <= DB10_ipd;
        din_b(9)  <= DB9_ipd;
        din_b(8)  <= DB8_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18DSR_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            rd_clk0, rd_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tviol_CE0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_CE1_RWCLK1_posedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_posedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_posedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA8_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA9_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA10_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA11_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA12_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA13_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA14_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA15_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_EDA1_RWCLK0_posedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB8_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB9_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB10_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB11_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB12_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB13_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB14_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB15_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_EDB1_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CE1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA8_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA9_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA10_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA11_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA12_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA13_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA14_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA15_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA1_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB8_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB9_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB10_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB11_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB12_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB13_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB14_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB15_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_posedge,
          TimingData              => Tmkr_WEN0_RWCLK0_posedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_posedge,
          TimingData              => Tmkr_WEN1_RWCLK1_posedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE0_RWCLK0_posedge,
          TimingData              => Tmkr_CE0_RWCLK0_posedge,
          TestSignal              => CE0_ipd,
          TestSignalName          => "CE0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_CE0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_CE0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_CE0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE1_RWCLK1_posedge,
          TimingData              => Tmkr_CE1_RWCLK1_posedge,
          TestSignal              => CE1_ipd,
          TestSignalName          => "CE1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_CE1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_CE1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_CE1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_posedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_posedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_posedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_posedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_posedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_posedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_posedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_posedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_posedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_posedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_posedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_posedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_posedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_posedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_posedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_posedge,
          TimingData              => Tmkr_DA0_RWCLK0_posedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_posedge,
          TimingData              => Tmkr_DA1_RWCLK0_posedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_posedge,
          TimingData              => Tmkr_DA2_RWCLK0_posedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_posedge,
          TimingData              => Tmkr_DA3_RWCLK0_posedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_posedge,
          TimingData              => Tmkr_DA4_RWCLK0_posedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_posedge,
          TimingData              => Tmkr_DA5_RWCLK0_posedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_posedge,
          TimingData              => Tmkr_DA6_RWCLK0_posedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_posedge,
          TimingData              => Tmkr_DA7_RWCLK0_posedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA8_RWCLK0_posedge,
          TimingData              => Tmkr_DA8_RWCLK0_posedge,
          TestSignal              => DA8_ipd,
          TestSignalName          => "DA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA8_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA8_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA8_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA8_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA9_RWCLK0_posedge,
          TimingData              => Tmkr_DA9_RWCLK0_posedge,
          TestSignal              => DA9_ipd,
          TestSignalName          => "DA9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA9_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA9_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA9_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA9_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA10_RWCLK0_posedge,
          TimingData              => Tmkr_DA10_RWCLK0_posedge,
          TestSignal              => DA10_ipd,
          TestSignalName          => "DA10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA10_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA10_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA10_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA10_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA11_RWCLK0_posedge,
          TimingData              => Tmkr_DA11_RWCLK0_posedge,
          TestSignal              => DA11_ipd,
          TestSignalName          => "DA11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA11_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA11_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA11_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA11_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA12_RWCLK0_posedge,
          TimingData              => Tmkr_DA12_RWCLK0_posedge,
          TestSignal              => DA12_ipd,
          TestSignalName          => "DA12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA12_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA12_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA12_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA12_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA13_RWCLK0_posedge,
          TimingData              => Tmkr_DA13_RWCLK0_posedge,
          TestSignal              => DA13_ipd,
          TestSignalName          => "DA13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA13_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA13_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA13_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA13_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA13_RWCLK0_posedge,
          TimingData              => Tmkr_DA13_RWCLK0_posedge,
          TestSignal              => DA13_ipd,
          TestSignalName          => "DA13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA13_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA13_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA13_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA13_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA14_RWCLK0_posedge,
          TimingData              => Tmkr_DA14_RWCLK0_posedge,
          TestSignal              => DA14_ipd,
          TestSignalName          => "DA14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA14_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA14_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA14_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA14_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA15_RWCLK0_posedge,
          TimingData              => Tmkr_DA15_RWCLK0_posedge,
          TestSignal              => DA15_ipd,
          TestSignalName          => "DA15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA15_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA15_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_posedge,
          TimingData              => Tmkr_EDA0_RWCLK0_posedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA1_RWCLK0_posedge,
          TimingData              => Tmkr_EDA1_RWCLK0_posedge,
          TestSignal              => EDA1_ipd,
          TestSignalName          => "EDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_EDA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_EDA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_EDA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_posedge,
          TimingData              => Tmkr_DB0_RWCLK1_posedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_posedge,
          TimingData              => Tmkr_DB1_RWCLK1_posedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_posedge,
          TimingData              => Tmkr_DB2_RWCLK1_posedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_posedge,
          TimingData              => Tmkr_DB3_RWCLK1_posedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_posedge,
          TimingData              => Tmkr_DB4_RWCLK1_posedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_posedge,
          TimingData              => Tmkr_DB5_RWCLK1_posedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_posedge,
          TimingData              => Tmkr_DB6_RWCLK1_posedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_posedge,
          TimingData              => Tmkr_DB7_RWCLK1_posedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB8_RWCLK1_posedge,
          TimingData              => Tmkr_DB8_RWCLK1_posedge,
          TestSignal              => DB8_ipd,
          TestSignalName          => "DB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB8_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB8_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB8_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB8_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB9_RWCLK1_posedge,
          TimingData              => Tmkr_DB9_RWCLK1_posedge,
          TestSignal              => DB9_ipd,
          TestSignalName          => "DB9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB9_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB9_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB9_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB9_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB10_RWCLK1_posedge,
          TimingData              => Tmkr_DB10_RWCLK1_posedge,
          TestSignal              => DB10_ipd,
          TestSignalName          => "DB10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB10_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB10_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB10_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB10_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB11_RWCLK1_posedge,
          TimingData              => Tmkr_DB11_RWCLK1_posedge,
          TestSignal              => DB11_ipd,
          TestSignalName          => "DB11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB11_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB11_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB11_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB11_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB12_RWCLK1_posedge,
          TimingData              => Tmkr_DB12_RWCLK1_posedge,
          TestSignal              => DB12_ipd,
          TestSignalName          => "DB12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB12_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB12_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB12_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB12_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB13_RWCLK1_posedge,
          TimingData              => Tmkr_DB13_RWCLK1_posedge,
          TestSignal              => DB13_ipd,
          TestSignalName          => "DB13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB13_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB13_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB13_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB13_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB14_RWCLK1_posedge,
          TimingData              => Tmkr_DB14_RWCLK1_posedge,
          TestSignal              => DB14_ipd,
          TestSignalName          => "DB14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB14_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB14_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB14_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB14_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB15_RWCLK1_posedge,
          TimingData              => Tmkr_DB15_RWCLK1_posedge,
          TestSignal              => DB15_ipd,
          TestSignalName          => "DB15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB15_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB15_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_posedge,
          TimingData              => Tmkr_EDB0_RWCLK1_posedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB1_RWCLK1_posedge,
          TimingData              => Tmkr_EDB1_RWCLK1_posedge,
          TestSignal              => EDB1_ipd,
          TestSignalName          => "EDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_EDB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_EDB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_EDB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_posedge,
          PulseWidthLow           => tpw_RWCLK0_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_posedge,
          PulseWidthLow           => tpw_RWCLK1_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk0'EVENT and rd_clk0 = '1' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '1' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '1' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( (rd_clk1'EVENT and rd_clk1 = '1') and not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10 : std_logic := 'Z';
    VARIABLE DATA_A11 : std_logic := 'Z';
    VARIABLE DATA_A12 : std_logic := 'Z';
    VARIABLE DATA_A13 : std_logic := 'Z';
    VARIABLE DATA_A14 : std_logic := 'Z';
    VARIABLE DATA_A15 : std_logic := 'Z';
    VARIABLE DATA_A16 : std_logic := 'Z';
    VARIABLE DATA_A17 : std_logic := 'Z';
    VARIABLE OE0_inverted : std_logic := 'Z';


    BEGIN

      OE0_inverted := NOT (OE0_ipd);
      con_a := VitalAND2(OE0_inverted, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10 := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11 := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12 := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13 := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14 := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15 := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16 := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17 := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA1, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA2, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA3, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA4, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA5, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA6, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA7, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA8, GLITCH_DATA_A8, "DA8", DATA_A8,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA8, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA9, GLITCH_DATA_A9, "DA9", DATA_A9,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA9, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA10, GLITCH_DATA_A10, "DA10", DATA_A10,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA10, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA11, GLITCH_DATA_A11, "DA11", DATA_A11,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA11, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA12, GLITCH_DATA_A12, "DA12", DATA_A12,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA12, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA13, GLITCH_DATA_A13, "DA13", DATA_A13,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA13, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA14, GLITCH_DATA_A14, "DA14", DATA_A14,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA14, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA15, GLITCH_DATA_A15, "DA15", DATA_A15,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA15, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A16, "EDA0", DATA_A16,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_EDA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA1, GLITCH_DATA_A17, "EDA1", DATA_A17,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_EDA1, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B17 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';
    VARIABLE DATA_B9  : std_logic := 'Z';
    VARIABLE DATA_B10 : std_logic := 'Z';
    VARIABLE DATA_B11 : std_logic := 'Z';
    VARIABLE DATA_B12 : std_logic := 'Z';
    VARIABLE DATA_B13 : std_logic := 'Z';
    VARIABLE DATA_B14 : std_logic := 'Z';
    VARIABLE DATA_B15 : std_logic := 'Z';
    VARIABLE DATA_B16 : std_logic := 'Z';
    VARIABLE DATA_B17 : std_logic := 'Z';
    VARIABLE OE1_inverted : std_logic := 'Z';


    BEGIN
      OE1_inverted := NOT (OE1_ipd);
      con_b := VitalAND2(OE1_inverted, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);
      DATA_B9  := VITALBUFIF1(data_out_b(9),con_b);
      DATA_B10 := VITALBUFIF1(data_out_b(10),con_b);
      DATA_B11 := VITALBUFIF1(data_out_b(11),con_b);
      DATA_B12 := VITALBUFIF1(data_out_b(12),con_b);
      DATA_B13 := VITALBUFIF1(data_out_b(13),con_b);
      DATA_B14 := VITALBUFIF1(data_out_b(14),con_b);
      DATA_B15 := VITALBUFIF1(data_out_b(15),con_b);
      DATA_B16 := VITALBUFIF1(data_out_b(16),con_b);
      DATA_B17 := VITALBUFIF1(data_out_b(17),con_b);


      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB1, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB2, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB3, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB4, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB5, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB6, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB7, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB8, GLITCH_DATA_B8, "DB8", DATA_B8,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB8, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB9, GLITCH_DATA_B9, "DB9", DATA_B9,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB9, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB10, GLITCH_DATA_B10, "DB10", DATA_B10,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB10, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB11, GLITCH_DATA_B11, "DB11", DATA_B11,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB11, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB12, GLITCH_DATA_B12, "DB12", DATA_B12,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB12, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB13, GLITCH_DATA_B13, "DB13", DATA_B13,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB13, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB14, GLITCH_DATA_B14, "DB14", DATA_B14,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB14, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB15, GLITCH_DATA_B15, "DB15", DATA_B15,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB15, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B16, "EDB0", DATA_B16,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_EDB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB1, GLITCH_DATA_B17, "EDB1", DATA_B17,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_EDB1, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB256X18DSR_1_VITAL of RAMB256X18DSR_1 is
   for VITAL
   end for;
end CFG_RAMB256X18DSR_1_VITAL;

----- CELL RAMB256X18DSF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18DSF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK0_DA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA8                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA9                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA10                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA11                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA12                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA13                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA14                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA15                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_EDA0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_EDA1                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB8                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB9                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB10                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB11                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB12                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB13                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB14                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB15                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_EDB0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_EDB1                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE0_RWCLK0_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      thold_CE0_RWCLK0_noedge_negedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CE1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      thold_CE1_RWCLK1_noedge_negedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA8_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA8_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA9_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA9_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA10_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA10_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA11_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA11_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA12_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA12_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA13_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA13_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA14_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA14_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA15_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA15_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA1_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB8_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB8_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB9_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB9_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB10_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB10_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB11_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB11_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB12_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB12_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB13_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB13_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB14_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB14_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB15_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB15_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB1_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;


      tpw_RWCLK0_negedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_negedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
      CE0                            :	in    STD_ULOGIC;
      CE1                            :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      DA8                            :	inout STD_ULOGIC;
      DA9                            :	inout STD_ULOGIC;
      DA10                           :	inout STD_ULOGIC;
      DA11                           :	inout STD_ULOGIC;
      DA12                           :	inout STD_ULOGIC;
      DA13                           :	inout STD_ULOGIC;
      DA14                           :	inout STD_ULOGIC;
      DA15                           :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      EDA1                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      DB8                            :	inout STD_ULOGIC;
      DB9                            :	inout STD_ULOGIC;
      DB10                           :	inout STD_ULOGIC;
      DB11                           :	inout STD_ULOGIC;
      DB12                           :	inout STD_ULOGIC;
      DB13                           :	inout STD_ULOGIC;
      DB14                           :	inout STD_ULOGIC;
      DB15                           :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC;
      EDB1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18DSF : entity is TRUE;
end RAMB256X18DSF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18DSF is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
      SIGNAL CE0_ipd                 :   std_logic :='X';
      SIGNAL CE1_ipd                 :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL DA8_ipd                 :   std_logic :='X';
      SIGNAL DA9_ipd                 :   std_logic :='X';
      SIGNAL DA10_ipd                :   std_logic :='X';
      SIGNAL DA11_ipd                :   std_logic :='X';
      SIGNAL DA12_ipd                :   std_logic :='X';
      SIGNAL DA13_ipd                :   std_logic :='X';
      SIGNAL DA14_ipd                :   std_logic :='X';
      SIGNAL DA15_ipd                :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL EDA1_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL DB8_ipd                 :   std_logic :='X';
      SIGNAL DB9_ipd                 :   std_logic :='X';
      SIGNAL DB10_ipd                :   std_logic :='X';
      SIGNAL DB11_ipd                :   std_logic :='X';
      SIGNAL DB12_ipd                :   std_logic :='X';
      SIGNAL DB13_ipd                :   std_logic :='X';
      SIGNAL DB14_ipd                :   std_logic :='X';
      SIGNAL DB15_ipd                :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';
      SIGNAL EDB1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;
      SIGNAL data_out_b              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL rd_clk0                 :   std_logic  := 'X';
      SIGNAL rd_clk1                 :   std_logic  := 'X';

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);
      SIGNAL din_b                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
	VitalWireDelay (CE0_ipd,      CE0,        tipd_CE0);
	VitalWireDelay (CE1_ipd,      CE1,        tipd_CE1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (DA8_ipd,      DA8,        tipd_DA8);
	VitalWireDelay (DA9_ipd,      DA9,        tipd_DA9);
	VitalWireDelay (DA10_ipd,     DA10,       tipd_DA10);
	VitalWireDelay (DA11_ipd,     DA11,       tipd_DA11);
	VitalWireDelay (DA12_ipd,     DA12,       tipd_DA12);
	VitalWireDelay (DA13_ipd,     DA13,       tipd_DA13);
	VitalWireDelay (DA14_ipd,     DA14,       tipd_DA14);
	VitalWireDelay (DA15_ipd,     DA15,       tipd_DA15);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);
	VitalWireDelay (EDA1_ipd,     EDA1,       tipd_EDA1);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (DB8_ipd,      DB8,        tipd_DB8);
	VitalWireDelay (DB9_ipd,      DB9,        tipd_DB9);
	VitalWireDelay (DB10_ipd,     DB10,       tipd_DB10);
	VitalWireDelay (DB11_ipd,     DB11,       tipd_DB11);
	VitalWireDelay (DB12_ipd,     DB12,       tipd_DB12);
	VitalWireDelay (DB13_ipd,     DB13,       tipd_DB13);
	VitalWireDelay (DB14_ipd,     DB14,       tipd_DB14);
	VitalWireDelay (DB15_ipd,     DB15,       tipd_DB15);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
	VitalWireDelay (EDB1_ipd,     EDB1,       tipd_EDB1);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '1' and WEN0_ipd = '1') then
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '1' and WEN1_ipd = '1') then
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_8;
   end if;
   end process wrapper_read_add_b;


   wrapper_read_clk_a : process(OE0_ipd, RWCLK0_ipd, CE0_ipd, WEN0_ipd)

   begin
    if (OE0_ipd = '1' and WEN0_ipd = '1' and CE0_ipd ='0') then
	rd_clk0 <= RWCLK0_ipd;
    else
	rd_clk0 <= '1';
    end if;
   end process;

   wrapper_read_clk_b : process(OE1_ipd, RWCLK1_ipd, CE1_ipd,WEN1_ipd)

   begin
    if (OE1_ipd = '1' and WEN1_ipd = '1' and CE1_ipd ='0') then
	rd_clk1 <= RWCLK1_ipd;
    else
	rd_clk1 <= '1';
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd, CE0_ipd)
   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd)

   begin
--    if (WEN0_ipd = '0' and CE0_ipd = '0' ) then
    if (WEN0_ipd = '0') then
	wr_clk0 <= RWCLK0_ipd;
    else
	wr_clk0 <= '1';
    end if;
   end process;

--   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd, CE1_ipd)
   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd)

   begin
--    if (WEN1_ipd = '0'and CE1_ipd = '0') then
    if (WEN1_ipd = '0') then
	wr_clk1 <= RWCLK1_ipd;
    else
	wr_clk1 <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DA15_ipd, 
                                  DA14_ipd, 
                                  DA13_ipd, 
                                  DA12_ipd, 
                                  DA11_ipd, 
                                  DA10_ipd, 
                                  DA9_ipd, 
                                  DA8_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(17) <= EDA1_ipd;
        din_a(16) <= EDA0_ipd;
        din_a(15) <= DA15_ipd;
        din_a(14) <= DA14_ipd;
        din_a(13) <= DA13_ipd;
        din_a(12) <= DA12_ipd;
        din_a(11) <= DA11_ipd;
        din_a(10) <= DA10_ipd;
        din_a(9)  <= DA9_ipd;
        din_a(8)  <= DA8_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DB15_ipd, 
                                  DB14_ipd, 
                                  DB13_ipd, 
                                  DB12_ipd, 
                                  DB11_ipd, 
                                  DB10_ipd, 
                                  DB9_ipd, 
                                  DB8_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(17) <= EDB1_ipd;
        din_b(16) <= EDB0_ipd;
        din_b(15) <= DB15_ipd;
        din_b(14) <= DB14_ipd;
        din_b(13) <= DB13_ipd;
        din_b(12) <= DB12_ipd;
        din_b(11) <= DB11_ipd;
        din_b(10) <= DB10_ipd;
        din_b(9)  <= DB9_ipd;
        din_b(8)  <= DB8_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18DSF Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            rd_clk0, rd_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_negedge   : std_ulogic  := '0';

        variable Tviol_CE0_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_CE1_RWCLK1_negedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_negedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_negedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA8_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA9_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA10_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_DA11_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_DA12_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_DA13_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_DA14_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_DA15_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_EDA1_RWCLK0_negedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB8_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB9_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB10_RWCLK1_negedge   : std_ulogic  := '0';
        variable Tviol_DB11_RWCLK1_negedge   : std_ulogic  := '0';
        variable Tviol_DB12_RWCLK1_negedge   : std_ulogic  := '0';
        variable Tviol_DB13_RWCLK1_negedge   : std_ulogic  := '0';
        variable Tviol_DB14_RWCLK1_negedge   : std_ulogic  := '0';
        variable Tviol_DB15_RWCLK1_negedge   : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_negedge   : std_ulogic  := '0';
        variable Tviol_EDB1_RWCLK1_negedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE0_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CE1_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA8_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA9_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA10_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA11_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA12_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA13_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA14_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA15_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA1_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB8_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB9_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB10_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB11_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB12_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB13_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB14_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB15_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB1_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_negedge,
          TimingData              => Tmkr_WEN0_RWCLK0_negedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_negedge,
          TimingData              => Tmkr_WEN1_RWCLK1_negedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE0_RWCLK0_negedge,
          TimingData              => Tmkr_CE0_RWCLK0_negedge,
          TestSignal              => CE0_ipd,
          TestSignalName          => "CE0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_CE0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_CE0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_CE0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE1_RWCLK1_negedge,
          TimingData              => Tmkr_CE1_RWCLK1_negedge,
          TestSignal              => CE1_ipd,
          TestSignalName          => "CE1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_CE1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_CE1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_CE1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_negedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_negedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_negedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_negedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_negedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_negedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_negedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_negedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_negedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_negedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_negedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_negedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_negedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_negedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_negedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_negedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_negedge,
          TimingData              => Tmkr_DA0_RWCLK0_negedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_negedge,
          TimingData              => Tmkr_DA1_RWCLK0_negedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_negedge,
          TimingData              => Tmkr_DA2_RWCLK0_negedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_negedge,
          TimingData              => Tmkr_DA3_RWCLK0_negedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_negedge,
          TimingData              => Tmkr_DA4_RWCLK0_negedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_negedge,
          TimingData              => Tmkr_DA5_RWCLK0_negedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_negedge,
          TimingData              => Tmkr_DA6_RWCLK0_negedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_negedge,
          TimingData              => Tmkr_DA7_RWCLK0_negedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA8_RWCLK0_negedge,
          TimingData              => Tmkr_DA8_RWCLK0_negedge,
          TestSignal              => DA8_ipd,
          TestSignalName          => "DA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA8_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA8_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA8_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA8_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA9_RWCLK0_negedge,
          TimingData              => Tmkr_DA9_RWCLK0_negedge,
          TestSignal              => DA9_ipd,
          TestSignalName          => "DA9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA9_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA9_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA9_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA9_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA10_RWCLK0_negedge,
          TimingData              => Tmkr_DA10_RWCLK0_negedge,
          TestSignal              => DA10_ipd,
          TestSignalName          => "DA10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA10_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA10_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA10_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA10_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA11_RWCLK0_negedge,
          TimingData              => Tmkr_DA11_RWCLK0_negedge,
          TestSignal              => DA11_ipd,
          TestSignalName          => "DA11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA11_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA11_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA11_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA11_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA12_RWCLK0_negedge,
          TimingData              => Tmkr_DA12_RWCLK0_negedge,
          TestSignal              => DA12_ipd,
          TestSignalName          => "DA12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA12_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA12_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA12_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA12_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA13_RWCLK0_negedge,
          TimingData              => Tmkr_DA13_RWCLK0_negedge,
          TestSignal              => DA13_ipd,
          TestSignalName          => "DA13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA13_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA13_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA13_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA13_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA14_RWCLK0_negedge,
          TimingData              => Tmkr_DA14_RWCLK0_negedge,
          TestSignal              => DA14_ipd,
          TestSignalName          => "DA14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA14_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA14_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA14_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA14_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA15_RWCLK0_negedge,
          TimingData              => Tmkr_DA15_RWCLK0_negedge,
          TestSignal              => DA15_ipd,
          TestSignalName          => "DA15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA15_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA15_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_negedge,
          TimingData              => Tmkr_EDA0_RWCLK0_negedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA1_RWCLK0_negedge,
          TimingData              => Tmkr_EDA1_RWCLK0_negedge,
          TestSignal              => EDA1_ipd,
          TestSignalName          => "EDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_EDA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_EDA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_EDA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_negedge,
          TimingData              => Tmkr_DB0_RWCLK1_negedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_negedge,
          TimingData              => Tmkr_DB1_RWCLK1_negedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_negedge,
          TimingData              => Tmkr_DB2_RWCLK1_negedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_negedge,
          TimingData              => Tmkr_DB3_RWCLK1_negedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_negedge,
          TimingData              => Tmkr_DB4_RWCLK1_negedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_negedge,
          TimingData              => Tmkr_DB5_RWCLK1_negedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_negedge,
          TimingData              => Tmkr_DB6_RWCLK1_negedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_negedge,
          TimingData              => Tmkr_DB7_RWCLK1_negedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB8_RWCLK1_negedge,
          TimingData              => Tmkr_DB8_RWCLK1_negedge,
          TestSignal              => DB8_ipd,
          TestSignalName          => "DB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB8_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB8_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB8_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB8_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB9_RWCLK1_negedge,
          TimingData              => Tmkr_DB9_RWCLK1_negedge,
          TestSignal              => DB9_ipd,
          TestSignalName          => "DB9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB9_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB9_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB9_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB9_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB10_RWCLK1_negedge,
          TimingData              => Tmkr_DB10_RWCLK1_negedge,
          TestSignal              => DB10_ipd,
          TestSignalName          => "DB10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB10_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB10_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB10_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB10_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB11_RWCLK1_negedge,
          TimingData              => Tmkr_DB11_RWCLK1_negedge,
          TestSignal              => DB11_ipd,
          TestSignalName          => "DB11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB11_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB11_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB11_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB11_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB12_RWCLK1_negedge,
          TimingData              => Tmkr_DB12_RWCLK1_negedge,
          TestSignal              => DB12_ipd,
          TestSignalName          => "DB12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB12_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB12_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB12_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB12_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB13_RWCLK1_negedge,
          TimingData              => Tmkr_DB13_RWCLK1_negedge,
          TestSignal              => DB13_ipd,
          TestSignalName          => "DB13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB13_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB13_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB13_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB13_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB14_RWCLK1_negedge,
          TimingData              => Tmkr_DB14_RWCLK1_negedge,
          TestSignal              => DB14_ipd,
          TestSignalName          => "DB14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB14_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB14_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB14_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB14_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB15_RWCLK1_negedge,
          TimingData              => Tmkr_DB15_RWCLK1_negedge,
          TestSignal              => DB15_ipd,
          TestSignalName          => "DB15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB15_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB15_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_negedge,
          TimingData              => Tmkr_EDB0_RWCLK1_negedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB1_RWCLK1_negedge,
          TimingData              => Tmkr_EDB1_RWCLK1_negedge,
          TestSignal              => EDB1_ipd,
          TestSignalName          => "EDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_EDB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_EDB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_EDB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_negedge,
          PulseWidthLow           => tpw_RWCLK0_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_negedge,
          PulseWidthLow           => tpw_RWCLK1_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk0'EVENT and rd_clk0 = '0' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '0' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '0' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( (rd_clk1'EVENT and rd_clk1 = '0') and not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10 : std_logic := 'Z';
    VARIABLE DATA_A11 : std_logic := 'Z';
    VARIABLE DATA_A12 : std_logic := 'Z';
    VARIABLE DATA_A13 : std_logic := 'Z';
    VARIABLE DATA_A14 : std_logic := 'Z';
    VARIABLE DATA_A15 : std_logic := 'Z';
    VARIABLE DATA_A16 : std_logic := 'Z';
    VARIABLE DATA_A17 : std_logic := 'Z';


    BEGIN

      con_a := VitalAND2(OE0_ipd, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10 := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11 := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12 := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13 := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14 := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15 := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16 := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17 := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA1, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA2, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA3, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA4, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA5, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA6, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA7, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA8, GLITCH_DATA_A8, "DA8", DATA_A8,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA8, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA9, GLITCH_DATA_A9, "DA9", DATA_A9,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA9, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA10, GLITCH_DATA_A10, "DA10", DATA_A10,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA10, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA11, GLITCH_DATA_A11, "DA11", DATA_A11,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA11, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA12, GLITCH_DATA_A12, "DA12", DATA_A12,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA12, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA13, GLITCH_DATA_A13, "DA13", DATA_A13,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA13, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA14, GLITCH_DATA_A14, "DA14", DATA_A14,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA14, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA15, GLITCH_DATA_A15, "DA15", DATA_A15,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA15, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A16, "EDA0", DATA_A16,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_EDA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA1, GLITCH_DATA_A17, "EDA1", DATA_A17,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_EDA1, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B17 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';
    VARIABLE DATA_B9  : std_logic := 'Z';
    VARIABLE DATA_B10 : std_logic := 'Z';
    VARIABLE DATA_B11 : std_logic := 'Z';
    VARIABLE DATA_B12 : std_logic := 'Z';
    VARIABLE DATA_B13 : std_logic := 'Z';
    VARIABLE DATA_B14 : std_logic := 'Z';
    VARIABLE DATA_B15 : std_logic := 'Z';
    VARIABLE DATA_B16 : std_logic := 'Z';
    VARIABLE DATA_B17 : std_logic := 'Z';


    BEGIN

      con_b := VitalAND2(OE1_ipd, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);
      DATA_B9  := VITALBUFIF1(data_out_b(9),con_b);
      DATA_B10 := VITALBUFIF1(data_out_b(10),con_b);
      DATA_B11 := VITALBUFIF1(data_out_b(11),con_b);
      DATA_B12 := VITALBUFIF1(data_out_b(12),con_b);
      DATA_B13 := VITALBUFIF1(data_out_b(13),con_b);
      DATA_B14 := VITALBUFIF1(data_out_b(14),con_b);
      DATA_B15 := VITALBUFIF1(data_out_b(15),con_b);
      DATA_B16 := VITALBUFIF1(data_out_b(16),con_b);
      DATA_B17 := VITALBUFIF1(data_out_b(17),con_b);


      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB1, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB2, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB3, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB4, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB5, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB6, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB7, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB8, GLITCH_DATA_B8, "DB8", DATA_B8,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB8, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB9, GLITCH_DATA_B9, "DB9", DATA_B9,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB9, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB10, GLITCH_DATA_B10, "DB10", DATA_B10,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB10, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB11, GLITCH_DATA_B11, "DB11", DATA_B11,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB11, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB12, GLITCH_DATA_B12, "DB12", DATA_B12,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB12, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB13, GLITCH_DATA_B13, "DB13", DATA_B13,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB13, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB14, GLITCH_DATA_B14, "DB14", DATA_B14,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB14, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB15, GLITCH_DATA_B15, "DB15", DATA_B15,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB15, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B16, "EDB0", DATA_B16,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_EDB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB1, GLITCH_DATA_B17, "EDB1", DATA_B17,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_EDB1, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB256X18DSF_VITAL of RAMB256X18DSF is
   for VITAL
   end for;
end CFG_RAMB256X18DSF_VITAL;

----- CELL RAMB256X18DSF_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18DSF_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK0_DA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA8                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA9                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA10                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA11                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA12                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA13                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA14                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA15                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_EDA0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_EDA1                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB8                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB9                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB10                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB11                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB12                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB13                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB14                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB15                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_EDB0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_EDB1                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE0_RWCLK0_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      thold_CE0_RWCLK0_noedge_negedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CE1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      thold_CE1_RWCLK1_noedge_negedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA8_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA8_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA9_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA9_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA10_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA10_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA11_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA11_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA12_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA12_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA13_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA13_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA14_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA14_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA15_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA15_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA1_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB8_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB8_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB9_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB9_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB10_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB10_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB11_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB11_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB12_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB12_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB13_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB13_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB14_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB14_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB15_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB15_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB1_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;


      tpw_RWCLK0_negedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_negedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
      CE0                            :	in    STD_ULOGIC;
      CE1                            :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      DA8                            :	inout STD_ULOGIC;
      DA9                            :	inout STD_ULOGIC;
      DA10                           :	inout STD_ULOGIC;
      DA11                           :	inout STD_ULOGIC;
      DA12                           :	inout STD_ULOGIC;
      DA13                           :	inout STD_ULOGIC;
      DA14                           :	inout STD_ULOGIC;
      DA15                           :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      EDA1                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      DB8                            :	inout STD_ULOGIC;
      DB9                            :	inout STD_ULOGIC;
      DB10                           :	inout STD_ULOGIC;
      DB11                           :	inout STD_ULOGIC;
      DB12                           :	inout STD_ULOGIC;
      DB13                           :	inout STD_ULOGIC;
      DB14                           :	inout STD_ULOGIC;
      DB15                           :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC;
      EDB1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18DSF_1 : entity is TRUE;
end RAMB256X18DSF_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18DSF_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
      SIGNAL CE0_ipd                 :   std_logic :='X';
      SIGNAL CE1_ipd                 :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL DA8_ipd                 :   std_logic :='X';
      SIGNAL DA9_ipd                 :   std_logic :='X';
      SIGNAL DA10_ipd                :   std_logic :='X';
      SIGNAL DA11_ipd                :   std_logic :='X';
      SIGNAL DA12_ipd                :   std_logic :='X';
      SIGNAL DA13_ipd                :   std_logic :='X';
      SIGNAL DA14_ipd                :   std_logic :='X';
      SIGNAL DA15_ipd                :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL EDA1_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL DB8_ipd                 :   std_logic :='X';
      SIGNAL DB9_ipd                 :   std_logic :='X';
      SIGNAL DB10_ipd                :   std_logic :='X';
      SIGNAL DB11_ipd                :   std_logic :='X';
      SIGNAL DB12_ipd                :   std_logic :='X';
      SIGNAL DB13_ipd                :   std_logic :='X';
      SIGNAL DB14_ipd                :   std_logic :='X';
      SIGNAL DB15_ipd                :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';
      SIGNAL EDB1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;
      SIGNAL data_out_b              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL rd_clk0                 :   std_logic  := 'X';
      SIGNAL rd_clk1                 :   std_logic  := 'X';

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);
      SIGNAL din_b                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
	VitalWireDelay (CE0_ipd,      CE0,        tipd_CE0);
	VitalWireDelay (CE1_ipd,      CE1,        tipd_CE1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (DA8_ipd,      DA8,        tipd_DA8);
	VitalWireDelay (DA9_ipd,      DA9,        tipd_DA9);
	VitalWireDelay (DA10_ipd,     DA10,       tipd_DA10);
	VitalWireDelay (DA11_ipd,     DA11,       tipd_DA11);
	VitalWireDelay (DA12_ipd,     DA12,       tipd_DA12);
	VitalWireDelay (DA13_ipd,     DA13,       tipd_DA13);
	VitalWireDelay (DA14_ipd,     DA14,       tipd_DA14);
	VitalWireDelay (DA15_ipd,     DA15,       tipd_DA15);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);
	VitalWireDelay (EDA1_ipd,     EDA1,       tipd_EDA1);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (DB8_ipd,      DB8,        tipd_DB8);
	VitalWireDelay (DB9_ipd,      DB9,        tipd_DB9);
	VitalWireDelay (DB10_ipd,     DB10,       tipd_DB10);
	VitalWireDelay (DB11_ipd,     DB11,       tipd_DB11);
	VitalWireDelay (DB12_ipd,     DB12,       tipd_DB12);
	VitalWireDelay (DB13_ipd,     DB13,       tipd_DB13);
	VitalWireDelay (DB14_ipd,     DB14,       tipd_DB14);
	VitalWireDelay (DB15_ipd,     DB15,       tipd_DB15);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
	VitalWireDelay (EDB1_ipd,     EDB1,       tipd_EDB1);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '0' and WEN0_ipd = '1') then
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '0' and WEN1_ipd = '1') then
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_8;
   end if;
   end process wrapper_read_add_b;


   wrapper_read_clk_a : process(OE0_ipd, RWCLK0_ipd, CE0_ipd, WEN0_ipd)

   begin
    if (OE0_ipd = '0' and WEN0_ipd = '1' and CE0_ipd ='0') then
	rd_clk0 <= RWCLK0_ipd;
    else
	rd_clk0 <= '1';
    end if;
   end process;

   wrapper_read_clk_b : process(OE1_ipd, RWCLK1_ipd, CE1_ipd,WEN1_ipd)

   begin
    if (OE1_ipd = '0' and WEN1_ipd = '1' and CE1_ipd ='0') then
	rd_clk1 <= RWCLK1_ipd;
    else
	rd_clk1 <= '1';
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd, CE0_ipd)
   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd)

   begin
--    if (WEN0_ipd = '0' and CE0_ipd = '0' ) then
    if (WEN0_ipd = '0') then
	wr_clk0 <= RWCLK0_ipd;
    else
	wr_clk0 <= '1';
    end if;
   end process;

--   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd, CE1_ipd)
   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd)

   begin
--    if (WEN1_ipd = '0'and CE1_ipd = '0') then
    if (WEN1_ipd = '0') then
	wr_clk1 <= RWCLK1_ipd;
    else
	wr_clk1 <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DA15_ipd, 
                                  DA14_ipd, 
                                  DA13_ipd, 
                                  DA12_ipd, 
                                  DA11_ipd, 
                                  DA10_ipd, 
                                  DA9_ipd, 
                                  DA8_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(17) <= EDA1_ipd;
        din_a(16) <= EDA0_ipd;
        din_a(15) <= DA15_ipd;
        din_a(14) <= DA14_ipd;
        din_a(13) <= DA13_ipd;
        din_a(12) <= DA12_ipd;
        din_a(11) <= DA11_ipd;
        din_a(10) <= DA10_ipd;
        din_a(9)  <= DA9_ipd;
        din_a(8)  <= DA8_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DB15_ipd, 
                                  DB14_ipd, 
                                  DB13_ipd, 
                                  DB12_ipd, 
                                  DB11_ipd, 
                                  DB10_ipd, 
                                  DB9_ipd, 
                                  DB8_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(17) <= EDB1_ipd;
        din_b(16) <= EDB0_ipd;
        din_b(15) <= DB15_ipd;
        din_b(14) <= DB14_ipd;
        din_b(13) <= DB13_ipd;
        din_b(12) <= DB12_ipd;
        din_b(11) <= DB11_ipd;
        din_b(10) <= DB10_ipd;
        din_b(9)  <= DB9_ipd;
        din_b(8)  <= DB8_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18DSF_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            rd_clk0, rd_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_negedge   : std_ulogic  := '0';

        variable Tviol_CE0_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_CE1_RWCLK1_negedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_negedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_negedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA8_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA9_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA10_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_DA11_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_DA12_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_DA13_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_DA14_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_DA15_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_EDA1_RWCLK0_negedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB8_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB9_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB10_RWCLK1_negedge   : std_ulogic  := '0';
        variable Tviol_DB11_RWCLK1_negedge   : std_ulogic  := '0';
        variable Tviol_DB12_RWCLK1_negedge   : std_ulogic  := '0';
        variable Tviol_DB13_RWCLK1_negedge   : std_ulogic  := '0';
        variable Tviol_DB14_RWCLK1_negedge   : std_ulogic  := '0';
        variable Tviol_DB15_RWCLK1_negedge   : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_negedge   : std_ulogic  := '0';
        variable Tviol_EDB1_RWCLK1_negedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE0_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CE1_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA8_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA9_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA10_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA11_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA12_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA13_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA14_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA15_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA1_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB8_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB9_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB10_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB11_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB12_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB13_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB14_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB15_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB1_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_negedge,
          TimingData              => Tmkr_WEN0_RWCLK0_negedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_negedge,
          TimingData              => Tmkr_WEN1_RWCLK1_negedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE0_RWCLK0_negedge,
          TimingData              => Tmkr_CE0_RWCLK0_negedge,
          TestSignal              => CE0_ipd,
          TestSignalName          => "CE0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_CE0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_CE0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_CE0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE1_RWCLK1_negedge,
          TimingData              => Tmkr_CE1_RWCLK1_negedge,
          TestSignal              => CE1_ipd,
          TestSignalName          => "CE1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_CE1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_CE1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_CE1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_negedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_negedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_negedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_negedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_negedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_negedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_negedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_negedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_negedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_negedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_negedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_negedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_negedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_negedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_negedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_negedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_negedge,
          TimingData              => Tmkr_DA0_RWCLK0_negedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_negedge,
          TimingData              => Tmkr_DA1_RWCLK0_negedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_negedge,
          TimingData              => Tmkr_DA2_RWCLK0_negedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_negedge,
          TimingData              => Tmkr_DA3_RWCLK0_negedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_negedge,
          TimingData              => Tmkr_DA4_RWCLK0_negedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_negedge,
          TimingData              => Tmkr_DA5_RWCLK0_negedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_negedge,
          TimingData              => Tmkr_DA6_RWCLK0_negedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_negedge,
          TimingData              => Tmkr_DA7_RWCLK0_negedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA8_RWCLK0_negedge,
          TimingData              => Tmkr_DA8_RWCLK0_negedge,
          TestSignal              => DA8_ipd,
          TestSignalName          => "DA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA8_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA8_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA8_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA8_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA9_RWCLK0_negedge,
          TimingData              => Tmkr_DA9_RWCLK0_negedge,
          TestSignal              => DA9_ipd,
          TestSignalName          => "DA9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA9_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA9_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA9_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA9_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA10_RWCLK0_negedge,
          TimingData              => Tmkr_DA10_RWCLK0_negedge,
          TestSignal              => DA10_ipd,
          TestSignalName          => "DA10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA10_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA10_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA10_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA10_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA11_RWCLK0_negedge,
          TimingData              => Tmkr_DA11_RWCLK0_negedge,
          TestSignal              => DA11_ipd,
          TestSignalName          => "DA11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA11_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA11_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA11_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA11_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA12_RWCLK0_negedge,
          TimingData              => Tmkr_DA12_RWCLK0_negedge,
          TestSignal              => DA12_ipd,
          TestSignalName          => "DA12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA12_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA12_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA12_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA12_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);


         VitalSetupHoldCheck (
          Violation               => Tviol_DA13_RWCLK0_negedge,
          TimingData              => Tmkr_DA13_RWCLK0_negedge,
          TestSignal              => DA13_ipd,
          TestSignalName          => "DA13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA13_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA13_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA13_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA13_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA14_RWCLK0_negedge,
          TimingData              => Tmkr_DA14_RWCLK0_negedge,
          TestSignal              => DA14_ipd,
          TestSignalName          => "DA14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA14_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA14_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA14_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA14_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA15_RWCLK0_negedge,
          TimingData              => Tmkr_DA15_RWCLK0_negedge,
          TestSignal              => DA15_ipd,
          TestSignalName          => "DA15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA15_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA15_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_negedge,
          TimingData              => Tmkr_EDA0_RWCLK0_negedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA1_RWCLK0_negedge,
          TimingData              => Tmkr_EDA1_RWCLK0_negedge,
          TestSignal              => EDA1_ipd,
          TestSignalName          => "EDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_EDA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_EDA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_EDA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_negedge,
          TimingData              => Tmkr_DB0_RWCLK1_negedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_negedge,
          TimingData              => Tmkr_DB1_RWCLK1_negedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_negedge,
          TimingData              => Tmkr_DB2_RWCLK1_negedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_negedge,
          TimingData              => Tmkr_DB3_RWCLK1_negedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_negedge,
          TimingData              => Tmkr_DB4_RWCLK1_negedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_negedge,
          TimingData              => Tmkr_DB5_RWCLK1_negedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_negedge,
          TimingData              => Tmkr_DB6_RWCLK1_negedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_negedge,
          TimingData              => Tmkr_DB7_RWCLK1_negedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB8_RWCLK1_negedge,
          TimingData              => Tmkr_DB8_RWCLK1_negedge,
          TestSignal              => DB8_ipd,
          TestSignalName          => "DB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB8_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB8_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB8_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB8_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB9_RWCLK1_negedge,
          TimingData              => Tmkr_DB9_RWCLK1_negedge,
          TestSignal              => DB9_ipd,
          TestSignalName          => "DB9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB9_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB9_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB9_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB9_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB10_RWCLK1_negedge,
          TimingData              => Tmkr_DB10_RWCLK1_negedge,
          TestSignal              => DB10_ipd,
          TestSignalName          => "DB10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB10_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB10_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB10_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB10_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB11_RWCLK1_negedge,
          TimingData              => Tmkr_DB11_RWCLK1_negedge,
          TestSignal              => DB11_ipd,
          TestSignalName          => "DB11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB11_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB11_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB11_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB11_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB12_RWCLK1_negedge,
          TimingData              => Tmkr_DB12_RWCLK1_negedge,
          TestSignal              => DB12_ipd,
          TestSignalName          => "DB12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB12_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB12_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB12_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB12_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB13_RWCLK1_negedge,
          TimingData              => Tmkr_DB13_RWCLK1_negedge,
          TestSignal              => DB13_ipd,
          TestSignalName          => "DB13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB13_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB13_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB13_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB13_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB14_RWCLK1_negedge,
          TimingData              => Tmkr_DB14_RWCLK1_negedge,
          TestSignal              => DB14_ipd,
          TestSignalName          => "DB14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB14_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB14_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB14_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB14_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB15_RWCLK1_negedge,
          TimingData              => Tmkr_DB15_RWCLK1_negedge,
          TestSignal              => DB15_ipd,
          TestSignalName          => "DB15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB15_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB15_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_negedge,
          TimingData              => Tmkr_EDB0_RWCLK1_negedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB1_RWCLK1_negedge,
          TimingData              => Tmkr_EDB1_RWCLK1_negedge,
          TestSignal              => EDB1_ipd,
          TestSignalName          => "EDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_EDB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_EDB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_EDB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_negedge,
          PulseWidthLow           => tpw_RWCLK0_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_negedge,
          PulseWidthLow           => tpw_RWCLK1_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk0'EVENT and rd_clk0 = '0' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '0' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '0' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( (rd_clk1'EVENT and rd_clk1 = '0') and not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10 : std_logic := 'Z';
    VARIABLE DATA_A11 : std_logic := 'Z';
    VARIABLE DATA_A12 : std_logic := 'Z';
    VARIABLE DATA_A13 : std_logic := 'Z';
    VARIABLE DATA_A14 : std_logic := 'Z';
    VARIABLE DATA_A15 : std_logic := 'Z';
    VARIABLE DATA_A16 : std_logic := 'Z';
    VARIABLE DATA_A17 : std_logic := 'Z';
    VARIABLE OE0_inverted : std_logic := '0';


    BEGIN
      OE0_inverted := NOT (OE0_ipd);
      con_a := VitalAND2(OE0_inverted, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10 := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11 := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12 := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13 := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14 := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15 := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16 := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17 := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA1, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA2, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA3, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA4, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA5, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA6, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA7, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA8, GLITCH_DATA_A8, "DA8", DATA_A8,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA8, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA9, GLITCH_DATA_A9, "DA9", DATA_A9,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA9, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA10, GLITCH_DATA_A10, "DA10", DATA_A10,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA10, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA11, GLITCH_DATA_A11, "DA11", DATA_A11,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA11, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA12, GLITCH_DATA_A12, "DA12", DATA_A12,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA12, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA13, GLITCH_DATA_A13, "DA13", DATA_A13,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA13, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA14, GLITCH_DATA_A14, "DA14", DATA_A14,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA14, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA15, GLITCH_DATA_A15, "DA15", DATA_A15,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA15, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A16, "EDA0", DATA_A16,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_EDA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA1, GLITCH_DATA_A17, "EDA1", DATA_A17,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_EDA1, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B17 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';
    VARIABLE DATA_B9  : std_logic := 'Z';
    VARIABLE DATA_B10 : std_logic := 'Z';
    VARIABLE DATA_B11 : std_logic := 'Z';
    VARIABLE DATA_B12 : std_logic := 'Z';
    VARIABLE DATA_B13 : std_logic := 'Z';
    VARIABLE DATA_B14 : std_logic := 'Z';
    VARIABLE DATA_B15 : std_logic := 'Z';
    VARIABLE DATA_B16 : std_logic := 'Z';
    VARIABLE DATA_B17 : std_logic := 'Z';
    VARIABLE OE1_inverted : std_logic := 'Z';


    BEGIN
      OE1_inverted := NOT (OE1_ipd);
      con_b := VitalAND2(OE1_inverted, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);
      DATA_B9  := VITALBUFIF1(data_out_b(9),con_b);
      DATA_B10 := VITALBUFIF1(data_out_b(10),con_b);
      DATA_B11 := VITALBUFIF1(data_out_b(11),con_b);
      DATA_B12 := VITALBUFIF1(data_out_b(12),con_b);
      DATA_B13 := VITALBUFIF1(data_out_b(13),con_b);
      DATA_B14 := VITALBUFIF1(data_out_b(14),con_b);
      DATA_B15 := VITALBUFIF1(data_out_b(15),con_b);
      DATA_B16 := VITALBUFIF1(data_out_b(16),con_b);
      DATA_B17 := VITALBUFIF1(data_out_b(17),con_b);


      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB1, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB2, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB3, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB4, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB5, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB6, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB7, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB8, GLITCH_DATA_B8, "DB8", DATA_B8,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB8, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB9, GLITCH_DATA_B9, "DB9", DATA_B9,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB9, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB10, GLITCH_DATA_B10, "DB10", DATA_B10,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB10, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB11, GLITCH_DATA_B11, "DB11", DATA_B11,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB11, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB12, GLITCH_DATA_B12, "DB12", DATA_B12,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB12, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB13, GLITCH_DATA_B13, "DB13", DATA_B13,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB13, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB14, GLITCH_DATA_B14, "DB14", DATA_B14,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB14, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB15, GLITCH_DATA_B15, "DB15", DATA_B15,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB15, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B16, "EDB0", DATA_B16,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_EDB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB1, GLITCH_DATA_B17, "EDB1", DATA_B17,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_EDB1, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB256X18DSF_1_VITAL of RAMB256X18DSF_1 is
   for VITAL
   end for;
end CFG_RAMB256X18DSF_1_VITAL;

----- CELL RAMB256X18DAR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18DAR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADDA0_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
--      tsetup_CE0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
--      thold_CE0_RWCLK0_noedge_posedge     :	VitalDelayType   := 0.0 ns;
--      tsetup_CE1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
--      thold_CE1_RWCLK1_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA8_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA8_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA9_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA9_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA10_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA10_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA11_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA11_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA12_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA12_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA13_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA13_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA14_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA14_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA15_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA15_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA1_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB8_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB8_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB9_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB9_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB10_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB10_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB11_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB11_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB12_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB12_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB13_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB13_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB14_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB14_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB15_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB15_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB1_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;


      tpw_RWCLK0_posedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

--      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
--      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
--      CE0                            :	in    STD_ULOGIC;
--      CE1                            :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      DA8                            :	inout STD_ULOGIC;
      DA9                            :	inout STD_ULOGIC;
      DA10                           :	inout STD_ULOGIC;
      DA11                           :	inout STD_ULOGIC;
      DA12                           :	inout STD_ULOGIC;
      DA13                           :	inout STD_ULOGIC;
      DA14                           :	inout STD_ULOGIC;
      DA15                           :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      EDA1                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      DB8                            :	inout STD_ULOGIC;
      DB9                            :	inout STD_ULOGIC;
      DB10                           :	inout STD_ULOGIC;
      DB11                           :	inout STD_ULOGIC;
      DB12                           :	inout STD_ULOGIC;
      DB13                           :	inout STD_ULOGIC;
      DB14                           :	inout STD_ULOGIC;
      DB15                           :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC;
      EDB1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18DAR : entity is TRUE;
end RAMB256X18DAR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18DAR is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
--      SIGNAL CE0_ipd                 :   std_logic :='X';
--      SIGNAL CE1_ipd                 :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL DA8_ipd                 :   std_logic :='X';
      SIGNAL DA9_ipd                 :   std_logic :='X';
      SIGNAL DA10_ipd                :   std_logic :='X';
      SIGNAL DA11_ipd                :   std_logic :='X';
      SIGNAL DA12_ipd                :   std_logic :='X';
      SIGNAL DA13_ipd                :   std_logic :='X';
      SIGNAL DA14_ipd                :   std_logic :='X';
      SIGNAL DA15_ipd                :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL EDA1_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL DB8_ipd                 :   std_logic :='X';
      SIGNAL DB9_ipd                 :   std_logic :='X';
      SIGNAL DB10_ipd                :   std_logic :='X';
      SIGNAL DB11_ipd                :   std_logic :='X';
      SIGNAL DB12_ipd                :   std_logic :='X';
      SIGNAL DB13_ipd                :   std_logic :='X';
      SIGNAL DB14_ipd                :   std_logic :='X';
      SIGNAL DB15_ipd                :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';
      SIGNAL EDB1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;
      SIGNAL data_out_b              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);
      SIGNAL din_b                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
--	VitalWireDelay (CE0_ipd,      CE0,        tipd_CE0);
--	VitalWireDelay (CE1_ipd,      CE1,        tipd_CE1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (DA8_ipd,      DA8,        tipd_DA8);
	VitalWireDelay (DA9_ipd,      DA9,        tipd_DA9);
	VitalWireDelay (DA10_ipd,     DA10,       tipd_DA10);
	VitalWireDelay (DA11_ipd,     DA11,       tipd_DA11);
	VitalWireDelay (DA12_ipd,     DA12,       tipd_DA12);
	VitalWireDelay (DA13_ipd,     DA13,       tipd_DA13);
	VitalWireDelay (DA14_ipd,     DA14,       tipd_DA14);
	VitalWireDelay (DA15_ipd,     DA15,       tipd_DA15);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);
	VitalWireDelay (EDA1_ipd,     EDA1,       tipd_EDA1);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (DB8_ipd,      DB8,        tipd_DB8);
	VitalWireDelay (DB9_ipd,      DB9,        tipd_DB9);
	VitalWireDelay (DB10_ipd,     DB10,       tipd_DB10);
	VitalWireDelay (DB11_ipd,     DB11,       tipd_DB11);
	VitalWireDelay (DB12_ipd,     DB12,       tipd_DB12);
	VitalWireDelay (DB13_ipd,     DB13,       tipd_DB13);
	VitalWireDelay (DB14_ipd,     DB14,       tipd_DB14);
	VitalWireDelay (DB15_ipd,     DB15,       tipd_DB15);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
	VitalWireDelay (EDB1_ipd,     EDB1,       tipd_EDB1);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '1' and WEN0_ipd = '1') then
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '1' and WEN1_ipd = '1') then
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_8;
   end if;
   end process wrapper_read_add_b;

--   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd, CE0_ipd)
   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd)

   begin
--    if (WEN0_ipd = '0' and CE0_ipd = '0' ) then
    if (WEN0_ipd = '0') then
	wr_clk0 <= RWCLK0_ipd;
    else
	wr_clk0 <= '0';
    end if;
   end process;

--   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd, CE1_ipd)
   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd)

   begin
--    if (WEN1_ipd = '0'and CE1_ipd = '0') then
    if (WEN1_ipd = '0') then
	wr_clk1 <= RWCLK1_ipd;
    else
	wr_clk1 <= '0';
    end if;
   end process;

   write_address_a : process(
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DA15_ipd, 
                                  DA14_ipd, 
                                  DA13_ipd, 
                                  DA12_ipd, 
                                  DA11_ipd, 
                                  DA10_ipd, 
                                  DA9_ipd, 
                                  DA8_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(17) <= EDA1_ipd;
        din_a(16) <= EDA0_ipd;
        din_a(15) <= DA15_ipd;
        din_a(14) <= DA14_ipd;
        din_a(13) <= DA13_ipd;
        din_a(12) <= DA12_ipd;
        din_a(11) <= DA11_ipd;
        din_a(10) <= DA10_ipd;
        din_a(9)  <= DA9_ipd;
        din_a(8)  <= DA8_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DB15_ipd, 
                                  DB14_ipd, 
                                  DB13_ipd, 
                                  DB12_ipd, 
                                  DB11_ipd, 
                                  DB10_ipd, 
                                  DB9_ipd, 
                                  DB8_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(17) <= EDB1_ipd;
        din_b(16) <= EDB0_ipd;
        din_b(15) <= DB15_ipd;
        din_b(14) <= DB14_ipd;
        din_b(13) <= DB13_ipd;
        din_b(12) <= DB12_ipd;
        din_b(11) <= DB11_ipd;
        din_b(10) <= DB10_ipd;
        din_b(9)  <= DB9_ipd;
        din_b(8)  <= DB8_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18DAR Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_posedge   : std_ulogic  := '0';

--        variable Tviol_CE0_RWCLK0_posedge    : std_ulogic  := '0';
--        variable Tviol_CE1_RWCLK1_posedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_posedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_posedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA8_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA9_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA10_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA11_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA12_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA13_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA14_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA15_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_EDA1_RWCLK0_posedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB8_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB9_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB10_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB11_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB12_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB13_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB14_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB15_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_EDB1_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

--        variable Tmkr_CE0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
--        variable Tmkr_CE1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA8_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA9_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA10_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA11_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA12_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA13_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA14_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA15_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA1_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB8_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB9_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB10_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB11_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB12_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB13_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB14_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB15_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_posedge,
          TimingData              => Tmkr_WEN0_RWCLK0_posedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_posedge,
          TimingData              => Tmkr_WEN1_RWCLK1_posedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

--         VitalSetupHoldCheck (
--          Violation               => Tviol_CE0_RWCLK0_posedge,
--          TimingData              => Tmkr_CE0_RWCLK0_posedge,
--          TestSignal              => CE0_ipd,
--          TestSignalName          => "CE0",
--          TestDelay               => 0 ns,
--          RefSignal               => RWCLK0_ipd,
--          RefSignalName           => "RWCLK0",
--          RefDelay                => 0 ns,
--          SetupHigh               => tsetup_CE0_RWCLK0_noedge_posedge,
--          SetupLow                => tsetup_CE0_RWCLK0_noedge_posedge,
--          HoldLow                 => thold_CE0_RWCLK0_noedge_posedge,
--          HoldHigh                => thold_CE0_RWCLK0_noedge_posedge,
--          CheckEnabled            => TRUE,
--          RefTransition           => 'R',
--          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
--          Xon                     => Xon,
--          MsgOn                   => MsgOn,
--          MsgSeverity             => WARNING);

--         VitalSetupHoldCheck (
--          Violation               => Tviol_CE1_RWCLK1_posedge,
--          TimingData              => Tmkr_CE1_RWCLK1_posedge,
--          TestSignal              => CE1_ipd,
--          TestSignalName          => "CE1",
--          TestDelay               => 0 ns,
--          RefSignal               => RWCLK1_ipd,
--          RefSignalName           => "RWCLK1",
--          RefDelay                => 0 ns,
--          SetupHigh               => tsetup_CE1_RWCLK1_noedge_posedge,
--          SetupLow                => tsetup_CE1_RWCLK1_noedge_posedge,
--          HoldLow                 => thold_CE1_RWCLK1_noedge_posedge,
--          HoldHigh                => thold_CE1_RWCLK1_noedge_posedge,
--          CheckEnabled            => TRUE,
--          RefTransition           => 'R',
--          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
--          Xon                     => Xon,
--          MsgOn                   => MsgOn,
--          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_posedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_posedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_posedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_posedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_posedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_posedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_posedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_posedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_posedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_posedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_posedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_posedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_posedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_posedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_posedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_posedge,
          TimingData              => Tmkr_DA0_RWCLK0_posedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_posedge,
          TimingData              => Tmkr_DA1_RWCLK0_posedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_posedge,
          TimingData              => Tmkr_DA2_RWCLK0_posedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_posedge,
          TimingData              => Tmkr_DA3_RWCLK0_posedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_posedge,
          TimingData              => Tmkr_DA4_RWCLK0_posedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_posedge,
          TimingData              => Tmkr_DA5_RWCLK0_posedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_posedge,
          TimingData              => Tmkr_DA6_RWCLK0_posedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_posedge,
          TimingData              => Tmkr_DA7_RWCLK0_posedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA8_RWCLK0_posedge,
          TimingData              => Tmkr_DA8_RWCLK0_posedge,
          TestSignal              => DA8_ipd,
          TestSignalName          => "DA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA8_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA8_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA8_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA8_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA9_RWCLK0_posedge,
          TimingData              => Tmkr_DA9_RWCLK0_posedge,
          TestSignal              => DA9_ipd,
          TestSignalName          => "DA9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA9_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA9_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA9_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA9_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA10_RWCLK0_posedge,
          TimingData              => Tmkr_DA10_RWCLK0_posedge,
          TestSignal              => DA10_ipd,
          TestSignalName          => "DA10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA10_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA10_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA10_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA10_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA11_RWCLK0_posedge,
          TimingData              => Tmkr_DA11_RWCLK0_posedge,
          TestSignal              => DA11_ipd,
          TestSignalName          => "DA11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA11_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA11_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA11_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA11_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA12_RWCLK0_posedge,
          TimingData              => Tmkr_DA12_RWCLK0_posedge,
          TestSignal              => DA12_ipd,
          TestSignalName          => "DA12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA12_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA12_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA12_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA12_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA13_RWCLK0_posedge,
          TimingData              => Tmkr_DA13_RWCLK0_posedge,
          TestSignal              => DA13_ipd,
          TestSignalName          => "DA13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA13_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA13_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA13_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA13_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA13_RWCLK0_posedge,
          TimingData              => Tmkr_DA13_RWCLK0_posedge,
          TestSignal              => DA13_ipd,
          TestSignalName          => "DA13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA13_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA13_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA13_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA13_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA14_RWCLK0_posedge,
          TimingData              => Tmkr_DA14_RWCLK0_posedge,
          TestSignal              => DA14_ipd,
          TestSignalName          => "DA14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA14_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA14_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA14_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA14_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA15_RWCLK0_posedge,
          TimingData              => Tmkr_DA15_RWCLK0_posedge,
          TestSignal              => DA15_ipd,
          TestSignalName          => "DA15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA15_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA15_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_posedge,
          TimingData              => Tmkr_EDA0_RWCLK0_posedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA1_RWCLK0_posedge,
          TimingData              => Tmkr_EDA1_RWCLK0_posedge,
          TestSignal              => EDA1_ipd,
          TestSignalName          => "EDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_EDA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_EDA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_EDA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_posedge,
          TimingData              => Tmkr_DB0_RWCLK1_posedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_posedge,
          TimingData              => Tmkr_DB1_RWCLK1_posedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_posedge,
          TimingData              => Tmkr_DB2_RWCLK1_posedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_posedge,
          TimingData              => Tmkr_DB3_RWCLK1_posedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_posedge,
          TimingData              => Tmkr_DB4_RWCLK1_posedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_posedge,
          TimingData              => Tmkr_DB5_RWCLK1_posedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_posedge,
          TimingData              => Tmkr_DB6_RWCLK1_posedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_posedge,
          TimingData              => Tmkr_DB7_RWCLK1_posedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB8_RWCLK1_posedge,
          TimingData              => Tmkr_DB8_RWCLK1_posedge,
          TestSignal              => DB8_ipd,
          TestSignalName          => "DB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB8_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB8_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB8_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB8_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB9_RWCLK1_posedge,
          TimingData              => Tmkr_DB9_RWCLK1_posedge,
          TestSignal              => DB9_ipd,
          TestSignalName          => "DB9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB9_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB9_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB9_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB9_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB10_RWCLK1_posedge,
          TimingData              => Tmkr_DB10_RWCLK1_posedge,
          TestSignal              => DB10_ipd,
          TestSignalName          => "DB10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB10_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB10_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB10_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB10_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB11_RWCLK1_posedge,
          TimingData              => Tmkr_DB11_RWCLK1_posedge,
          TestSignal              => DB11_ipd,
          TestSignalName          => "DB11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB11_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB11_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB11_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB11_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB12_RWCLK1_posedge,
          TimingData              => Tmkr_DB12_RWCLK1_posedge,
          TestSignal              => DB12_ipd,
          TestSignalName          => "DB12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB12_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB12_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB12_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB12_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB13_RWCLK1_posedge,
          TimingData              => Tmkr_DB13_RWCLK1_posedge,
          TestSignal              => DB13_ipd,
          TestSignalName          => "DB13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB13_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB13_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB13_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB13_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB13_RWCLK1_posedge,
          TimingData              => Tmkr_DB13_RWCLK1_posedge,
          TestSignal              => DB13_ipd,
          TestSignalName          => "DB13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB13_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB13_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB13_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB13_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB14_RWCLK1_posedge,
          TimingData              => Tmkr_DB14_RWCLK1_posedge,
          TestSignal              => DB14_ipd,
          TestSignalName          => "DB14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB14_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB14_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB14_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB14_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB15_RWCLK1_posedge,
          TimingData              => Tmkr_DB15_RWCLK1_posedge,
          TestSignal              => DB15_ipd,
          TestSignalName          => "DB15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB15_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB15_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_posedge,
          TimingData              => Tmkr_EDB0_RWCLK1_posedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB1_RWCLK1_posedge,
          TimingData              => Tmkr_EDB1_RWCLK1_posedge,
          TestSignal              => EDB1_ipd,
          TestSignalName          => "EDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_EDB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_EDB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_EDB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_posedge,
          PulseWidthLow           => tpw_RWCLK0_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_posedge,
          PulseWidthLow           => tpw_RWCLK1_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '1' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '1' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10 : std_logic := 'Z';
    VARIABLE DATA_A11 : std_logic := 'Z';
    VARIABLE DATA_A12 : std_logic := 'Z';
    VARIABLE DATA_A13 : std_logic := 'Z';
    VARIABLE DATA_A14 : std_logic := 'Z';
    VARIABLE DATA_A15 : std_logic := 'Z';
    VARIABLE DATA_A16 : std_logic := 'Z';
    VARIABLE DATA_A17 : std_logic := 'Z';


    BEGIN

      con_a := VitalAND2(OE0_ipd, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10 := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11 := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12 := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13 := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14 := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15 := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16 := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17 := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA0, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA1, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA1, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA1, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA1, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA1, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA1, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA1, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA1, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA2, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA2, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA2, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA2, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA2, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA2, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA2, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA2, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA3, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA3, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA3, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA3, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA3, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA3, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA3, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA3, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA4, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA4, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA4, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA4, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA4, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA4, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA4, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA4, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA5, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA5, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA5, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA5, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA5, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA5, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA5, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA5, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA6, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA6, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA6, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA6, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA6, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA6, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA6, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA6, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA7, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA7, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA7, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA7, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA7, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA7, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA7, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA7, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA8, GLITCH_DATA_A8, "DA8", DATA_A8,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA8, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA8, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA8, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA8, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA8, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA8, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA8, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA8, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA9, GLITCH_DATA_A9, "DA9", DATA_A9,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA9, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA9, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA9, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA9, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA9, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA9, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA9, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA9, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA10, GLITCH_DATA_A10, "DA10", DATA_A10,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA10, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA10, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA10, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA10, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA10, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA10, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA10, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA10, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA11, GLITCH_DATA_A11, "DA11", DATA_A11,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA11, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA11, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA11, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA11, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA11, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA11, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA11, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA11, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA12, GLITCH_DATA_A12, "DA12", DATA_A12,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA12, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA12, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA12, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA12, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA12, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA12, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA12, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA12, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA13, GLITCH_DATA_A13, "DA13", DATA_A13,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA13, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA13, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA13, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA13, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA13, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA13, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA13, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA13, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA14, GLITCH_DATA_A14, "DA14", DATA_A14,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA14, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA14, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA14, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA14, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA14, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA14, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA14, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA14, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA15, GLITCH_DATA_A15, "DA15", DATA_A15,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA15, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA15, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA15, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA15, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA15, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA15, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA15, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA15, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A16, "EDA0", DATA_A16,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_EDA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_EDA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_EDA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_EDA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_EDA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_EDA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_EDA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_EDA0, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA1, GLITCH_DATA_A17, "EDA1", DATA_A17,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_EDA1, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_EDA1, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_EDA1, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_EDA1, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_EDA1, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_EDA1, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_EDA1, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_EDA1, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B17 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';
    VARIABLE DATA_B9  : std_logic := 'Z';
    VARIABLE DATA_B10 : std_logic := 'Z';
    VARIABLE DATA_B11 : std_logic := 'Z';
    VARIABLE DATA_B12 : std_logic := 'Z';
    VARIABLE DATA_B13 : std_logic := 'Z';
    VARIABLE DATA_B14 : std_logic := 'Z';
    VARIABLE DATA_B15 : std_logic := 'Z';
    VARIABLE DATA_B16 : std_logic := 'Z';
    VARIABLE DATA_B17 : std_logic := 'Z';


    BEGIN

      con_b := VitalAND2(OE1_ipd, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);
      DATA_B9  := VITALBUFIF1(data_out_b(9),con_b);
      DATA_B10 := VITALBUFIF1(data_out_b(10),con_b);
      DATA_B11 := VITALBUFIF1(data_out_b(11),con_b);
      DATA_B12 := VITALBUFIF1(data_out_b(12),con_b);
      DATA_B13 := VITALBUFIF1(data_out_b(13),con_b);
      DATA_B14 := VITALBUFIF1(data_out_b(14),con_b);
      DATA_B15 := VITALBUFIF1(data_out_b(15),con_b);
      DATA_B16 := VITALBUFIF1(data_out_b(16),con_b);
      DATA_B17 := VITALBUFIF1(data_out_b(17),con_b);


      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB0, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB1, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB1, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB1, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB1, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB1, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB1, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB1, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB1, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB2, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB2, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB2, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB2, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB2, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB2, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB2, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB2, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB3, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB3, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB3, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB3, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB3, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB3, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB3, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB3, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB4, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB4, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB4, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB4, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB4, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB4, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB4, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB4, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB5, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB5, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB5, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB5, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB5, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB5, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB5, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB5, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB6, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB6, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB6, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB6, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB6, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB6, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB6, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB6, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB7, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB7, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB7, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB7, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB7, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB7, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB7, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB7, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB8, GLITCH_DATA_B8, "DB8", DATA_B8,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB8, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB8, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB8, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB8, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB8, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB8, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB8, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB8, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB9, GLITCH_DATA_B9, "DB9", DATA_B9,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB9, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB9, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB9, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB9, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB9, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB9, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB9, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB9, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB10, GLITCH_DATA_B10, "DB10", DATA_B10,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB10, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB10, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB10, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB10, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB10, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB10, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB10, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB10, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB11, GLITCH_DATA_B11, "DB11", DATA_B11,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB11, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB11, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB11, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB11, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB11, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB11, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB11, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB11, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB12, GLITCH_DATA_B12, "DB12", DATA_B12,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB12, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB12, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB12, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB12, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB12, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB12, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB12, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB12, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB13, GLITCH_DATA_B13, "DB13", DATA_B13,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB13, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB13, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB13, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB13, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB13, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB13, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB13, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB13, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB14, GLITCH_DATA_B14, "DB14", DATA_B14,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB14, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB14, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB14, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB14, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB14, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB14, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB14, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB14, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB15, GLITCH_DATA_B15, "DB15", DATA_B15,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB15, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB15, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB15, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB15, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB15, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB15, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB15, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB15, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B16, "EDB0", DATA_B16,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_EDB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_EDB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_EDB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_EDB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_EDB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_EDB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_EDB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_EDB0, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB1, GLITCH_DATA_B17, "EDB1", DATA_B17,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_EDB1, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_EDB1, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_EDB1, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_EDB1, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_EDB1, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_EDB1, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_EDB1, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_EDB1, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB256X18DAR_VITAL of RAMB256X18DAR is
   for VITAL
   end for;
end CFG_RAMB256X18DAR_VITAL;

----- CELL RAMB256X18DAR_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18DAR_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADDA0_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
--      tsetup_CE0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
--      thold_CE0_RWCLK0_noedge_posedge     :	VitalDelayType   := 0.0 ns;
--      tsetup_CE1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
--      thold_CE1_RWCLK1_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA8_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA8_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA9_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA9_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA10_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA10_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA11_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA11_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA12_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA12_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA13_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA13_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA14_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA14_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA15_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DA15_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA1_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB8_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB8_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB9_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB9_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB10_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB10_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB11_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB11_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB12_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB12_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB13_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB13_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB14_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB14_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB15_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_DB15_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB1_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;


      tpw_RWCLK0_posedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

--      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
--      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
--      CE0                            :	in    STD_ULOGIC;
--      CE1                            :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      DA8                            :	inout STD_ULOGIC;
      DA9                            :	inout STD_ULOGIC;
      DA10                           :	inout STD_ULOGIC;
      DA11                           :	inout STD_ULOGIC;
      DA12                           :	inout STD_ULOGIC;
      DA13                           :	inout STD_ULOGIC;
      DA14                           :	inout STD_ULOGIC;
      DA15                           :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      EDA1                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      DB8                            :	inout STD_ULOGIC;
      DB9                            :	inout STD_ULOGIC;
      DB10                           :	inout STD_ULOGIC;
      DB11                           :	inout STD_ULOGIC;
      DB12                           :	inout STD_ULOGIC;
      DB13                           :	inout STD_ULOGIC;
      DB14                           :	inout STD_ULOGIC;
      DB15                           :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC;
      EDB1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18DAR_1 : entity is TRUE;
end RAMB256X18DAR_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18DAR_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
--      SIGNAL CE0_ipd                 :   std_logic :='X';
--      SIGNAL CE1_ipd                 :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL DA8_ipd                 :   std_logic :='X';
      SIGNAL DA9_ipd                 :   std_logic :='X';
      SIGNAL DA10_ipd                :   std_logic :='X';
      SIGNAL DA11_ipd                :   std_logic :='X';
      SIGNAL DA12_ipd                :   std_logic :='X';
      SIGNAL DA13_ipd                :   std_logic :='X';
      SIGNAL DA14_ipd                :   std_logic :='X';
      SIGNAL DA15_ipd                :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL EDA1_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL DB8_ipd                 :   std_logic :='X';
      SIGNAL DB9_ipd                 :   std_logic :='X';
      SIGNAL DB10_ipd                :   std_logic :='X';
      SIGNAL DB11_ipd                :   std_logic :='X';
      SIGNAL DB12_ipd                :   std_logic :='X';
      SIGNAL DB13_ipd                :   std_logic :='X';
      SIGNAL DB14_ipd                :   std_logic :='X';
      SIGNAL DB15_ipd                :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';
      SIGNAL EDB1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;
      SIGNAL data_out_b              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);
      SIGNAL din_b                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
--	VitalWireDelay (CE0_ipd,      CE0,        tipd_CE0);
--	VitalWireDelay (CE1_ipd,      CE1,        tipd_CE1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (DA8_ipd,      DA8,        tipd_DA8);
	VitalWireDelay (DA9_ipd,      DA9,        tipd_DA9);
	VitalWireDelay (DA10_ipd,     DA10,       tipd_DA10);
	VitalWireDelay (DA11_ipd,     DA11,       tipd_DA11);
	VitalWireDelay (DA12_ipd,     DA12,       tipd_DA12);
	VitalWireDelay (DA13_ipd,     DA13,       tipd_DA13);
	VitalWireDelay (DA14_ipd,     DA14,       tipd_DA14);
	VitalWireDelay (DA15_ipd,     DA15,       tipd_DA15);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);
	VitalWireDelay (EDA1_ipd,     EDA1,       tipd_EDA1);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (DB8_ipd,      DB8,        tipd_DB8);
	VitalWireDelay (DB9_ipd,      DB9,        tipd_DB9);
	VitalWireDelay (DB10_ipd,     DB10,       tipd_DB10);
	VitalWireDelay (DB11_ipd,     DB11,       tipd_DB11);
	VitalWireDelay (DB12_ipd,     DB12,       tipd_DB12);
	VitalWireDelay (DB13_ipd,     DB13,       tipd_DB13);
	VitalWireDelay (DB14_ipd,     DB14,       tipd_DB14);
	VitalWireDelay (DB15_ipd,     DB15,       tipd_DB15);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
	VitalWireDelay (EDB1_ipd,     EDB1,       tipd_EDB1);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '0' and WEN0_ipd = '1') then
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '0' and WEN1_ipd = '1') then
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_8;
   end if;
   end process wrapper_read_add_b;

--   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd, CE0_ipd)
   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd)

   begin
--    if (WEN0_ipd = '0' and CE0_ipd = '0' ) then
    if (WEN0_ipd = '0') then
	wr_clk0 <= RWCLK0_ipd;
    else
	wr_clk0 <= '0';
    end if;
   end process;

--   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd, CE1_ipd)
   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd)

   begin
--    if (WEN1_ipd = '0'and CE1_ipd = '0') then
    if (WEN1_ipd = '0') then
	wr_clk1 <= RWCLK1_ipd;
    else
	wr_clk1 <= '0';
    end if;
   end process;

   write_address_a : process(
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DA15_ipd, 
                                  DA14_ipd, 
                                  DA13_ipd, 
                                  DA12_ipd, 
                                  DA11_ipd, 
                                  DA10_ipd, 
                                  DA9_ipd, 
                                  DA8_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(17) <= EDA1_ipd;
        din_a(16) <= EDA0_ipd;
        din_a(15) <= DA15_ipd;
        din_a(14) <= DA14_ipd;
        din_a(13) <= DA13_ipd;
        din_a(12) <= DA12_ipd;
        din_a(11) <= DA11_ipd;
        din_a(10) <= DA10_ipd;
        din_a(9)  <= DA9_ipd;
        din_a(8)  <= DA8_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DB15_ipd, 
                                  DB14_ipd, 
                                  DB13_ipd, 
                                  DB12_ipd, 
                                  DB11_ipd, 
                                  DB10_ipd, 
                                  DB9_ipd, 
                                  DB8_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(17) <= EDB1_ipd;
        din_b(16) <= EDB0_ipd;
        din_b(15) <= DB15_ipd;
        din_b(14) <= DB14_ipd;
        din_b(13) <= DB13_ipd;
        din_b(12) <= DB12_ipd;
        din_b(11) <= DB11_ipd;
        din_b(10) <= DB10_ipd;
        din_b(9)  <= DB9_ipd;
        din_b(8)  <= DB8_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18DAR_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_posedge   : std_ulogic  := '0';

--        variable Tviol_CE0_RWCLK0_posedge    : std_ulogic  := '0';
--        variable Tviol_CE1_RWCLK1_posedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_posedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_posedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA8_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA9_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA10_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA11_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA12_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA13_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA14_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA15_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_EDA1_RWCLK0_posedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB8_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB9_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB10_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB11_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB12_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB13_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB14_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB15_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_EDB1_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

--        variable Tmkr_CE0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
--        variable Tmkr_CE1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA8_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA9_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA10_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA11_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA12_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA13_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA14_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA15_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA1_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB8_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB9_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB10_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB11_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB12_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB13_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB14_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB15_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_posedge,
          TimingData              => Tmkr_WEN0_RWCLK0_posedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_posedge,
          TimingData              => Tmkr_WEN1_RWCLK1_posedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

--         VitalSetupHoldCheck (
--          Violation               => Tviol_CE0_RWCLK0_posedge,
--          TimingData              => Tmkr_CE0_RWCLK0_posedge,
--          TestSignal              => CE0_ipd,
--          TestSignalName          => "CE0",
--          TestDelay               => 0 ns,
--          RefSignal               => RWCLK0_ipd,
--          RefSignalName           => "RWCLK0",
--          RefDelay                => 0 ns,
--          SetupHigh               => tsetup_CE0_RWCLK0_noedge_posedge,
--          SetupLow                => tsetup_CE0_RWCLK0_noedge_posedge,
--          HoldLow                 => thold_CE0_RWCLK0_noedge_posedge,
--          HoldHigh                => thold_CE0_RWCLK0_noedge_posedge,
--          CheckEnabled            => TRUE,
--          RefTransition           => 'R',
--          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
--          Xon                     => Xon,
--          MsgOn                   => MsgOn,
--          MsgSeverity             => WARNING);

--         VitalSetupHoldCheck (
--          Violation               => Tviol_CE1_RWCLK1_posedge,
--          TimingData              => Tmkr_CE1_RWCLK1_posedge,
--          TestSignal              => CE1_ipd,
--          TestSignalName          => "CE1",
--          TestDelay               => 0 ns,
--          RefSignal               => RWCLK1_ipd,
--          RefSignalName           => "RWCLK1",
--          RefDelay                => 0 ns,
--          SetupHigh               => tsetup_CE1_RWCLK1_noedge_posedge,
--          SetupLow                => tsetup_CE1_RWCLK1_noedge_posedge,
--          HoldLow                 => thold_CE1_RWCLK1_noedge_posedge,
--          HoldHigh                => thold_CE1_RWCLK1_noedge_posedge,
--          CheckEnabled            => TRUE,
--          RefTransition           => 'R',
--          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
--          Xon                     => Xon,
--          MsgOn                   => MsgOn,
--          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_posedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_posedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_posedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_posedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_posedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_posedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_posedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_posedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_posedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_posedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_posedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_posedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_posedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_posedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_posedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_posedge,
          TimingData              => Tmkr_DA0_RWCLK0_posedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_posedge,
          TimingData              => Tmkr_DA1_RWCLK0_posedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_posedge,
          TimingData              => Tmkr_DA2_RWCLK0_posedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_posedge,
          TimingData              => Tmkr_DA3_RWCLK0_posedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_posedge,
          TimingData              => Tmkr_DA4_RWCLK0_posedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_posedge,
          TimingData              => Tmkr_DA5_RWCLK0_posedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_posedge,
          TimingData              => Tmkr_DA6_RWCLK0_posedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_posedge,
          TimingData              => Tmkr_DA7_RWCLK0_posedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA8_RWCLK0_posedge,
          TimingData              => Tmkr_DA8_RWCLK0_posedge,
          TestSignal              => DA8_ipd,
          TestSignalName          => "DA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA8_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA8_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA8_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA8_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA9_RWCLK0_posedge,
          TimingData              => Tmkr_DA9_RWCLK0_posedge,
          TestSignal              => DA9_ipd,
          TestSignalName          => "DA9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA9_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA9_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA9_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA9_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA10_RWCLK0_posedge,
          TimingData              => Tmkr_DA10_RWCLK0_posedge,
          TestSignal              => DA10_ipd,
          TestSignalName          => "DA10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA10_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA10_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA10_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA10_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA11_RWCLK0_posedge,
          TimingData              => Tmkr_DA11_RWCLK0_posedge,
          TestSignal              => DA11_ipd,
          TestSignalName          => "DA11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA11_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA11_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA11_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA11_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA12_RWCLK0_posedge,
          TimingData              => Tmkr_DA12_RWCLK0_posedge,
          TestSignal              => DA12_ipd,
          TestSignalName          => "DA12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA12_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA12_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA12_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA12_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA13_RWCLK0_posedge,
          TimingData              => Tmkr_DA13_RWCLK0_posedge,
          TestSignal              => DA13_ipd,
          TestSignalName          => "DA13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA13_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA13_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA13_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA13_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA13_RWCLK0_posedge,
          TimingData              => Tmkr_DA13_RWCLK0_posedge,
          TestSignal              => DA13_ipd,
          TestSignalName          => "DA13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA13_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA13_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA13_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA13_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA14_RWCLK0_posedge,
          TimingData              => Tmkr_DA14_RWCLK0_posedge,
          TestSignal              => DA14_ipd,
          TestSignalName          => "DA14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA14_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA14_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA14_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA14_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA15_RWCLK0_posedge,
          TimingData              => Tmkr_DA15_RWCLK0_posedge,
          TestSignal              => DA15_ipd,
          TestSignalName          => "DA15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA15_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA15_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_posedge,
          TimingData              => Tmkr_EDA0_RWCLK0_posedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA1_RWCLK0_posedge,
          TimingData              => Tmkr_EDA1_RWCLK0_posedge,
          TestSignal              => EDA1_ipd,
          TestSignalName          => "EDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_EDA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_EDA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_EDA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_posedge,
          TimingData              => Tmkr_DB0_RWCLK1_posedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_posedge,
          TimingData              => Tmkr_DB1_RWCLK1_posedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_posedge,
          TimingData              => Tmkr_DB2_RWCLK1_posedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_posedge,
          TimingData              => Tmkr_DB3_RWCLK1_posedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_posedge,
          TimingData              => Tmkr_DB4_RWCLK1_posedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_posedge,
          TimingData              => Tmkr_DB5_RWCLK1_posedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_posedge,
          TimingData              => Tmkr_DB6_RWCLK1_posedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_posedge,
          TimingData              => Tmkr_DB7_RWCLK1_posedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB8_RWCLK1_posedge,
          TimingData              => Tmkr_DB8_RWCLK1_posedge,
          TestSignal              => DB8_ipd,
          TestSignalName          => "DB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB8_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB8_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB8_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB8_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB9_RWCLK1_posedge,
          TimingData              => Tmkr_DB9_RWCLK1_posedge,
          TestSignal              => DB9_ipd,
          TestSignalName          => "DB9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB9_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB9_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB9_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB9_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB10_RWCLK1_posedge,
          TimingData              => Tmkr_DB10_RWCLK1_posedge,
          TestSignal              => DB10_ipd,
          TestSignalName          => "DB10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB10_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB10_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB10_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB10_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB11_RWCLK1_posedge,
          TimingData              => Tmkr_DB11_RWCLK1_posedge,
          TestSignal              => DB11_ipd,
          TestSignalName          => "DB11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB11_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB11_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB11_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB11_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB12_RWCLK1_posedge,
          TimingData              => Tmkr_DB12_RWCLK1_posedge,
          TestSignal              => DB12_ipd,
          TestSignalName          => "DB12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB12_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB12_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB12_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB12_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB13_RWCLK1_posedge,
          TimingData              => Tmkr_DB13_RWCLK1_posedge,
          TestSignal              => DB13_ipd,
          TestSignalName          => "DB13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB13_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB13_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB13_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB13_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB13_RWCLK1_posedge,
          TimingData              => Tmkr_DB13_RWCLK1_posedge,
          TestSignal              => DB13_ipd,
          TestSignalName          => "DB13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB13_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB13_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB13_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB13_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB14_RWCLK1_posedge,
          TimingData              => Tmkr_DB14_RWCLK1_posedge,
          TestSignal              => DB14_ipd,
          TestSignalName          => "DB14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB14_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB14_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB14_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB14_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB15_RWCLK1_posedge,
          TimingData              => Tmkr_DB15_RWCLK1_posedge,
          TestSignal              => DB15_ipd,
          TestSignalName          => "DB15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB15_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB15_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_posedge,
          TimingData              => Tmkr_EDB0_RWCLK1_posedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB1_RWCLK1_posedge,
          TimingData              => Tmkr_EDB1_RWCLK1_posedge,
          TestSignal              => EDB1_ipd,
          TestSignalName          => "EDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_EDB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_EDB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_EDB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_posedge,
          PulseWidthLow           => tpw_RWCLK0_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_posedge,
          PulseWidthLow           => tpw_RWCLK1_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '1' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '1' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10 : std_logic := 'Z';
    VARIABLE DATA_A11 : std_logic := 'Z';
    VARIABLE DATA_A12 : std_logic := 'Z';
    VARIABLE DATA_A13 : std_logic := 'Z';
    VARIABLE DATA_A14 : std_logic := 'Z';
    VARIABLE DATA_A15 : std_logic := 'Z';
    VARIABLE DATA_A16 : std_logic := 'Z';
    VARIABLE DATA_A17 : std_logic := 'Z';
    VARIABLE OE0_inverted : std_logic := 'Z';


    BEGIN

      OE0_inverted := NOT (OE0_ipd);
      con_a := VitalAND2(OE0_inverted, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10 := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11 := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12 := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13 := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14 := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15 := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16 := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17 := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA0, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA1, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA1, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA1, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA1, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA1, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA1, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA1, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA1, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA2, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA2, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA2, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA2, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA2, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA2, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA2, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA2, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA3, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA3, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA3, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA3, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA3, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA3, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA3, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA3, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA4, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA4, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA4, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA4, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA4, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA4, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA4, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA4, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA5, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA5, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA5, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA5, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA5, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA5, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA5, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA5, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA6, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA6, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA6, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA6, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA6, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA6, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA6, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA6, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA7, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA7, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA7, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA7, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA7, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA7, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA7, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA7, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA8, GLITCH_DATA_A8, "DA8", DATA_A8,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA8, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA8, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA8, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA8, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA8, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA8, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA8, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA8, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA9, GLITCH_DATA_A9, "DA9", DATA_A9,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA9, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA9, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA9, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA9, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA9, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA9, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA9, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA9, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA10, GLITCH_DATA_A10, "DA10", DATA_A10,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA10, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA10, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA10, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA10, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA10, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA10, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA10, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA10, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA11, GLITCH_DATA_A11, "DA11", DATA_A11,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA11, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA11, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA11, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA11, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA11, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA11, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA11, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA11, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA12, GLITCH_DATA_A12, "DA12", DATA_A12,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA12, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA12, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA12, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA12, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA12, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA12, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA12, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA12, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA13, GLITCH_DATA_A13, "DA13", DATA_A13,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA13, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA13, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA13, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA13, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA13, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA13, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA13, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA13, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA14, GLITCH_DATA_A14, "DA14", DATA_A14,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA14, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA14, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA14, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA14, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA14, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA14, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA14, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA14, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA15, GLITCH_DATA_A15, "DA15", DATA_A15,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA15, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA15, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA15, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA15, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA15, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA15, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA15, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA15, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A16, "EDA0", DATA_A16,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_EDA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_EDA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_EDA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_EDA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_EDA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_EDA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_EDA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_EDA0, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA1, GLITCH_DATA_A17, "EDA1", DATA_A17,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_EDA1, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_EDA1, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_EDA1, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_EDA1, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_EDA1, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_EDA1, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_EDA1, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_EDA1, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B17 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';
    VARIABLE DATA_B9  : std_logic := 'Z';
    VARIABLE DATA_B10 : std_logic := 'Z';
    VARIABLE DATA_B11 : std_logic := 'Z';
    VARIABLE DATA_B12 : std_logic := 'Z';
    VARIABLE DATA_B13 : std_logic := 'Z';
    VARIABLE DATA_B14 : std_logic := 'Z';
    VARIABLE DATA_B15 : std_logic := 'Z';
    VARIABLE DATA_B16 : std_logic := 'Z';
    VARIABLE DATA_B17 : std_logic := 'Z';
    VARIABLE OE1_inverted : std_logic := 'Z';


    BEGIN

      OE1_inverted := NOT (OE1_ipd);
      con_b := VitalAND2(OE1_inverted, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);
      DATA_B9  := VITALBUFIF1(data_out_b(9),con_b);
      DATA_B10 := VITALBUFIF1(data_out_b(10),con_b);
      DATA_B11 := VITALBUFIF1(data_out_b(11),con_b);
      DATA_B12 := VITALBUFIF1(data_out_b(12),con_b);
      DATA_B13 := VITALBUFIF1(data_out_b(13),con_b);
      DATA_B14 := VITALBUFIF1(data_out_b(14),con_b);
      DATA_B15 := VITALBUFIF1(data_out_b(15),con_b);
      DATA_B16 := VITALBUFIF1(data_out_b(16),con_b);
      DATA_B17 := VITALBUFIF1(data_out_b(17),con_b);


      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB0, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB1, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB1, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB1, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB1, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB1, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB1, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB1, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB1, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB2, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB2, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB2, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB2, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB2, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB2, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB2, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB2, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB3, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB3, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB3, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB3, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB3, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB3, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB3, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB3, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB4, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB4, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB4, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB4, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB4, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB4, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB4, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB4, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB5, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB5, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB5, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB5, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB5, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB5, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB5, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB5, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB6, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB6, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB6, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB6, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB6, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB6, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB6, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB6, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB7, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB7, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB7, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB7, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB7, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB7, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB7, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB7, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB8, GLITCH_DATA_B8, "DB8", DATA_B8,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB8, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB8, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB8, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB8, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB8, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB8, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB8, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB8, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB9, GLITCH_DATA_B9, "DB9", DATA_B9,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB9, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB9, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB9, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB9, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB9, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB9, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB9, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB9, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB10, GLITCH_DATA_B10, "DB10", DATA_B10,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB10, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB10, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB10, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB10, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB10, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB10, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB10, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB10, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB11, GLITCH_DATA_B11, "DB11", DATA_B11,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB11, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB11, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB11, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB11, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB11, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB11, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB11, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB11, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB12, GLITCH_DATA_B12, "DB12", DATA_B12,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB12, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB12, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB12, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB12, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB12, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB12, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB12, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB12, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB13, GLITCH_DATA_B13, "DB13", DATA_B13,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB13, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB13, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB13, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB13, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB13, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB13, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB13, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB13, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB14, GLITCH_DATA_B14, "DB14", DATA_B14,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB14, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB14, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB14, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB14, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB14, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB14, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB14, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB14, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB15, GLITCH_DATA_B15, "DB15", DATA_B15,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB15, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB15, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB15, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB15, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB15, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB15, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB15, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB15, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B16, "EDB0", DATA_B16,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_EDB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_EDB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_EDB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_EDB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_EDB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_EDB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_EDB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_EDB0, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB1, GLITCH_DATA_B17, "EDB1", DATA_B17,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_EDB1, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_EDB1, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_EDB1, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_EDB1, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_EDB1, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_EDB1, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_EDB1, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_EDB1, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB256X18DAR_1_VITAL of RAMB256X18DAR_1 is
   for VITAL
   end for;
end CFG_RAMB256X18DAR_1_VITAL;

----- CELL RAMB256X18DAF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18DAF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADDA0_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
--      tsetup_CE0_RWCLK0_noedge_negedge    :	VitalDelayType   := 0.0 ns;
--      thold_CE0_RWCLK0_noedge_negedge     :	VitalDelayType   := 0.0 ns;
--      tsetup_CE1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
--      thold_CE1_RWCLK1_noedge_negedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA8_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA8_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA9_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA9_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA10_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA10_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA11_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA11_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA12_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA12_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA13_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA13_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA14_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA14_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA15_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA15_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA1_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB8_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB8_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB9_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB9_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB10_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB10_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB11_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB11_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB12_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB12_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB13_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB13_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB14_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB14_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB15_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB15_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB1_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;


      tpw_RWCLK0_posedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

--      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
--      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
--      CE0                            :	in    STD_ULOGIC;
--      CE1                            :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      DA8                            :	inout STD_ULOGIC;
      DA9                            :	inout STD_ULOGIC;
      DA10                           :	inout STD_ULOGIC;
      DA11                           :	inout STD_ULOGIC;
      DA12                           :	inout STD_ULOGIC;
      DA13                           :	inout STD_ULOGIC;
      DA14                           :	inout STD_ULOGIC;
      DA15                           :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      EDA1                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      DB8                            :	inout STD_ULOGIC;
      DB9                            :	inout STD_ULOGIC;
      DB10                           :	inout STD_ULOGIC;
      DB11                           :	inout STD_ULOGIC;
      DB12                           :	inout STD_ULOGIC;
      DB13                           :	inout STD_ULOGIC;
      DB14                           :	inout STD_ULOGIC;
      DB15                           :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC;
      EDB1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18DAF : entity is TRUE;
end RAMB256X18DAF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18DAF is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
--      SIGNAL CE0_ipd                 :   std_logic :='X';
--      SIGNAL CE1_ipd                 :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL DA8_ipd                 :   std_logic :='X';
      SIGNAL DA9_ipd                 :   std_logic :='X';
      SIGNAL DA10_ipd                :   std_logic :='X';
      SIGNAL DA11_ipd                :   std_logic :='X';
      SIGNAL DA12_ipd                :   std_logic :='X';
      SIGNAL DA13_ipd                :   std_logic :='X';
      SIGNAL DA14_ipd                :   std_logic :='X';
      SIGNAL DA15_ipd                :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL EDA1_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL DB8_ipd                 :   std_logic :='X';
      SIGNAL DB9_ipd                 :   std_logic :='X';
      SIGNAL DB10_ipd                :   std_logic :='X';
      SIGNAL DB11_ipd                :   std_logic :='X';
      SIGNAL DB12_ipd                :   std_logic :='X';
      SIGNAL DB13_ipd                :   std_logic :='X';
      SIGNAL DB14_ipd                :   std_logic :='X';
      SIGNAL DB15_ipd                :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';
      SIGNAL EDB1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;
      SIGNAL data_out_b              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);
      SIGNAL din_b                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
--	VitalWireDelay (CE0_ipd,      CE0,        tipd_CE0);
--	VitalWireDelay (CE1_ipd,      CE1,        tipd_CE1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (DA8_ipd,      DA8,        tipd_DA8);
	VitalWireDelay (DA9_ipd,      DA9,        tipd_DA9);
	VitalWireDelay (DA10_ipd,     DA10,       tipd_DA10);
	VitalWireDelay (DA11_ipd,     DA11,       tipd_DA11);
	VitalWireDelay (DA12_ipd,     DA12,       tipd_DA12);
	VitalWireDelay (DA13_ipd,     DA13,       tipd_DA13);
	VitalWireDelay (DA14_ipd,     DA14,       tipd_DA14);
	VitalWireDelay (DA15_ipd,     DA15,       tipd_DA15);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);
	VitalWireDelay (EDA1_ipd,     EDA1,       tipd_EDA1);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (DB8_ipd,      DB8,        tipd_DB8);
	VitalWireDelay (DB9_ipd,      DB9,        tipd_DB9);
	VitalWireDelay (DB10_ipd,     DB10,       tipd_DB10);
	VitalWireDelay (DB11_ipd,     DB11,       tipd_DB11);
	VitalWireDelay (DB12_ipd,     DB12,       tipd_DB12);
	VitalWireDelay (DB13_ipd,     DB13,       tipd_DB13);
	VitalWireDelay (DB14_ipd,     DB14,       tipd_DB14);
	VitalWireDelay (DB15_ipd,     DB15,       tipd_DB15);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
	VitalWireDelay (EDB1_ipd,     EDB1,       tipd_EDB1);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '1' and WEN0_ipd = '1') then
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '1' and WEN1_ipd = '1') then
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_8;
   end if;
   end process wrapper_read_add_b;

--   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd, CE0_ipd)
   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd)

   begin
--    if (WEN0_ipd = '0' and CE0_ipd = '0' ) then
    if (WEN0_ipd = '0') then
	wr_clk0 <= RWCLK0_ipd;
    else
	wr_clk0 <= '1';
    end if;
   end process;

--   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd, CE1_ipd)
   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd)

   begin
--    if (WEN1_ipd = '0'and CE1_ipd = '0') then
    if (WEN1_ipd = '0') then
	wr_clk1 <= RWCLK1_ipd;
    else
	wr_clk1 <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DA15_ipd, 
                                  DA14_ipd, 
                                  DA13_ipd, 
                                  DA12_ipd, 
                                  DA11_ipd, 
                                  DA10_ipd, 
                                  DA9_ipd, 
                                  DA8_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(17) <= EDA1_ipd;
        din_a(16) <= EDA0_ipd;
        din_a(15) <= DA15_ipd;
        din_a(14) <= DA14_ipd;
        din_a(13) <= DA13_ipd;
        din_a(12) <= DA12_ipd;
        din_a(11) <= DA11_ipd;
        din_a(10) <= DA10_ipd;
        din_a(9)  <= DA9_ipd;
        din_a(8)  <= DA8_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DB15_ipd, 
                                  DB14_ipd, 
                                  DB13_ipd, 
                                  DB12_ipd, 
                                  DB11_ipd, 
                                  DB10_ipd, 
                                  DB9_ipd, 
                                  DB8_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(17) <= EDB1_ipd;
        din_b(16) <= EDB0_ipd;
        din_b(15) <= DB15_ipd;
        din_b(14) <= DB14_ipd;
        din_b(13) <= DB13_ipd;
        din_b(12) <= DB12_ipd;
        din_b(11) <= DB11_ipd;
        din_b(10) <= DB10_ipd;
        din_b(9)  <= DB9_ipd;
        din_b(8)  <= DB8_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18DAF Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_posedge   : std_ulogic  := '0';

--        variable Tviol_CE0_RWCLK0_posedge    : std_ulogic  := '0';
--        variable Tviol_CE1_RWCLK1_posedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_posedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_posedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA8_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA9_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA10_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA11_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA12_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA13_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA14_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA15_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_EDA1_RWCLK0_posedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB8_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB9_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB10_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB11_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB12_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB13_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB14_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB15_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_EDB1_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

--        variable Tmkr_CE0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
--        variable Tmkr_CE1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA8_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA9_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA10_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA11_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA12_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA13_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA14_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA15_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA1_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB8_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB9_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB10_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB11_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB12_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB13_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB14_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB15_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_posedge,
          TimingData              => Tmkr_WEN0_RWCLK0_posedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_posedge,
          TimingData              => Tmkr_WEN1_RWCLK1_posedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

--         VitalSetupHoldCheck (
--          Violation               => Tviol_CE0_RWCLK0_posedge,
--          TimingData              => Tmkr_CE0_RWCLK0_posedge,
--          TestSignal              => CE0_ipd,
--          TestSignalName          => "CE0",
--          TestDelay               => 0 ns,
--          RefSignal               => RWCLK0_ipd,
--          RefSignalName           => "RWCLK0",
--          RefDelay                => 0 ns,
--          SetupHigh               => tsetup_CE0_RWCLK0_noedge_negedge,
--          SetupLow                => tsetup_CE0_RWCLK0_noedge_negedge,
--          HoldLow                 => thold_CE0_RWCLK0_noedge_negedge,
--          HoldHigh                => thold_CE0_RWCLK0_noedge_negedge,
--          CheckEnabled            => TRUE,
--          RefTransition           => 'F',
--          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
--          Xon                     => Xon,
--          MsgOn                   => MsgOn,
--          MsgSeverity             => WARNING);

--         VitalSetupHoldCheck (
--          Violation               => Tviol_CE1_RWCLK1_posedge,
--          TimingData              => Tmkr_CE1_RWCLK1_posedge,
--          TestSignal              => CE1_ipd,
--          TestSignalName          => "CE1",
--          TestDelay               => 0 ns,
--          RefSignal               => RWCLK1_ipd,
--          RefSignalName           => "RWCLK1",
--          RefDelay                => 0 ns,
--          SetupHigh               => tsetup_CE1_RWCLK1_noedge_negedge,
--          SetupLow                => tsetup_CE1_RWCLK1_noedge_negedge,
--          HoldLow                 => thold_CE1_RWCLK1_noedge_negedge,
--          HoldHigh                => thold_CE1_RWCLK1_noedge_negedge,
--          CheckEnabled            => TRUE,
--          RefTransition           => 'F',
--          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
--          Xon                     => Xon,
--          MsgOn                   => MsgOn,
--          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_posedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_posedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_posedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_posedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_posedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_posedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_posedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_posedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_posedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_posedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_posedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_posedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_posedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_posedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_posedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_posedge,
          TimingData              => Tmkr_DA0_RWCLK0_posedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_posedge,
          TimingData              => Tmkr_DA1_RWCLK0_posedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_posedge,
          TimingData              => Tmkr_DA2_RWCLK0_posedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_posedge,
          TimingData              => Tmkr_DA3_RWCLK0_posedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_posedge,
          TimingData              => Tmkr_DA4_RWCLK0_posedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_posedge,
          TimingData              => Tmkr_DA5_RWCLK0_posedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_posedge,
          TimingData              => Tmkr_DA6_RWCLK0_posedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_posedge,
          TimingData              => Tmkr_DA7_RWCLK0_posedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA8_RWCLK0_posedge,
          TimingData              => Tmkr_DA8_RWCLK0_posedge,
          TestSignal              => DA8_ipd,
          TestSignalName          => "DA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA8_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA8_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA8_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA8_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA9_RWCLK0_posedge,
          TimingData              => Tmkr_DA9_RWCLK0_posedge,
          TestSignal              => DA9_ipd,
          TestSignalName          => "DA9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA9_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA9_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA9_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA9_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA10_RWCLK0_posedge,
          TimingData              => Tmkr_DA10_RWCLK0_posedge,
          TestSignal              => DA10_ipd,
          TestSignalName          => "DA10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA10_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA10_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA10_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA10_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA11_RWCLK0_posedge,
          TimingData              => Tmkr_DA11_RWCLK0_posedge,
          TestSignal              => DA11_ipd,
          TestSignalName          => "DA11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA11_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA11_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA11_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA11_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA12_RWCLK0_posedge,
          TimingData              => Tmkr_DA12_RWCLK0_posedge,
          TestSignal              => DA12_ipd,
          TestSignalName          => "DA12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA12_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA12_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA12_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA12_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA13_RWCLK0_posedge,
          TimingData              => Tmkr_DA13_RWCLK0_posedge,
          TestSignal              => DA13_ipd,
          TestSignalName          => "DA13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA13_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA13_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA13_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA13_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA13_RWCLK0_posedge,
          TimingData              => Tmkr_DA13_RWCLK0_posedge,
          TestSignal              => DA13_ipd,
          TestSignalName          => "DA13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA13_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA13_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA13_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA13_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA14_RWCLK0_posedge,
          TimingData              => Tmkr_DA14_RWCLK0_posedge,
          TestSignal              => DA14_ipd,
          TestSignalName          => "DA14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA14_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA14_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA14_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA14_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA15_RWCLK0_posedge,
          TimingData              => Tmkr_DA15_RWCLK0_posedge,
          TestSignal              => DA15_ipd,
          TestSignalName          => "DA15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA15_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA15_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_posedge,
          TimingData              => Tmkr_EDA0_RWCLK0_posedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA1_RWCLK0_posedge,
          TimingData              => Tmkr_EDA1_RWCLK0_posedge,
          TestSignal              => EDA1_ipd,
          TestSignalName          => "EDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_EDA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_EDA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_EDA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_posedge,
          TimingData              => Tmkr_DB0_RWCLK1_posedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_posedge,
          TimingData              => Tmkr_DB1_RWCLK1_posedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_posedge,
          TimingData              => Tmkr_DB2_RWCLK1_posedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_posedge,
          TimingData              => Tmkr_DB3_RWCLK1_posedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_posedge,
          TimingData              => Tmkr_DB4_RWCLK1_posedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_posedge,
          TimingData              => Tmkr_DB5_RWCLK1_posedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_posedge,
          TimingData              => Tmkr_DB6_RWCLK1_posedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_posedge,
          TimingData              => Tmkr_DB7_RWCLK1_posedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB8_RWCLK1_posedge,
          TimingData              => Tmkr_DB8_RWCLK1_posedge,
          TestSignal              => DB8_ipd,
          TestSignalName          => "DB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB8_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB8_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB8_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB8_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB9_RWCLK1_posedge,
          TimingData              => Tmkr_DB9_RWCLK1_posedge,
          TestSignal              => DB9_ipd,
          TestSignalName          => "DB9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB9_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB9_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB9_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB9_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB10_RWCLK1_posedge,
          TimingData              => Tmkr_DB10_RWCLK1_posedge,
          TestSignal              => DB10_ipd,
          TestSignalName          => "DB10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB10_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB10_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB10_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB10_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB11_RWCLK1_posedge,
          TimingData              => Tmkr_DB11_RWCLK1_posedge,
          TestSignal              => DB11_ipd,
          TestSignalName          => "DB11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB11_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB11_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB11_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB11_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB12_RWCLK1_posedge,
          TimingData              => Tmkr_DB12_RWCLK1_posedge,
          TestSignal              => DB12_ipd,
          TestSignalName          => "DB12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB12_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB12_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB12_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB12_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB13_RWCLK1_posedge,
          TimingData              => Tmkr_DB13_RWCLK1_posedge,
          TestSignal              => DB13_ipd,
          TestSignalName          => "DB13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB13_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB13_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB13_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB13_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB13_RWCLK1_posedge,
          TimingData              => Tmkr_DB13_RWCLK1_posedge,
          TestSignal              => DB13_ipd,
          TestSignalName          => "DB13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB13_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB13_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB13_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB13_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB14_RWCLK1_posedge,
          TimingData              => Tmkr_DB14_RWCLK1_posedge,
          TestSignal              => DB14_ipd,
          TestSignalName          => "DB14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB14_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB14_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB14_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB14_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB15_RWCLK1_posedge,
          TimingData              => Tmkr_DB15_RWCLK1_posedge,
          TestSignal              => DB15_ipd,
          TestSignalName          => "DB15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB15_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB15_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_posedge,
          TimingData              => Tmkr_EDB0_RWCLK1_posedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB1_RWCLK1_posedge,
          TimingData              => Tmkr_EDB1_RWCLK1_posedge,
          TestSignal              => EDB1_ipd,
          TestSignalName          => "EDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_EDB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_EDB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_EDB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_posedge,
          PulseWidthLow           => tpw_RWCLK0_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_posedge,
          PulseWidthLow           => tpw_RWCLK1_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '0' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '0' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10 : std_logic := 'Z';
    VARIABLE DATA_A11 : std_logic := 'Z';
    VARIABLE DATA_A12 : std_logic := 'Z';
    VARIABLE DATA_A13 : std_logic := 'Z';
    VARIABLE DATA_A14 : std_logic := 'Z';
    VARIABLE DATA_A15 : std_logic := 'Z';
    VARIABLE DATA_A16 : std_logic := 'Z';
    VARIABLE DATA_A17 : std_logic := 'Z';


    BEGIN

      con_a := VitalAND2(OE0_ipd, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10 := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11 := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12 := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13 := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14 := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15 := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16 := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17 := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA0, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA1, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA1, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA1, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA1, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA1, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA1, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA1, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA1, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA2, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA2, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA2, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA2, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA2, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA2, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA2, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA2, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA3, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA3, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA3, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA3, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA3, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA3, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA3, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA3, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA4, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA4, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA4, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA4, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA4, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA4, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA4, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA4, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA5, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA5, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA5, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA5, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA5, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA5, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA5, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA5, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA6, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA6, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA6, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA6, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA6, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA6, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA6, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA6, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA7, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA7, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA7, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA7, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA7, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA7, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA7, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA7, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA8, GLITCH_DATA_A8, "DA8", DATA_A8,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA8, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA8, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA8, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA8, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA8, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA8, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA8, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA8, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA9, GLITCH_DATA_A9, "DA9", DATA_A9,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA9, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA9, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA9, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA9, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA9, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA9, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA9, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA9, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA10, GLITCH_DATA_A10, "DA10", DATA_A10,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA10, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA10, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA10, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA10, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA10, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA10, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA10, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA10, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA11, GLITCH_DATA_A11, "DA11", DATA_A11,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA11, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA11, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA11, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA11, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA11, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA11, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA11, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA11, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA12, GLITCH_DATA_A12, "DA12", DATA_A12,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA12, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA12, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA12, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA12, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA12, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA12, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA12, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA12, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA13, GLITCH_DATA_A13, "DA13", DATA_A13,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA13, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA13, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA13, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA13, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA13, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA13, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA13, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA13, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA14, GLITCH_DATA_A14, "DA14", DATA_A14,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA14, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA14, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA14, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA14, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA14, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA14, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA14, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA14, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA15, GLITCH_DATA_A15, "DA15", DATA_A15,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA15, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA15, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA15, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA15, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA15, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA15, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA15, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA15, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A16, "EDA0", DATA_A16,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_EDA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_EDA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_EDA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_EDA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_EDA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_EDA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_EDA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_EDA0, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA1, GLITCH_DATA_A17, "EDA1", DATA_A17,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_EDA1, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_EDA1, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_EDA1, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_EDA1, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_EDA1, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_EDA1, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_EDA1, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_EDA1, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B17 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';
    VARIABLE DATA_B9  : std_logic := 'Z';
    VARIABLE DATA_B10 : std_logic := 'Z';
    VARIABLE DATA_B11 : std_logic := 'Z';
    VARIABLE DATA_B12 : std_logic := 'Z';
    VARIABLE DATA_B13 : std_logic := 'Z';
    VARIABLE DATA_B14 : std_logic := 'Z';
    VARIABLE DATA_B15 : std_logic := 'Z';
    VARIABLE DATA_B16 : std_logic := 'Z';
    VARIABLE DATA_B17 : std_logic := 'Z';


    BEGIN

      con_b := VitalAND2(OE1_ipd, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);
      DATA_B9  := VITALBUFIF1(data_out_b(9),con_b);
      DATA_B10 := VITALBUFIF1(data_out_b(10),con_b);
      DATA_B11 := VITALBUFIF1(data_out_b(11),con_b);
      DATA_B12 := VITALBUFIF1(data_out_b(12),con_b);
      DATA_B13 := VITALBUFIF1(data_out_b(13),con_b);
      DATA_B14 := VITALBUFIF1(data_out_b(14),con_b);
      DATA_B15 := VITALBUFIF1(data_out_b(15),con_b);
      DATA_B16 := VITALBUFIF1(data_out_b(16),con_b);
      DATA_B17 := VITALBUFIF1(data_out_b(17),con_b);


      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB0, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB1, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB1, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB1, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB1, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB1, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB1, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB1, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB1, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB2, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB2, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB2, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB2, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB2, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB2, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB2, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB2, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB3, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB3, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB3, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB3, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB3, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB3, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB3, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB3, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB4, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB4, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB4, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB4, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB4, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB4, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB4, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB4, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB5, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB5, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB5, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB5, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB5, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB5, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB5, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB5, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB6, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB6, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB6, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB6, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB6, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB6, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB6, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB6, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB7, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB7, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB7, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB7, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB7, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB7, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB7, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB7, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB8, GLITCH_DATA_B8, "DB8", DATA_B8,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB8, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB8, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB8, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB8, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB8, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB8, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB8, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB8, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB9, GLITCH_DATA_B9, "DB9", DATA_B9,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB9, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB9, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB9, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB9, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB9, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB9, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB9, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB9, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB10, GLITCH_DATA_B10, "DB10", DATA_B10,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB10, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB10, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB10, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB10, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB10, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB10, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB10, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB10, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB11, GLITCH_DATA_B11, "DB11", DATA_B11,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB11, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB11, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB11, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB11, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB11, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB11, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB11, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB11, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB12, GLITCH_DATA_B12, "DB12", DATA_B12,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB12, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB12, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB12, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB12, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB12, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB12, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB12, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB12, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB13, GLITCH_DATA_B13, "DB13", DATA_B13,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB13, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB13, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB13, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB13, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB13, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB13, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB13, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB13, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB14, GLITCH_DATA_B14, "DB14", DATA_B14,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB14, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB14, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB14, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB14, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB14, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB14, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB14, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB14, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB15, GLITCH_DATA_B15, "DB15", DATA_B15,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB15, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB15, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB15, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB15, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB15, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB15, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB15, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB15, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B16, "EDB0", DATA_B16,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_EDB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_EDB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_EDB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_EDB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_EDB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_EDB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_EDB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_EDB0, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB1, GLITCH_DATA_B17, "EDB1", DATA_B17,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_EDB1, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_EDB1, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_EDB1, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_EDB1, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_EDB1, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_EDB1, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_EDB1, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_EDB1, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB256X18DAF_VITAL of RAMB256X18DAF is
   for VITAL
   end for;
end CFG_RAMB256X18DAF_VITAL;

----- CELL RAMB256X18DAF_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18DAF_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADDA0_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_EDA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_EDB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
--      tsetup_CE0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
--      thold_CE0_RWCLK0_noedge_negedge     :	VitalDelayType   := 0.0 ns;
--      tsetup_CE1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
--      thold_CE1_RWCLK1_noedge_negedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA8_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA8_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA9_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA9_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA10_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA10_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA11_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA11_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA12_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA12_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA13_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA13_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA14_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA14_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DA15_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DA15_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDA1_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB8_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB8_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB9_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB9_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB10_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB10_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB11_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB11_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB12_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB12_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB13_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB13_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB14_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB14_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_DB15_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_DB15_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      tsetup_EDB1_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;


      tpw_RWCLK0_posedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

--      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
--      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
--      CE0                            :	in    STD_ULOGIC;
--      CE1                            :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      DA8                            :	inout STD_ULOGIC;
      DA9                            :	inout STD_ULOGIC;
      DA10                           :	inout STD_ULOGIC;
      DA11                           :	inout STD_ULOGIC;
      DA12                           :	inout STD_ULOGIC;
      DA13                           :	inout STD_ULOGIC;
      DA14                           :	inout STD_ULOGIC;
      DA15                           :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      EDA1                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      DB8                            :	inout STD_ULOGIC;
      DB9                            :	inout STD_ULOGIC;
      DB10                           :	inout STD_ULOGIC;
      DB11                           :	inout STD_ULOGIC;
      DB12                           :	inout STD_ULOGIC;
      DB13                           :	inout STD_ULOGIC;
      DB14                           :	inout STD_ULOGIC;
      DB15                           :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC;
      EDB1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18DAF_1 : entity is TRUE;
end RAMB256X18DAF_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18DAF_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
--      SIGNAL CE0_ipd                 :   std_logic :='X';
--      SIGNAL CE1_ipd                 :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL DA8_ipd                 :   std_logic :='X';
      SIGNAL DA9_ipd                 :   std_logic :='X';
      SIGNAL DA10_ipd                :   std_logic :='X';
      SIGNAL DA11_ipd                :   std_logic :='X';
      SIGNAL DA12_ipd                :   std_logic :='X';
      SIGNAL DA13_ipd                :   std_logic :='X';
      SIGNAL DA14_ipd                :   std_logic :='X';
      SIGNAL DA15_ipd                :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL EDA1_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL DB8_ipd                 :   std_logic :='X';
      SIGNAL DB9_ipd                 :   std_logic :='X';
      SIGNAL DB10_ipd                :   std_logic :='X';
      SIGNAL DB11_ipd                :   std_logic :='X';
      SIGNAL DB12_ipd                :   std_logic :='X';
      SIGNAL DB13_ipd                :   std_logic :='X';
      SIGNAL DB14_ipd                :   std_logic :='X';
      SIGNAL DB15_ipd                :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';
      SIGNAL EDB1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;
      SIGNAL data_out_b              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);
      SIGNAL din_b                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
--	VitalWireDelay (CE0_ipd,      CE0,        tipd_CE0);
--	VitalWireDelay (CE1_ipd,      CE1,        tipd_CE1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (DA8_ipd,      DA8,        tipd_DA8);
	VitalWireDelay (DA9_ipd,      DA9,        tipd_DA9);
	VitalWireDelay (DA10_ipd,     DA10,       tipd_DA10);
	VitalWireDelay (DA11_ipd,     DA11,       tipd_DA11);
	VitalWireDelay (DA12_ipd,     DA12,       tipd_DA12);
	VitalWireDelay (DA13_ipd,     DA13,       tipd_DA13);
	VitalWireDelay (DA14_ipd,     DA14,       tipd_DA14);
	VitalWireDelay (DA15_ipd,     DA15,       tipd_DA15);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);
	VitalWireDelay (EDA1_ipd,     EDA1,       tipd_EDA1);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (DB8_ipd,      DB8,        tipd_DB8);
	VitalWireDelay (DB9_ipd,      DB9,        tipd_DB9);
	VitalWireDelay (DB10_ipd,     DB10,       tipd_DB10);
	VitalWireDelay (DB11_ipd,     DB11,       tipd_DB11);
	VitalWireDelay (DB12_ipd,     DB12,       tipd_DB12);
	VitalWireDelay (DB13_ipd,     DB13,       tipd_DB13);
	VitalWireDelay (DB14_ipd,     DB14,       tipd_DB14);
	VitalWireDelay (DB15_ipd,     DB15,       tipd_DB15);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
	VitalWireDelay (EDB1_ipd,     EDB1,       tipd_EDB1);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '0' and WEN0_ipd = '1') then
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '0' and WEN1_ipd = '1') then
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_8;
   end if;
   end process wrapper_read_add_b;

--   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd, CE0_ipd)
   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd)

   begin
--    if (WEN0_ipd = '0' and CE0_ipd = '0' ) then
    if (WEN0_ipd = '0') then
	wr_clk0 <= RWCLK0_ipd;
    else
	wr_clk0 <= '1';
    end if;
   end process;

--   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd, CE1_ipd)
   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd)

   begin
--    if (WEN1_ipd = '0'and CE1_ipd = '0') then
    if (WEN1_ipd = '0') then
	wr_clk1 <= RWCLK1_ipd;
    else
	wr_clk1 <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DA15_ipd, 
                                  DA14_ipd, 
                                  DA13_ipd, 
                                  DA12_ipd, 
                                  DA11_ipd, 
                                  DA10_ipd, 
                                  DA9_ipd, 
                                  DA8_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(17) <= EDA1_ipd;
        din_a(16) <= EDA0_ipd;
        din_a(15) <= DA15_ipd;
        din_a(14) <= DA14_ipd;
        din_a(13) <= DA13_ipd;
        din_a(12) <= DA12_ipd;
        din_a(11) <= DA11_ipd;
        din_a(10) <= DA10_ipd;
        din_a(9)  <= DA9_ipd;
        din_a(8)  <= DA8_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA1_ipd, 
                                  EDA0_ipd, 
                                  DB15_ipd, 
                                  DB14_ipd, 
                                  DB13_ipd, 
                                  DB12_ipd, 
                                  DB11_ipd, 
                                  DB10_ipd, 
                                  DB9_ipd, 
                                  DB8_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(17) <= EDB1_ipd;
        din_b(16) <= EDB0_ipd;
        din_b(15) <= DB15_ipd;
        din_b(14) <= DB14_ipd;
        din_b(13) <= DB13_ipd;
        din_b(12) <= DB12_ipd;
        din_b(11) <= DB11_ipd;
        din_b(10) <= DB10_ipd;
        din_b(9)  <= DB9_ipd;
        din_b(8)  <= DB8_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18DAF_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_posedge   : std_ulogic  := '0';

--        variable Tviol_CE0_RWCLK0_posedge    : std_ulogic  := '0';
--        variable Tviol_CE1_RWCLK1_posedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_posedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_posedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA8_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA9_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA10_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA11_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA12_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA13_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA14_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_DA15_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_EDA1_RWCLK0_posedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB8_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB9_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB10_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB11_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB12_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB13_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB14_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_DB15_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_posedge   : std_ulogic  := '0';
        variable Tviol_EDB1_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

--        variable Tmkr_CE0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
--        variable Tmkr_CE1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA8_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA9_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA10_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA11_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA12_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA13_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA14_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA15_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA1_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB8_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB9_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB10_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB11_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB12_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB13_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB14_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB15_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_posedge,
          TimingData              => Tmkr_WEN0_RWCLK0_posedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_posedge,
          TimingData              => Tmkr_WEN1_RWCLK1_posedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

--         VitalSetupHoldCheck (
--          Violation               => Tviol_CE0_RWCLK0_posedge,
--          TimingData              => Tmkr_CE0_RWCLK0_posedge,
--          TestSignal              => CE0_ipd,
--          TestSignalName          => "CE0",
--          TestDelay               => 0 ns,
--          RefSignal               => RWCLK0_ipd,
--          RefSignalName           => "RWCLK0",
--          RefDelay                => 0 ns,
--          SetupHigh               => tsetup_CE0_RWCLK0_noedge_negedge,
--          SetupLow                => tsetup_CE0_RWCLK0_noedge_negedge,
--          HoldLow                 => thold_CE0_RWCLK0_noedge_negedge,
--          HoldHigh                => thold_CE0_RWCLK0_noedge_negedge,
--          CheckEnabled            => TRUE,
--          RefTransition           => 'F',
--          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
--          Xon                     => Xon,
--          MsgOn                   => MsgOn,
--          MsgSeverity             => WARNING);

--         VitalSetupHoldCheck (
--          Violation               => Tviol_CE1_RWCLK1_posedge,
--          TimingData              => Tmkr_CE1_RWCLK1_posedge,
--          TestSignal              => CE1_ipd,
--          TestSignalName          => "CE1",
--          TestDelay               => 0 ns,
--          RefSignal               => RWCLK1_ipd,
--          RefSignalName           => "RWCLK1",
--          RefDelay                => 0 ns,
--          SetupHigh               => tsetup_CE1_RWCLK1_noedge_negedge,
--          SetupLow                => tsetup_CE1_RWCLK1_noedge_negedge,
--          HoldLow                 => thold_CE1_RWCLK1_noedge_negedge,
--          HoldHigh                => thold_CE1_RWCLK1_noedge_negedge,
--          CheckEnabled            => TRUE,
--          RefTransition           => 'F',
--          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
--          Xon                     => Xon,
--          MsgOn                   => MsgOn,
--          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_posedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_posedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_posedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_posedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_posedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_posedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_posedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_posedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_posedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_posedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_posedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_posedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_posedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_posedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_posedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_posedge,
          TimingData              => Tmkr_DA0_RWCLK0_posedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_posedge,
          TimingData              => Tmkr_DA1_RWCLK0_posedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_posedge,
          TimingData              => Tmkr_DA2_RWCLK0_posedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_posedge,
          TimingData              => Tmkr_DA3_RWCLK0_posedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_posedge,
          TimingData              => Tmkr_DA4_RWCLK0_posedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_posedge,
          TimingData              => Tmkr_DA5_RWCLK0_posedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_posedge,
          TimingData              => Tmkr_DA6_RWCLK0_posedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_posedge,
          TimingData              => Tmkr_DA7_RWCLK0_posedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA8_RWCLK0_posedge,
          TimingData              => Tmkr_DA8_RWCLK0_posedge,
          TestSignal              => DA8_ipd,
          TestSignalName          => "DA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA8_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA8_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA8_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA8_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA9_RWCLK0_posedge,
          TimingData              => Tmkr_DA9_RWCLK0_posedge,
          TestSignal              => DA9_ipd,
          TestSignalName          => "DA9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA9_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA9_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA9_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA9_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA10_RWCLK0_posedge,
          TimingData              => Tmkr_DA10_RWCLK0_posedge,
          TestSignal              => DA10_ipd,
          TestSignalName          => "DA10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA10_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA10_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA10_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA10_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA11_RWCLK0_posedge,
          TimingData              => Tmkr_DA11_RWCLK0_posedge,
          TestSignal              => DA11_ipd,
          TestSignalName          => "DA11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA11_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA11_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA11_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA11_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA12_RWCLK0_posedge,
          TimingData              => Tmkr_DA12_RWCLK0_posedge,
          TestSignal              => DA12_ipd,
          TestSignalName          => "DA12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA12_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA12_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA12_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA12_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA13_RWCLK0_posedge,
          TimingData              => Tmkr_DA13_RWCLK0_posedge,
          TestSignal              => DA13_ipd,
          TestSignalName          => "DA13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA13_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA13_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA13_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA13_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA13_RWCLK0_posedge,
          TimingData              => Tmkr_DA13_RWCLK0_posedge,
          TestSignal              => DA13_ipd,
          TestSignalName          => "DA13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA13_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA13_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA13_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA13_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA14_RWCLK0_posedge,
          TimingData              => Tmkr_DA14_RWCLK0_posedge,
          TestSignal              => DA14_ipd,
          TestSignalName          => "DA14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA14_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA14_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA14_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA14_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA15_RWCLK0_posedge,
          TimingData              => Tmkr_DA15_RWCLK0_posedge,
          TestSignal              => DA15_ipd,
          TestSignalName          => "DA15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA15_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA15_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_posedge,
          TimingData              => Tmkr_EDA0_RWCLK0_posedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA1_RWCLK0_posedge,
          TimingData              => Tmkr_EDA1_RWCLK0_posedge,
          TestSignal              => EDA1_ipd,
          TestSignalName          => "EDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_EDA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_EDA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_EDA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_posedge,
          TimingData              => Tmkr_DB0_RWCLK1_posedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_posedge,
          TimingData              => Tmkr_DB1_RWCLK1_posedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_posedge,
          TimingData              => Tmkr_DB2_RWCLK1_posedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_posedge,
          TimingData              => Tmkr_DB3_RWCLK1_posedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_posedge,
          TimingData              => Tmkr_DB4_RWCLK1_posedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_posedge,
          TimingData              => Tmkr_DB5_RWCLK1_posedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_posedge,
          TimingData              => Tmkr_DB6_RWCLK1_posedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_posedge,
          TimingData              => Tmkr_DB7_RWCLK1_posedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB8_RWCLK1_posedge,
          TimingData              => Tmkr_DB8_RWCLK1_posedge,
          TestSignal              => DB8_ipd,
          TestSignalName          => "DB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB8_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB8_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB8_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB8_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB9_RWCLK1_posedge,
          TimingData              => Tmkr_DB9_RWCLK1_posedge,
          TestSignal              => DB9_ipd,
          TestSignalName          => "DB9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB9_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB9_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB9_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB9_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB10_RWCLK1_posedge,
          TimingData              => Tmkr_DB10_RWCLK1_posedge,
          TestSignal              => DB10_ipd,
          TestSignalName          => "DB10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB10_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB10_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB10_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB10_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB11_RWCLK1_posedge,
          TimingData              => Tmkr_DB11_RWCLK1_posedge,
          TestSignal              => DB11_ipd,
          TestSignalName          => "DB11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB11_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB11_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB11_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB11_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB12_RWCLK1_posedge,
          TimingData              => Tmkr_DB12_RWCLK1_posedge,
          TestSignal              => DB12_ipd,
          TestSignalName          => "DB12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB12_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB12_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB12_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB12_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB13_RWCLK1_posedge,
          TimingData              => Tmkr_DB13_RWCLK1_posedge,
          TestSignal              => DB13_ipd,
          TestSignalName          => "DB13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB13_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB13_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB13_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB13_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB13_RWCLK1_posedge,
          TimingData              => Tmkr_DB13_RWCLK1_posedge,
          TestSignal              => DB13_ipd,
          TestSignalName          => "DB13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB13_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB13_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB13_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB13_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB14_RWCLK1_posedge,
          TimingData              => Tmkr_DB14_RWCLK1_posedge,
          TestSignal              => DB14_ipd,
          TestSignalName          => "DB14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB14_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB14_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB14_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB14_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB15_RWCLK1_posedge,
          TimingData              => Tmkr_DB15_RWCLK1_posedge,
          TestSignal              => DB15_ipd,
          TestSignalName          => "DB15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB15_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB15_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_posedge,
          TimingData              => Tmkr_EDB0_RWCLK1_posedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB1_RWCLK1_posedge,
          TimingData              => Tmkr_EDB1_RWCLK1_posedge,
          TestSignal              => EDB1_ipd,
          TestSignalName          => "EDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_EDB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_EDB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_EDB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_posedge,
          PulseWidthLow           => tpw_RWCLK0_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_posedge,
          PulseWidthLow           => tpw_RWCLK1_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '0' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '0' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10 : std_logic := 'Z';
    VARIABLE DATA_A11 : std_logic := 'Z';
    VARIABLE DATA_A12 : std_logic := 'Z';
    VARIABLE DATA_A13 : std_logic := 'Z';
    VARIABLE DATA_A14 : std_logic := 'Z';
    VARIABLE DATA_A15 : std_logic := 'Z';
    VARIABLE DATA_A16 : std_logic := 'Z';
    VARIABLE DATA_A17 : std_logic := 'Z';
    VARIABLE OE0_inverted : std_logic := 'Z';


    BEGIN

      OE0_inverted := NOT (OE0_ipd);
      con_a := VitalAND2(OE0_inverted, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10 := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11 := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12 := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13 := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14 := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15 := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16 := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17 := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA0, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA1, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA1, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA1, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA1, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA1, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA1, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA1, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA1, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA2, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA2, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA2, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA2, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA2, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA2, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA2, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA2, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA3, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA3, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA3, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA3, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA3, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA3, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA3, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA3, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA4, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA4, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA4, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA4, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA4, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA4, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA4, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA4, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA5, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA5, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA5, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA5, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA5, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA5, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA5, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA5, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA6, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA6, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA6, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA6, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA6, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA6, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA6, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA6, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA7, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA7, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA7, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA7, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA7, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA7, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA7, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA7, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA8, GLITCH_DATA_A8, "DA8", DATA_A8,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA8, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA8, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA8, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA8, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA8, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA8, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA8, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA8, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA9, GLITCH_DATA_A9, "DA9", DATA_A9,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA9, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA9, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA9, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA9, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA9, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA9, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA9, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA9, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA10, GLITCH_DATA_A10, "DA10", DATA_A10,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA10, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA10, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA10, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA10, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA10, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA10, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA10, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA10, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA11, GLITCH_DATA_A11, "DA11", DATA_A11,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA11, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA11, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA11, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA11, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA11, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA11, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA11, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA11, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA12, GLITCH_DATA_A12, "DA12", DATA_A12,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA12, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA12, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA12, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA12, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA12, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA12, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA12, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA12, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA13, GLITCH_DATA_A13, "DA13", DATA_A13,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA13, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA13, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA13, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA13, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA13, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA13, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA13, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA13, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA14, GLITCH_DATA_A14, "DA14", DATA_A14,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA14, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA14, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA14, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA14, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA14, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA14, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA14, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA14, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA15, GLITCH_DATA_A15, "DA15", DATA_A15,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA15, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA15, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA15, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA15, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA15, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA15, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA15, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA15, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A16, "EDA0", DATA_A16,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_EDA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_EDA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_EDA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_EDA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_EDA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_EDA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_EDA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_EDA0, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA1, GLITCH_DATA_A17, "EDA1", DATA_A17,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_EDA1, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_EDA1, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_EDA1, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_EDA1, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_EDA1, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_EDA1, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_EDA1, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_EDA1, TRUE),
        8 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B17 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';
    VARIABLE DATA_B9  : std_logic := 'Z';
    VARIABLE DATA_B10 : std_logic := 'Z';
    VARIABLE DATA_B11 : std_logic := 'Z';
    VARIABLE DATA_B12 : std_logic := 'Z';
    VARIABLE DATA_B13 : std_logic := 'Z';
    VARIABLE DATA_B14 : std_logic := 'Z';
    VARIABLE DATA_B15 : std_logic := 'Z';
    VARIABLE DATA_B16 : std_logic := 'Z';
    VARIABLE DATA_B17 : std_logic := 'Z';
    VARIABLE OE1_inverted : std_logic := 'Z';


    BEGIN

      OE1_inverted := NOT (OE1_ipd);
      con_b := VitalAND2(OE1_inverted, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);
      DATA_B9  := VITALBUFIF1(data_out_b(9),con_b);
      DATA_B10 := VITALBUFIF1(data_out_b(10),con_b);
      DATA_B11 := VITALBUFIF1(data_out_b(11),con_b);
      DATA_B12 := VITALBUFIF1(data_out_b(12),con_b);
      DATA_B13 := VITALBUFIF1(data_out_b(13),con_b);
      DATA_B14 := VITALBUFIF1(data_out_b(14),con_b);
      DATA_B15 := VITALBUFIF1(data_out_b(15),con_b);
      DATA_B16 := VITALBUFIF1(data_out_b(16),con_b);
      DATA_B17 := VITALBUFIF1(data_out_b(17),con_b);


      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB0, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB1, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB1, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB1, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB1, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB1, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB1, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB1, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB1, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB2, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB2, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB2, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB2, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB2, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB2, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB2, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB2, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB3, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB3, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB3, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB3, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB3, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB3, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB3, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB3, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB4, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB4, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB4, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB4, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB4, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB4, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB4, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB4, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB5, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB5, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB5, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB5, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB5, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB5, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB5, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB5, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB6, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB6, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB6, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB6, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB6, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB6, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB6, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB6, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB7, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB7, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB7, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB7, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB7, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB7, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB7, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB7, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB8, GLITCH_DATA_B8, "DB8", DATA_B8,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB8, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB8, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB8, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB8, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB8, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB8, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB8, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB8, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB9, GLITCH_DATA_B9, "DB9", DATA_B9,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB9, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB9, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB9, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB9, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB9, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB9, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB9, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB9, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB10, GLITCH_DATA_B10, "DB10", DATA_B10,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB10, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB10, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB10, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB10, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB10, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB10, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB10, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB10, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB11, GLITCH_DATA_B11, "DB11", DATA_B11,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB11, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB11, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB11, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB11, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB11, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB11, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB11, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB11, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB12, GLITCH_DATA_B12, "DB12", DATA_B12,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB12, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB12, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB12, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB12, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB12, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB12, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB12, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB12, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB13, GLITCH_DATA_B13, "DB13", DATA_B13,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB13, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB13, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB13, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB13, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB13, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB13, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB13, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB13, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB14, GLITCH_DATA_B14, "DB14", DATA_B14,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB14, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB14, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB14, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB14, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB14, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB14, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB14, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB14, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB15, GLITCH_DATA_B15, "DB15", DATA_B15,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB15, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB15, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB15, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB15, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB15, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB15, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB15, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB15, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B16, "EDB0", DATA_B16,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_EDB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_EDB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_EDB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_EDB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_EDB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_EDB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_EDB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_EDB0, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB1, GLITCH_DATA_B17, "EDB1", DATA_B17,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_EDB1, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_EDB1, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_EDB1, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_EDB1, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_EDB1, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_EDB1, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_EDB1, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_EDB1, TRUE),
        8 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB256X18DAF_1_VITAL of RAMB256X18DAF_1 is
   for VITAL
   end for;
end CFG_RAMB256X18DAF_1_VITAL;

----- CELL RAMB512X9DSR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9DSR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK0_DA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_EDA0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_EDB0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE0_RWCLK0_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CE1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE1_RWCLK1_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA8_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA8_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB8_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB8_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK0_posedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

       INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
      CE0                            :	in    STD_ULOGIC;
      CE1                            :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDA8                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      ADDB8                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9DSR : entity is TRUE;
end RAMB512X9DSR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9DSR is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
      SIGNAL CE0_ipd                 :   std_logic :='X';
      SIGNAL CE1_ipd                 :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDA8_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL ADDB8_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;
      SIGNAL data_out_b              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL rd_clk0                 :   std_logic  := 'X';
      SIGNAL rd_clk1                 :   std_logic  := 'X';

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);
      SIGNAL din_b                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512( init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
	VitalWireDelay (CE0_ipd,      CE0,        tipd_CE0);
	VitalWireDelay (CE1_ipd,      CE1,        tipd_CE1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);
	VitalWireDelay (ADDA8_ipd,    ADDA8,      tipd_ADDA8);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);
	VitalWireDelay (ADDB8_ipd,    ADDB8,      tipd_ADDB8);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                ADDA8_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '1' and WEN0_ipd = '1') then
        rd_add_a(8) <= ADDA8_ipd;
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                ADDB8_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '1' and WEN1_ipd = '1') then
        rd_add_b(8) <= ADDB8_ipd;
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_9;
   end if;
   end process wrapper_read_add_b;


   --wrapper_read_clk_a : process(OE0_ipd, RWCLK0_ipd, CE0_ipd, WEN0_ipd)
   wrapper_read_clk_a : process( RWCLK0_ipd) --071804

   begin
    if rising_edge (RWCLK0_ipd) then --071804
     if (OE0_ipd = '1' and WEN0_ipd = '1' and CE0_ipd ='0') then
	rd_clk0 <= RWCLK0_ipd;
     end if;
    else
	rd_clk0 <= '0';
    end if;
   end process;

   --wrapper_read_clk_b : process(OE1_ipd, RWCLK1_ipd, CE1_ipd,WEN1_ipd)
   wrapper_read_clk_b : process( RWCLK1_ipd) --071804
   begin
    if rising_edge (RWCLK1_ipd) then --071804
     if (OE1_ipd = '1' and WEN1_ipd = '1' and CE1_ipd ='0') then
	 rd_clk1 <= RWCLK1_ipd;
     end if;
    else
	rd_clk1 <= '0';
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd, CE0_ipd)
   --wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd) 
   wrapper_write_clk_a : process(RWCLK0_ipd)  --071804

   begin
    if rising_edge (RWCLK0_ipd)  then --071804
     --if (WEN0_ipd = '0'and CE0_ipd = '0' ) then --112304
       if (WEN0_ipd = '0' ) then --ct061605 
	wr_clk0 <= RWCLK0_ipd;
     end if;
    else
	wr_clk0 <= '0';
    end if;
   end process;

--   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd, CE1_ipd)
   --wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd)
   wrapper_write_clk_b : process(RWCLK1_ipd) --071804
   begin
--  if (WEN1_ipd = '0'and CE1_ipd = '0') then
    if rising_edge (RWCLK1_ipd) then --071804
     --if (WEN1_ipd = '0'and CE1_ipd = '0' ) then --112304
     if (WEN1_ipd = '0' ) then --ct061605
	wr_clk1 <= RWCLK1_ipd;
     end if;
    else
	wr_clk1 <= '0';
    end if;
   end process;

   write_address_a : process(
                            ADDA8_ipd,
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(8) <= ADDA8_ipd;
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB8_ipd,
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(8) <= ADDB8_ipd;
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA0_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(8) <= EDA0_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA0_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(8) <= EDB0_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9DSR Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            rd_clk0, rd_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tviol_CE0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_CE1_RWCLK1_posedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA8_RWCLK0_posedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB8_RWCLK1_posedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_posedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CE1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA8_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB8_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_posedge,
          TimingData              => Tmkr_WEN0_RWCLK0_posedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_posedge,
          TimingData              => Tmkr_WEN1_RWCLK1_posedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE0_RWCLK0_posedge,
          TimingData              => Tmkr_CE0_RWCLK0_posedge,
          TestSignal              => CE0_ipd,
          TestSignalName          => "CE0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_CE0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_CE0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_CE0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE1_RWCLK1_posedge,
          TimingData              => Tmkr_CE1_RWCLK1_posedge,
          TestSignal              => CE1_ipd,
          TestSignalName          => "CE1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_CE1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_CE1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_CE1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_posedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_posedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_posedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_posedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_posedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_posedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_posedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_posedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA8_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA8_RWCLK0_posedge,
          TestSignal              => ADDA8_ipd,
          TestSignalName          => "ADDA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA8_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA8_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA8_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA8_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_posedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_posedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_posedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_posedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_posedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_posedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_posedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB8_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB8_RWCLK1_posedge,
          TestSignal              => ADDB8_ipd,
          TestSignalName          => "ADDB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB8_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB8_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB8_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB8_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_posedge,
          TimingData              => Tmkr_DA0_RWCLK0_posedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_posedge,
          TimingData              => Tmkr_DA1_RWCLK0_posedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_posedge,
          TimingData              => Tmkr_DA2_RWCLK0_posedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_posedge,
          TimingData              => Tmkr_DA3_RWCLK0_posedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_posedge,
          TimingData              => Tmkr_DA4_RWCLK0_posedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_posedge,
          TimingData              => Tmkr_DA5_RWCLK0_posedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_posedge,
          TimingData              => Tmkr_DA6_RWCLK0_posedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_posedge,
          TimingData              => Tmkr_DA7_RWCLK0_posedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_posedge,
          TimingData              => Tmkr_EDA0_RWCLK0_posedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_posedge,
          TimingData              => Tmkr_DB0_RWCLK1_posedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_posedge,
          TimingData              => Tmkr_DB1_RWCLK1_posedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_posedge,
          TimingData              => Tmkr_DB2_RWCLK1_posedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_posedge,
          TimingData              => Tmkr_DB3_RWCLK1_posedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_posedge,
          TimingData              => Tmkr_DB4_RWCLK1_posedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_posedge,
          TimingData              => Tmkr_DB5_RWCLK1_posedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_posedge,
          TimingData              => Tmkr_DB6_RWCLK1_posedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_posedge,
          TimingData              => Tmkr_DB7_RWCLK1_posedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_posedge,
          TimingData              => Tmkr_EDB0_RWCLK1_posedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_posedge,
          PulseWidthLow           => tpw_RWCLK0_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_posedge,
          PulseWidthLow           => tpw_RWCLK1_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk0'EVENT and rd_clk0 = '1' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '1' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '1' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( (rd_clk1'EVENT and rd_clk1 = '1') and not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';

    BEGIN

      con_a := VitalAND2(OE0_ipd, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);

      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA1, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA2, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA3, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA4, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA5, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA6, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA7, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A8, "EDA0", DATA_A8,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_EDA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';

    BEGIN

      con_b := VitalAND2(OE1_ipd, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);

      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB1, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB2, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB3, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB4, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB5, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB6, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB7, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B8, "EDB0", DATA_B8,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_EDB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB512X9DSR_VITAL of RAMB512X9DSR is
   for VITAL
   end for;
end CFG_RAMB512X9DSR_VITAL;

----- CELL RAMB512X9DSR_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9DSR_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK0_DA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_EDA0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_EDB0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE0_RWCLK0_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CE1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE1_RWCLK1_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA8_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA8_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB8_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB8_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK0_posedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

       INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
      CE0                            :	in    STD_ULOGIC;
      CE1                            :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDA8                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      ADDB8                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9DSR_1 : entity is TRUE;
end RAMB512X9DSR_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9DSR_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
      SIGNAL CE0_ipd                 :   std_logic :='X';
      SIGNAL CE1_ipd                 :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDA8_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL ADDB8_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;
      SIGNAL data_out_b              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL rd_clk0                 :   std_logic  := 'X';
      SIGNAL rd_clk1                 :   std_logic  := 'X';

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);
      SIGNAL din_b                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512( init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
	VitalWireDelay (CE0_ipd,      CE0,        tipd_CE0);
	VitalWireDelay (CE1_ipd,      CE1,        tipd_CE1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);
	VitalWireDelay (ADDA8_ipd,    ADDA8,      tipd_ADDA8);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);
	VitalWireDelay (ADDB8_ipd,    ADDB8,      tipd_ADDB8);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                ADDA8_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '0' and WEN0_ipd = '1') then
        rd_add_a(8) <= ADDA8_ipd;
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                ADDB8_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '0' and WEN1_ipd = '1') then
        rd_add_b(8) <= ADDB8_ipd;
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_9;
   end if;
   end process wrapper_read_add_b;


   wrapper_read_clk_a : process(OE0_ipd, RWCLK0_ipd, CE0_ipd, WEN0_ipd)

   begin
    if (OE0_ipd = '0' and WEN0_ipd = '1' and CE0_ipd ='0') then
	rd_clk0 <= RWCLK0_ipd;
    else
	rd_clk0 <= '0';
    end if;
   end process;

   wrapper_read_clk_b : process(OE1_ipd, RWCLK1_ipd, CE1_ipd,WEN1_ipd)

   begin
    if (OE1_ipd = '0' and WEN1_ipd = '1' and CE1_ipd ='0') then
	rd_clk1 <= RWCLK1_ipd;
    else
	rd_clk1 <= '0';
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd, CE0_ipd)
   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd)

   begin
--    if (WEN0_ipd = '0' and CE0_ipd = '0' ) then
    if (WEN0_ipd = '0') then
	wr_clk0 <= RWCLK0_ipd;
    else
	wr_clk0 <= '0';
    end if;
   end process;

--   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd, CE1_ipd)
   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd)

   begin
--    if (WEN1_ipd = '0'and CE1_ipd = '0') then
    if (WEN1_ipd = '0') then
	wr_clk1 <= RWCLK1_ipd;
    else
	wr_clk1 <= '0';
    end if;
   end process;

   write_address_a : process(
                            ADDA8_ipd,
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(8) <= ADDA8_ipd;
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB8_ipd,
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(8) <= ADDB8_ipd;
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA0_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(8) <= EDA0_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA0_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(8) <= EDB0_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9DSR_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            rd_clk0, rd_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tviol_CE0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_CE1_RWCLK1_posedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA8_RWCLK0_posedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB8_RWCLK1_posedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_posedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CE1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA8_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB8_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_posedge,
          TimingData              => Tmkr_WEN0_RWCLK0_posedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_posedge,
          TimingData              => Tmkr_WEN1_RWCLK1_posedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE0_RWCLK0_posedge,
          TimingData              => Tmkr_CE0_RWCLK0_posedge,
          TestSignal              => CE0_ipd,
          TestSignalName          => "CE0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_CE0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_CE0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_CE0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE1_RWCLK1_posedge,
          TimingData              => Tmkr_CE1_RWCLK1_posedge,
          TestSignal              => CE1_ipd,
          TestSignalName          => "CE1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_CE1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_CE1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_CE1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_posedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_posedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_posedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_posedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_posedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_posedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_posedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_posedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA8_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA8_RWCLK0_posedge,
          TestSignal              => ADDA8_ipd,
          TestSignalName          => "ADDA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA8_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA8_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA8_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA8_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_posedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_posedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_posedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_posedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_posedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_posedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_posedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB8_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB8_RWCLK1_posedge,
          TestSignal              => ADDB8_ipd,
          TestSignalName          => "ADDB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB8_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB8_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB8_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB8_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_posedge,
          TimingData              => Tmkr_DA0_RWCLK0_posedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_posedge,
          TimingData              => Tmkr_DA1_RWCLK0_posedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_posedge,
          TimingData              => Tmkr_DA2_RWCLK0_posedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_posedge,
          TimingData              => Tmkr_DA3_RWCLK0_posedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_posedge,
          TimingData              => Tmkr_DA4_RWCLK0_posedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_posedge,
          TimingData              => Tmkr_DA5_RWCLK0_posedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_posedge,
          TimingData              => Tmkr_DA6_RWCLK0_posedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_posedge,
          TimingData              => Tmkr_DA7_RWCLK0_posedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_posedge,
          TimingData              => Tmkr_EDA0_RWCLK0_posedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_posedge,
          TimingData              => Tmkr_DB0_RWCLK1_posedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_posedge,
          TimingData              => Tmkr_DB1_RWCLK1_posedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_posedge,
          TimingData              => Tmkr_DB2_RWCLK1_posedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_posedge,
          TimingData              => Tmkr_DB3_RWCLK1_posedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_posedge,
          TimingData              => Tmkr_DB4_RWCLK1_posedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_posedge,
          TimingData              => Tmkr_DB5_RWCLK1_posedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_posedge,
          TimingData              => Tmkr_DB6_RWCLK1_posedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_posedge,
          TimingData              => Tmkr_DB7_RWCLK1_posedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_posedge,
          TimingData              => Tmkr_EDB0_RWCLK1_posedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_posedge,
          PulseWidthLow           => tpw_RWCLK0_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_posedge,
          PulseWidthLow           => tpw_RWCLK1_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk0'EVENT and rd_clk0 = '1' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '1' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '1' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( (rd_clk1'EVENT and rd_clk1 = '1') and not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE OE0_inverted  : std_logic := 'Z';

    BEGIN
      OE0_inverted := NOT (OE0_ipd);
      con_a := VitalAND2(OE0_inverted, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);

      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA1, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA2, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA3, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA4, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA5, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA6, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA7, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A8, "EDA0", DATA_A8,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_EDA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';
    VARIABLE OE1_inverted  : std_logic := 'Z';

    BEGIN
      OE1_inverted := NOT (OE1_ipd);
      con_b := VitalAND2(OE1_inverted, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);

      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB1, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB2, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB3, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB4, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB5, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB6, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB7, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B8, "EDB0", DATA_B8,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_EDB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB512X9DSR_1_VITAL of RAMB512X9DSR_1 is
   for VITAL
   end for;
end CFG_RAMB512X9DSR_1_VITAL;

----- CELL RAMB512X9DSF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9DSF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK0_DA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_EDA0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_EDB0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE0_RWCLK0_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      thold_CE0_RWCLK0_noedge_negedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CE1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      thold_CE1_RWCLK1_noedge_negedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA8_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA8_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB8_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB8_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK0_negedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_negedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

       INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
      CE0                            :	in    STD_ULOGIC;
      CE1                            :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDA8                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      ADDB8                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9DSF : entity is TRUE;
end RAMB512X9DSF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9DSF is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
      SIGNAL CE0_ipd                 :   std_logic :='X';
      SIGNAL CE1_ipd                 :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDA8_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL ADDB8_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;
      SIGNAL data_out_b              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL rd_clk0                 :   std_logic  := 'X';
      SIGNAL rd_clk1                 :   std_logic  := 'X';

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);
      SIGNAL din_b                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512( init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
	VitalWireDelay (CE0_ipd,      CE0,        tipd_CE0);
	VitalWireDelay (CE1_ipd,      CE1,        tipd_CE1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);
	VitalWireDelay (ADDA8_ipd,    ADDA8,      tipd_ADDA8);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);
	VitalWireDelay (ADDB8_ipd,    ADDB8,      tipd_ADDB8);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                ADDA8_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '1' and WEN0_ipd = '1') then
        rd_add_a(8) <= ADDA8_ipd;
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                ADDB8_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '1' and WEN1_ipd = '1') then
        rd_add_b(8) <= ADDB8_ipd;
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_9;
   end if;
   end process wrapper_read_add_b;


   wrapper_read_clk_a : process(OE0_ipd, RWCLK0_ipd, CE0_ipd, WEN0_ipd)

   begin
    if (OE0_ipd = '1' and WEN0_ipd = '1' and CE0_ipd ='0') then
	rd_clk0 <= RWCLK0_ipd;
    else
	rd_clk0 <= '1';
    end if;
   end process;

   wrapper_read_clk_b : process(OE1_ipd, RWCLK1_ipd, CE1_ipd,WEN1_ipd)

   begin
    if (OE1_ipd = '1' and WEN1_ipd = '1' and CE1_ipd ='0') then
	rd_clk1 <= RWCLK1_ipd;
    else
	rd_clk1 <= '1';
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd, CE0_ipd)
   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd)

   begin
--    if (WEN0_ipd = '0' and CE0_ipd = '0' ) then
    if (WEN0_ipd = '0') then
	wr_clk0 <= RWCLK0_ipd;
    else
	wr_clk0 <= '1';
    end if;
   end process;

--   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd, CE1_ipd)
   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd)

   begin
--    if (WEN1_ipd = '0'and CE1_ipd = '0') then
    if (WEN1_ipd = '0') then
	wr_clk1 <= RWCLK1_ipd;
    else
	wr_clk1 <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADDA8_ipd,
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(8) <= ADDA8_ipd;
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB8_ipd,
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(8) <= ADDB8_ipd;
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA0_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(8) <= EDA0_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA0_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(8) <= EDB0_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9DSF Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            rd_clk0, rd_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_negedge   : std_ulogic  := '0';

        variable Tviol_CE0_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_CE1_RWCLK1_negedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA8_RWCLK0_negedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB8_RWCLK1_negedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_negedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_negedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE0_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CE1_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA8_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB8_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_negedge,
          TimingData              => Tmkr_WEN0_RWCLK0_negedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_negedge,
          TimingData              => Tmkr_WEN1_RWCLK1_negedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE0_RWCLK0_negedge,
          TimingData              => Tmkr_CE0_RWCLK0_negedge,
          TestSignal              => CE0_ipd,
          TestSignalName          => "CE0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_CE0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_CE0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_CE0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE1_RWCLK1_negedge,
          TimingData              => Tmkr_CE1_RWCLK1_negedge,
          TestSignal              => CE1_ipd,
          TestSignalName          => "CE1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_CE1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_CE1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_CE1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_negedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_negedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_negedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_negedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_negedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_negedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_negedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_negedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA8_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA8_RWCLK0_negedge,
          TestSignal              => ADDA8_ipd,
          TestSignalName          => "ADDA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA8_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA8_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA8_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA8_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_negedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_negedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_negedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_negedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_negedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_negedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_negedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_negedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB8_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB8_RWCLK1_negedge,
          TestSignal              => ADDB8_ipd,
          TestSignalName          => "ADDB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB8_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB8_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB8_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB8_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_negedge,
          TimingData              => Tmkr_DA0_RWCLK0_negedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_negedge,
          TimingData              => Tmkr_DA1_RWCLK0_negedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_negedge,
          TimingData              => Tmkr_DA2_RWCLK0_negedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_negedge,
          TimingData              => Tmkr_DA3_RWCLK0_negedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_negedge,
          TimingData              => Tmkr_DA4_RWCLK0_negedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_negedge,
          TimingData              => Tmkr_DA5_RWCLK0_negedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_negedge,
          TimingData              => Tmkr_DA6_RWCLK0_negedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_negedge,
          TimingData              => Tmkr_DA7_RWCLK0_negedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_negedge,
          TimingData              => Tmkr_EDA0_RWCLK0_negedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_negedge,
          TimingData              => Tmkr_DB0_RWCLK1_negedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_negedge,
          TimingData              => Tmkr_DB1_RWCLK1_negedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_negedge,
          TimingData              => Tmkr_DB2_RWCLK1_negedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_negedge,
          TimingData              => Tmkr_DB3_RWCLK1_negedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_negedge,
          TimingData              => Tmkr_DB4_RWCLK1_negedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_negedge,
          TimingData              => Tmkr_DB5_RWCLK1_negedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_negedge,
          TimingData              => Tmkr_DB6_RWCLK1_negedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_negedge,
          TimingData              => Tmkr_DB7_RWCLK1_negedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_negedge,
          TimingData              => Tmkr_EDB0_RWCLK1_negedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_negedge,
          PulseWidthLow           => tpw_RWCLK0_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_negedge,
          PulseWidthLow           => tpw_RWCLK1_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk0'EVENT and rd_clk0 = '0' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '0' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '0' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( (rd_clk1'EVENT and rd_clk1 = '0') and not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';

    BEGIN

      con_a := VitalAND2(OE0_ipd, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);

      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA1, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA2, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA3, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA4, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA5, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA6, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA7, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A8, "EDA0", DATA_A8,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_EDA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';

    BEGIN

      con_b := VitalAND2(OE1_ipd, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);

      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB1, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB2, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB3, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB4, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB5, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB6, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB7, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B8, "EDB0", DATA_B8,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_EDB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB512X9DSF_VITAL of RAMB512X9DSF is
   for VITAL
   end for;
end CFG_RAMB512X9DSF_VITAL;

----- CELL RAMB512X9DSF_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9DSF_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK0_DA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_DA7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK0_EDA0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_DB7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK1_EDB0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE0_RWCLK0_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      thold_CE0_RWCLK0_noedge_negedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CE1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      thold_CE1_RWCLK1_noedge_negedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA8_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA8_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB8_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB8_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK0_negedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_negedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

       INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
      CE0                            :	in    STD_ULOGIC;
      CE1                            :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDA8                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      ADDB8                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9DSF_1 : entity is TRUE;
end RAMB512X9DSF_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9DSF_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
      SIGNAL CE0_ipd                 :   std_logic :='X';
      SIGNAL CE1_ipd                 :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDA8_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL ADDB8_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;
      SIGNAL data_out_b              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL rd_clk0                 :   std_logic  := 'X';
      SIGNAL rd_clk1                 :   std_logic  := 'X';

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);
      SIGNAL din_b                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512( init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
	VitalWireDelay (CE0_ipd,      CE0,        tipd_CE0);
	VitalWireDelay (CE1_ipd,      CE1,        tipd_CE1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);
	VitalWireDelay (ADDA8_ipd,    ADDA8,      tipd_ADDA8);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);
	VitalWireDelay (ADDB8_ipd,    ADDB8,      tipd_ADDB8);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                ADDA8_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '0' and WEN0_ipd = '1') then
        rd_add_a(8) <= ADDA8_ipd;
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                ADDB8_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '0' and WEN1_ipd = '1') then
        rd_add_b(8) <= ADDB8_ipd;
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_9;
   end if;
   end process wrapper_read_add_b;


   wrapper_read_clk_a : process(OE0_ipd, RWCLK0_ipd, CE0_ipd, WEN0_ipd)

   begin
    if (OE0_ipd = '0' and WEN0_ipd = '1' and CE0_ipd ='0') then
	rd_clk0 <= RWCLK0_ipd;
    else
	rd_clk0 <= '1';
    end if;
   end process;

   wrapper_read_clk_b : process(OE1_ipd, RWCLK1_ipd, CE1_ipd,WEN1_ipd)

   begin
    if (OE1_ipd = '0' and WEN1_ipd = '1' and CE1_ipd ='0') then
	rd_clk1 <= RWCLK1_ipd;
    else
	rd_clk1 <= '1';
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd, CE0_ipd)
   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd)

   begin
--    if (WEN0_ipd = '0' and CE0_ipd = '0' ) then
    if (WEN0_ipd = '0') then
	wr_clk0 <= RWCLK0_ipd;
    else
	wr_clk0 <= '1';
    end if;
   end process;

--   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd, CE1_ipd)
   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd)

   begin
--    if (WEN1_ipd = '0'and CE1_ipd = '0') then
    if (WEN1_ipd = '0') then
	wr_clk1 <= RWCLK1_ipd;
    else
	wr_clk1 <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADDA8_ipd,
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(8) <= ADDA8_ipd;
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB8_ipd,
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(8) <= ADDB8_ipd;
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA0_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(8) <= EDA0_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA0_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(8) <= EDB0_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9DSF_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            rd_clk0, rd_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_negedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_negedge   : std_ulogic  := '0';

        variable Tviol_CE0_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_CE1_RWCLK1_negedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_negedge  : std_ulogic  := '0';
        variable Tviol_ADDA8_RWCLK0_negedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_negedge  : std_ulogic  := '0';
        variable Tviol_ADDB8_RWCLK1_negedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_negedge    : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_negedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_negedge    : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_negedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE0_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CE1_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA8_RWCLK0_negedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB8_RWCLK1_negedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_negedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_negedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_negedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_negedge,
          TimingData              => Tmkr_WEN0_RWCLK0_negedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_negedge,
          TimingData              => Tmkr_WEN1_RWCLK1_negedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE0_RWCLK0_negedge,
          TimingData              => Tmkr_CE0_RWCLK0_negedge,
          TestSignal              => CE0_ipd,
          TestSignalName          => "CE0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_CE0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_CE0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_CE0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE1_RWCLK1_negedge,
          TimingData              => Tmkr_CE1_RWCLK1_negedge,
          TestSignal              => CE1_ipd,
          TestSignalName          => "CE1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_CE1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_CE1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_CE1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_negedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_negedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_negedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_negedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_negedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_negedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_negedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_negedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA8_RWCLK0_negedge,
          TimingData              => Tmkr_ADDA8_RWCLK0_negedge,
          TestSignal              => ADDA8_ipd,
          TestSignalName          => "ADDA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA8_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA8_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA8_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA8_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_negedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_negedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_negedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_negedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_negedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_negedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_negedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_negedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB8_RWCLK1_negedge,
          TimingData              => Tmkr_ADDB8_RWCLK1_negedge,
          TestSignal              => ADDB8_ipd,
          TestSignalName          => "ADDB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB8_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB8_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB8_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB8_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_negedge,
          TimingData              => Tmkr_DA0_RWCLK0_negedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_negedge,
          TimingData              => Tmkr_DA1_RWCLK0_negedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_negedge,
          TimingData              => Tmkr_DA2_RWCLK0_negedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_negedge,
          TimingData              => Tmkr_DA3_RWCLK0_negedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_negedge,
          TimingData              => Tmkr_DA4_RWCLK0_negedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_negedge,
          TimingData              => Tmkr_DA5_RWCLK0_negedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_negedge,
          TimingData              => Tmkr_DA6_RWCLK0_negedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_negedge,
          TimingData              => Tmkr_DA7_RWCLK0_negedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_negedge,
          TimingData              => Tmkr_EDA0_RWCLK0_negedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_negedge,
          TimingData              => Tmkr_DB0_RWCLK1_negedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_negedge,
          TimingData              => Tmkr_DB1_RWCLK1_negedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_negedge,
          TimingData              => Tmkr_DB2_RWCLK1_negedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_negedge,
          TimingData              => Tmkr_DB3_RWCLK1_negedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_negedge,
          TimingData              => Tmkr_DB4_RWCLK1_negedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_negedge,
          TimingData              => Tmkr_DB5_RWCLK1_negedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_negedge,
          TimingData              => Tmkr_DB6_RWCLK1_negedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_negedge,
          TimingData              => Tmkr_DB7_RWCLK1_negedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_negedge,
          TimingData              => Tmkr_EDB0_RWCLK1_negedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_negedge,
          PulseWidthLow           => tpw_RWCLK0_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_negedge,
          PulseWidthLow           => tpw_RWCLK1_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk0'EVENT and rd_clk0 = '0' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '0' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '0' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( (rd_clk1'EVENT and rd_clk1 = '0') and not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE OE0_inverted  : std_logic := 'Z';

    BEGIN
      OE0_inverted := NOT (OE0_ipd);
      con_a := VitalAND2(OE0_inverted, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);

      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA1, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA2, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA3, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA4, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA5, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA6, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_DA7, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A8, "EDA0", DATA_A8,
        Paths => (
        0 => ( RWCLK0_ipd'LAST_EVENT, tpd_RWCLK0_EDA0, TRUE),
        1 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';
    VARIABLE OE1_inverted  : std_logic := 'Z';

    BEGIN
      OE1_inverted := NOT (OE1_ipd);
      con_b := VitalAND2(OE1_inverted, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);

      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB1, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB2, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB3, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB4, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB5, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB6, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_DB7, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B8, "EDB0", DATA_B8,
        Paths => (
        0 => ( RWCLK1_ipd'LAST_EVENT, tpd_RWCLK1_EDB0, TRUE),
        1 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB512X9DSF_1_VITAL of RAMB512X9DSF_1 is
   for VITAL
   end for;
end CFG_RAMB512X9DSF_1_VITAL;

----- CELL RAMB512X9DAR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9DAR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADDA0_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE0_RWCLK0_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CE1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE1_RWCLK1_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA8_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA8_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB8_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB8_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK0_posedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDA8                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      ADDB8                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9DAR : entity is TRUE;
end RAMB512X9DAR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9DAR is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDA8_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL ADDB8_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;
      SIGNAL data_out_b              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);
      SIGNAL din_b                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512( init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);
	VitalWireDelay (ADDA8_ipd,    ADDA8,      tipd_ADDA8);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);
	VitalWireDelay (ADDB8_ipd,    ADDB8,      tipd_ADDB8);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                ADDA8_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '1' and WEN0_ipd = '1') then
        rd_add_a(8) <= ADDA8_ipd;
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                ADDB8_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '1' and WEN1_ipd = '1') then
        rd_add_b(8) <= ADDB8_ipd;
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_9;
   end if;
   end process wrapper_read_add_b;

   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd)

   begin
    if (WEN0_ipd = '0' ) then
	wr_clk0 <= RWCLK0_ipd;
    else
	wr_clk0 <= '0';
    end if;
   end process;

   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd)

   begin
    if (WEN1_ipd = '0' ) then
	wr_clk1 <= RWCLK1_ipd;
    else
	wr_clk1 <= '0';
    end if;
   end process;

   write_address_a : process(
                            ADDA8_ipd,
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(8) <= ADDA8_ipd;
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB8_ipd,
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(8) <= ADDB8_ipd;
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA0_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(8)  <= EDA0_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA0_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(8) <= EDB0_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9DAR Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tviol_CE0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_CE1_RWCLK1_posedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA8_RWCLK0_posedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB8_RWCLK1_posedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_posedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CE1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA8_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB8_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_posedge,
          TimingData              => Tmkr_WEN0_RWCLK0_posedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_posedge,
          TimingData              => Tmkr_WEN1_RWCLK1_posedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_posedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_posedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_posedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_posedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_posedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_posedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_posedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_posedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA8_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA8_RWCLK0_posedge,
          TestSignal              => ADDA8_ipd,
          TestSignalName          => "ADDA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA8_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA8_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA8_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA8_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_posedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_posedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_posedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_posedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_posedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_posedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_posedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB8_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB8_RWCLK1_posedge,
          TestSignal              => ADDB8_ipd,
          TestSignalName          => "ADDB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB8_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB8_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB8_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB8_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_posedge,
          TimingData              => Tmkr_DA0_RWCLK0_posedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_posedge,
          TimingData              => Tmkr_DA1_RWCLK0_posedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_posedge,
          TimingData              => Tmkr_DA2_RWCLK0_posedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_posedge,
          TimingData              => Tmkr_DA3_RWCLK0_posedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_posedge,
          TimingData              => Tmkr_DA4_RWCLK0_posedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_posedge,
          TimingData              => Tmkr_DA5_RWCLK0_posedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_posedge,
          TimingData              => Tmkr_DA6_RWCLK0_posedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_posedge,
          TimingData              => Tmkr_DA7_RWCLK0_posedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_posedge,
          TimingData              => Tmkr_EDA0_RWCLK0_posedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_posedge,
          TimingData              => Tmkr_DB0_RWCLK1_posedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_posedge,
          TimingData              => Tmkr_DB1_RWCLK1_posedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_posedge,
          TimingData              => Tmkr_DB2_RWCLK1_posedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_posedge,
          TimingData              => Tmkr_DB3_RWCLK1_posedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_posedge,
          TimingData              => Tmkr_DB4_RWCLK1_posedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_posedge,
          TimingData              => Tmkr_DB5_RWCLK1_posedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_posedge,
          TimingData              => Tmkr_DB6_RWCLK1_posedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_posedge,
          TimingData              => Tmkr_DB7_RWCLK1_posedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_posedge,
          TimingData              => Tmkr_EDB0_RWCLK1_posedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_posedge,
          PulseWidthLow           => tpw_RWCLK0_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_posedge,
          PulseWidthLow           => tpw_RWCLK1_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '1' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '1' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';


    BEGIN

      con_a := VitalAND2(OE0_ipd, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);


      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA0, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA0, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA1, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA1, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA1, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA1, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA1, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA1, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA1, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA1, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA1, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA2, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA2, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA2, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA2, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA2, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA2, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA2, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA2, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA2, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA3, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA3, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA3, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA3, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA3, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA3, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA3, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA3, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA3, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA4, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA4, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA4, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA4, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA4, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA4, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA4, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA4, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA4, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA5, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA5, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA5, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA5, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA5, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA5, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA5, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA5, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA5, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA6, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA6, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA6, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA6, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA6, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA6, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA6, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA6, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA6, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA7, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA7, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA7, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA7, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA7, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA7, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA7, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA7, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA7, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A8, "EDA0", DATA_A8,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_EDA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_EDA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_EDA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_EDA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_EDA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_EDA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_EDA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_EDA0, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_EDA0, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';

    BEGIN

      con_b := VitalAND2(OE1_ipd, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);


      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB0, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB0, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB1, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB1, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB1, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB1, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB1, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB1, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB1, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB1, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB1, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB2, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB2, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB2, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB2, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB2, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB2, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB2, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB2, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB2, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB3, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB3, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB3, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB3, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB3, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB3, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB3, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB3, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB3, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB4, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB4, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB4, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB4, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB4, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB4, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB4, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB4, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB4, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB5, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB5, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB5, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB5, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB5, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB5, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB5, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB5, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB5, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB6, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB6, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB6, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB6, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB6, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB6, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB6, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB6, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB6, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB7, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB7, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB7, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB7, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB7, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB7, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB7, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB7, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB7, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B8, "EDB0", DATA_B8,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_EDB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_EDB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_EDB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_EDB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_EDB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_EDB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_EDB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_EDB0, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_EDB0, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB512X9DAR_VITAL of RAMB512X9DAR is
   for VITAL
   end for;
end CFG_RAMB512X9DAR_VITAL;

----- CELL RAMB512X9DAR_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9DAR_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADDA0_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE0_RWCLK0_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE0_RWCLK0_noedge_posedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CE1_RWCLK1_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE1_RWCLK1_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA8_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA8_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB8_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB8_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK0_posedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDA8                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      ADDB8                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9DAR_1 : entity is TRUE;
end RAMB512X9DAR_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9DAR_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDA8_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL ADDB8_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;
      SIGNAL data_out_b              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);
      SIGNAL din_b                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512( init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);
	VitalWireDelay (ADDA8_ipd,    ADDA8,      tipd_ADDA8);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);
	VitalWireDelay (ADDB8_ipd,    ADDB8,      tipd_ADDB8);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                ADDA8_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '0' and WEN0_ipd = '1') then
        rd_add_a(8) <= ADDA8_ipd;
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                ADDB8_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '0' and WEN1_ipd = '1') then
        rd_add_b(8) <= ADDB8_ipd;
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_9;
   end if;
   end process wrapper_read_add_b;

   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd)

   begin
    if (WEN0_ipd = '0' ) then
	wr_clk0 <= RWCLK0_ipd;
    else
	wr_clk0 <= '0';
    end if;
   end process;

   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd)

   begin
    if (WEN1_ipd = '0' ) then
	wr_clk1 <= RWCLK1_ipd;
    else
	wr_clk1 <= '0';
    end if;
   end process;

   write_address_a : process(
                            ADDA8_ipd,
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(8) <= ADDA8_ipd;
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB8_ipd,
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(8) <= ADDB8_ipd;
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA0_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(8)  <= EDA0_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA0_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(8) <= EDB0_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9DAR_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tviol_CE0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_CE1_RWCLK1_posedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA8_RWCLK0_posedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB8_RWCLK1_posedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_posedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CE1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA8_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB8_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_posedge,
          TimingData              => Tmkr_WEN0_RWCLK0_posedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_posedge,
          TimingData              => Tmkr_WEN1_RWCLK1_posedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_posedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_posedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_posedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_posedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_posedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_posedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_posedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_posedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA8_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA8_RWCLK0_posedge,
          TestSignal              => ADDA8_ipd,
          TestSignalName          => "ADDA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA8_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_ADDA8_RWCLK0_noedge_posedge,
          HoldLow                 => thold_ADDA8_RWCLK0_noedge_posedge,
          HoldHigh                => thold_ADDA8_RWCLK0_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_posedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_posedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_posedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_posedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_posedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_posedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_posedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB8_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB8_RWCLK1_posedge,
          TestSignal              => ADDB8_ipd,
          TestSignalName          => "ADDB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB8_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_ADDB8_RWCLK1_noedge_posedge,
          HoldLow                 => thold_ADDB8_RWCLK1_noedge_posedge,
          HoldHigh                => thold_ADDB8_RWCLK1_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_posedge,
          TimingData              => Tmkr_DA0_RWCLK0_posedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_posedge,
          TimingData              => Tmkr_DA1_RWCLK0_posedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_posedge,
          TimingData              => Tmkr_DA2_RWCLK0_posedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_posedge,
          TimingData              => Tmkr_DA3_RWCLK0_posedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_posedge,
          TimingData              => Tmkr_DA4_RWCLK0_posedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_posedge,
          TimingData              => Tmkr_DA5_RWCLK0_posedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_posedge,
          TimingData              => Tmkr_DA6_RWCLK0_posedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_posedge,
          TimingData              => Tmkr_DA7_RWCLK0_posedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_posedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_posedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_posedge,
          TimingData              => Tmkr_EDA0_RWCLK0_posedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_posedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_posedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_posedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_posedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_posedge,
          TimingData              => Tmkr_DB0_RWCLK1_posedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_posedge,
          TimingData              => Tmkr_DB1_RWCLK1_posedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_posedge,
          TimingData              => Tmkr_DB2_RWCLK1_posedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_posedge,
          TimingData              => Tmkr_DB3_RWCLK1_posedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_posedge,
          TimingData              => Tmkr_DB4_RWCLK1_posedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_posedge,
          TimingData              => Tmkr_DB5_RWCLK1_posedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_posedge,
          TimingData              => Tmkr_DB6_RWCLK1_posedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_posedge,
          TimingData              => Tmkr_DB7_RWCLK1_posedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_posedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_posedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_posedge,
          TimingData              => Tmkr_EDB0_RWCLK1_posedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_posedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_posedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_posedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_posedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_posedge,
          PulseWidthLow           => tpw_RWCLK0_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_posedge,
          PulseWidthLow           => tpw_RWCLK1_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '1' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '1' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE OE0_inverted  : std_logic := 'Z';


    BEGIN

      OE0_inverted := NOT (OE0_ipd);
      con_a := VitalAND2(OE0_inverted, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);


      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA0, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA0, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA1, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA1, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA1, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA1, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA1, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA1, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA1, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA1, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA1, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA2, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA2, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA2, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA2, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA2, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA2, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA2, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA2, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA2, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA3, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA3, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA3, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA3, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA3, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA3, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA3, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA3, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA3, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA4, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA4, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA4, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA4, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA4, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA4, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA4, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA4, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA4, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA5, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA5, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA5, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA5, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA5, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA5, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA5, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA5, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA5, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA6, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA6, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA6, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA6, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA6, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA6, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA6, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA6, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA6, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA7, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA7, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA7, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA7, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA7, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA7, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA7, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA7, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA7, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A8, "EDA0", DATA_A8,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_EDA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_EDA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_EDA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_EDA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_EDA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_EDA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_EDA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_EDA0, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_EDA0, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';
    VARIABLE OE1_inverted  : std_logic := 'Z';

    BEGIN

      OE1_inverted := NOT (OE1_ipd);
      con_b := VitalAND2(OE1_inverted, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);


      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB0, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB0, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB1, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB1, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB1, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB1, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB1, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB1, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB1, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB1, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB1, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB2, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB2, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB2, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB2, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB2, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB2, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB2, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB2, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB2, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB3, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB3, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB3, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB3, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB3, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB3, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB3, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB3, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB3, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB4, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB4, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB4, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB4, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB4, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB4, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB4, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB4, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB4, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB5, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB5, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB5, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB5, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB5, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB5, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB5, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB5, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB5, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB6, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB6, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB6, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB6, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB6, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB6, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB6, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB6, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB6, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB7, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB7, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB7, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB7, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB7, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB7, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB7, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB7, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB7, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B8, "EDB0", DATA_B8,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_EDB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_EDB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_EDB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_EDB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_EDB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_EDB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_EDB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_EDB0, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_EDB0, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB512X9DAR_1_VITAL of RAMB512X9DAR_1 is
   for VITAL
   end for;
end CFG_RAMB512X9DAR_1_VITAL;

----- CELL RAMB512X9DAF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9DAF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADDA0_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE0_RWCLK0_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      thold_CE0_RWCLK0_noedge_negedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CE1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      thold_CE1_RWCLK1_noedge_negedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA8_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA8_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB8_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB8_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK0_posedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDA8                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      ADDB8                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9DAF : entity is TRUE;
end RAMB512X9DAF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9DAF is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDA8_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL ADDB8_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;
      SIGNAL data_out_b              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);
      SIGNAL din_b                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512( init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);
	VitalWireDelay (ADDA8_ipd,    ADDA8,      tipd_ADDA8);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);
	VitalWireDelay (ADDB8_ipd,    ADDB8,      tipd_ADDB8);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                ADDA8_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '1' and WEN0_ipd = '1') then
        rd_add_a(8) <= ADDA8_ipd;
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                ADDB8_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '1' and WEN1_ipd = '1') then
        rd_add_b(8) <= ADDB8_ipd;
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_9;
   end if;
   end process wrapper_read_add_b;

   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd)

   begin
    if (WEN0_ipd = '0' ) then
	wr_clk0 <= RWCLK0_ipd;
    else
	wr_clk0 <= '1';
    end if;
   end process;

   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd)

   begin
    if (WEN1_ipd = '0' ) then
	wr_clk1 <= RWCLK1_ipd;
    else
	wr_clk1 <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADDA8_ipd,
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(8) <= ADDA8_ipd;
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB8_ipd,
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(8) <= ADDB8_ipd;
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA0_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(8)  <= EDA0_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA0_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(8) <= EDB0_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9DAF Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tviol_CE0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_CE1_RWCLK1_posedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA8_RWCLK0_posedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB8_RWCLK1_posedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_posedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CE1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA8_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB8_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_posedge,
          TimingData              => Tmkr_WEN0_RWCLK0_posedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_posedge,
          TimingData              => Tmkr_WEN1_RWCLK1_posedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_posedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_posedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_posedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_posedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_posedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_posedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_posedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_posedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA8_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA8_RWCLK0_posedge,
          TestSignal              => ADDA8_ipd,
          TestSignalName          => "ADDA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA8_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA8_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA8_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA8_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_posedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_posedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_posedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_posedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_posedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_posedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_posedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB8_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB8_RWCLK1_posedge,
          TestSignal              => ADDB8_ipd,
          TestSignalName          => "ADDB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB8_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB8_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB8_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB8_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_posedge,
          TimingData              => Tmkr_DA0_RWCLK0_posedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_posedge,
          TimingData              => Tmkr_DA1_RWCLK0_posedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_posedge,
          TimingData              => Tmkr_DA2_RWCLK0_posedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_posedge,
          TimingData              => Tmkr_DA3_RWCLK0_posedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_posedge,
          TimingData              => Tmkr_DA4_RWCLK0_posedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_posedge,
          TimingData              => Tmkr_DA5_RWCLK0_posedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_posedge,
          TimingData              => Tmkr_DA6_RWCLK0_posedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_posedge,
          TimingData              => Tmkr_DA7_RWCLK0_posedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_posedge,
          TimingData              => Tmkr_EDA0_RWCLK0_posedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_posedge,
          TimingData              => Tmkr_DB0_RWCLK1_posedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_posedge,
          TimingData              => Tmkr_DB1_RWCLK1_posedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_posedge,
          TimingData              => Tmkr_DB2_RWCLK1_posedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_posedge,
          TimingData              => Tmkr_DB3_RWCLK1_posedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_posedge,
          TimingData              => Tmkr_DB4_RWCLK1_posedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_posedge,
          TimingData              => Tmkr_DB5_RWCLK1_posedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_posedge,
          TimingData              => Tmkr_DB6_RWCLK1_posedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_posedge,
          TimingData              => Tmkr_DB7_RWCLK1_posedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_posedge,
          TimingData              => Tmkr_EDB0_RWCLK1_posedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_posedge,
          PulseWidthLow           => tpw_RWCLK0_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_posedge,
          PulseWidthLow           => tpw_RWCLK1_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '0' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '0' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';


    BEGIN

      con_a := VitalAND2(OE0_ipd, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);


      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA0, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA0, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA1, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA1, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA1, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA1, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA1, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA1, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA1, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA1, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA1, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA2, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA2, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA2, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA2, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA2, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA2, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA2, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA2, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA2, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA3, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA3, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA3, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA3, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA3, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA3, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA3, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA3, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA3, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA4, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA4, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA4, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA4, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA4, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA4, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA4, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA4, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA4, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA5, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA5, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA5, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA5, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA5, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA5, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA5, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA5, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA5, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA6, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA6, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA6, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA6, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA6, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA6, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA6, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA6, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA6, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA7, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA7, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA7, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA7, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA7, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA7, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA7, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA7, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA7, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A8, "EDA0", DATA_A8,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_EDA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_EDA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_EDA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_EDA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_EDA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_EDA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_EDA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_EDA0, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_EDA0, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';

    BEGIN

      con_b := VitalAND2(OE1_ipd, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);


      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB0, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB0, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB1, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB1, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB1, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB1, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB1, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB1, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB1, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB1, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB1, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB2, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB2, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB2, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB2, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB2, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB2, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB2, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB2, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB2, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB3, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB3, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB3, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB3, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB3, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB3, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB3, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB3, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB3, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB4, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB4, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB4, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB4, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB4, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB4, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB4, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB4, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB4, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB5, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB5, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB5, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB5, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB5, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB5, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB5, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB5, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB5, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB6, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB6, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB6, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB6, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB6, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB6, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB6, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB6, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB6, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB7, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB7, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB7, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB7, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB7, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB7, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB7, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB7, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB7, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B8, "EDB0", DATA_B8,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_EDB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_EDB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_EDB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_EDB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_EDB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_EDB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_EDB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_EDB0, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_EDB0, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB512X9DAF_VITAL of RAMB512X9DAF is
   for VITAL
   end for;
end CFG_RAMB512X9DAF_VITAL;

----- CELL RAMB512X9DAF_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9DAF_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADDA0_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA0_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA1_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA2_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_DA8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA3_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA4_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA5_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA6_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA7_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_DA7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDA8_EDA0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB0_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB1_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB2_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB3_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB4_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB5_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB6_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB7_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_DB7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADDB8_EDB0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_DA7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE0_EDA0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE1_DB0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_DB7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE1_EDB0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN0_RWCLK0_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_WEN1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE0_RWCLK0_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      thold_CE0_RWCLK0_noedge_negedge     :	VitalDelayType   := 0.0 ns;
      tsetup_CE1_RWCLK1_noedge_negedge    :	VitalDelayType   := 0.0 ns;
      thold_CE1_RWCLK1_noedge_negedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDA8_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDA8_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA0_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA1_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA1_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA2_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA2_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA3_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA3_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA4_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA4_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA5_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA5_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA6_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA6_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DA7_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DA7_RWCLK0_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDA0_RWCLK0_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDA0_RWCLK0_noedge_negedge  :	VitalDelayType   := 0.0 ns;

      tsetup_ADDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADDB8_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_ADDB8_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;

      tsetup_DB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB0_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB1_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB1_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB2_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB2_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB3_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB3_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB4_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB4_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB5_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB5_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB6_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB6_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_DB7_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;
      thold_DB7_RWCLK1_noedge_negedge   :	VitalDelayType   := 0.0 ns;
      tsetup_EDB0_RWCLK1_noedge_negedge :	VitalDelayType   := 0.0 ns;
      thold_EDB0_RWCLK1_noedge_negedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK0_posedge                :	VitalDelayType   := 2.0 ns;
      tpw_RWCLK1_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_WEN1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK1                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_OE1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDA0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDA8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADDB0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADDB8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DA0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DA7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDA0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_DB0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_DB7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EDB0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN0                           :	in    STD_ULOGIC;
      WEN1                           :	in    STD_ULOGIC;
      RWCLK0                         :	in    STD_ULOGIC;
      RWCLK1                         :	in    STD_ULOGIC;
      OE0                            :	in    STD_ULOGIC;
      OE1                            :	in    STD_ULOGIC;
      ADDA0                          :	in    STD_ULOGIC;
      ADDA1                          :	in    STD_ULOGIC;
      ADDA2                          :	in    STD_ULOGIC;
      ADDA3                          :	in    STD_ULOGIC;
      ADDA4                          :	in    STD_ULOGIC;
      ADDA5                          :	in    STD_ULOGIC;
      ADDA6                          :	in    STD_ULOGIC;
      ADDA7                          :	in    STD_ULOGIC;
      ADDA8                          :	in    STD_ULOGIC;
      ADDB0                          :	in    STD_ULOGIC;
      ADDB1                          :	in    STD_ULOGIC;
      ADDB2                          :	in    STD_ULOGIC;
      ADDB3                          :	in    STD_ULOGIC;
      ADDB4                          :	in    STD_ULOGIC;
      ADDB5                          :	in    STD_ULOGIC;
      ADDB6                          :	in    STD_ULOGIC;
      ADDB7                          :	in    STD_ULOGIC;
      ADDB8                          :	in    STD_ULOGIC;
      DA0                            :	inout STD_ULOGIC;
      DA1                            :	inout STD_ULOGIC;
      DA2                            :	inout STD_ULOGIC;
      DA3                            :	inout STD_ULOGIC;
      DA4                            :	inout STD_ULOGIC;
      DA5                            :	inout STD_ULOGIC;
      DA6                            :	inout STD_ULOGIC;
      DA7                            :	inout STD_ULOGIC;
      EDA0                           :	inout STD_ULOGIC;
      DB0                            :	inout STD_ULOGIC;
      DB1                            :	inout STD_ULOGIC;
      DB2                            :	inout STD_ULOGIC;
      DB3                            :	inout STD_ULOGIC;
      DB4                            :	inout STD_ULOGIC;
      DB5                            :	inout STD_ULOGIC;
      DB6                            :	inout STD_ULOGIC;
      DB7                            :	inout STD_ULOGIC;
      EDB0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9DAF_1 : entity is TRUE;
end RAMB512X9DAF_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9DAF_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN0_ipd                :   std_logic :='X';
      SIGNAL WEN1_ipd                :   std_logic :='X';
      SIGNAL RWCLK0_ipd              :   std_logic :='X';
      SIGNAL RWCLK1_ipd              :   std_logic :='X';
      SIGNAL OE0_ipd                 :   std_logic :='X';
      SIGNAL OE1_ipd                 :   std_logic :='X';
      SIGNAL ADDA0_ipd               :   std_logic :='X';
      SIGNAL ADDA1_ipd               :   std_logic :='X';
      SIGNAL ADDA2_ipd               :   std_logic :='X';
      SIGNAL ADDA3_ipd               :   std_logic :='X';
      SIGNAL ADDA4_ipd               :   std_logic :='X';
      SIGNAL ADDA5_ipd               :   std_logic :='X';
      SIGNAL ADDA6_ipd               :   std_logic :='X';
      SIGNAL ADDA7_ipd               :   std_logic :='X';
      SIGNAL ADDA8_ipd               :   std_logic :='X';
      SIGNAL ADDB0_ipd               :   std_logic :='X';
      SIGNAL ADDB1_ipd               :   std_logic :='X';
      SIGNAL ADDB2_ipd               :   std_logic :='X';
      SIGNAL ADDB3_ipd               :   std_logic :='X';
      SIGNAL ADDB4_ipd               :   std_logic :='X';
      SIGNAL ADDB5_ipd               :   std_logic :='X';
      SIGNAL ADDB6_ipd               :   std_logic :='X';
      SIGNAL ADDB7_ipd               :   std_logic :='X';
      SIGNAL ADDB8_ipd               :   std_logic :='X';
      SIGNAL DA0_ipd                 :   std_logic :='X';
      SIGNAL DA1_ipd                 :   std_logic :='X';
      SIGNAL DA2_ipd                 :   std_logic :='X';
      SIGNAL DA3_ipd                 :   std_logic :='X';
      SIGNAL DA4_ipd                 :   std_logic :='X';
      SIGNAL DA5_ipd                 :   std_logic :='X';
      SIGNAL DA6_ipd                 :   std_logic :='X';
      SIGNAL DA7_ipd                 :   std_logic :='X';
      SIGNAL EDA0_ipd                :   std_logic :='X';
      SIGNAL DB0_ipd                 :   std_logic :='X';
      SIGNAL DB1_ipd                 :   std_logic :='X';
      SIGNAL DB2_ipd                 :   std_logic :='X';
      SIGNAL DB3_ipd                 :   std_logic :='X';
      SIGNAL DB4_ipd                 :   std_logic :='X';
      SIGNAL DB5_ipd                 :   std_logic :='X';
      SIGNAL DB6_ipd                 :   std_logic :='X';
      SIGNAL DB7_ipd                 :   std_logic :='X';
      SIGNAL EDB0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;
      SIGNAL data_out_b              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL rd_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL wr_clk0                 :   std_logic  := 'X';
      SIGNAL wr_clk1                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);
      SIGNAL wr_add_b                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);
      SIGNAL din_b                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512( init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN0_ipd,     WEN0,       tipd_WEN0);
	VitalWireDelay (WEN1_ipd,     WEN1,       tipd_WEN1);
	VitalWireDelay (RWCLK0_ipd,   RWCLK0,     tipd_RWCLK0);
	VitalWireDelay (RWCLK1_ipd,   RWCLK1,     tipd_RWCLK1);
	VitalWireDelay (OE0_ipd,      OE0,        tipd_OE0);
	VitalWireDelay (OE1_ipd,      OE1,        tipd_OE1);

	VitalWireDelay (ADDA0_ipd,    ADDA0,      tipd_ADDA0);
	VitalWireDelay (ADDA1_ipd,    ADDA1,      tipd_ADDA1);
	VitalWireDelay (ADDA2_ipd,    ADDA2,      tipd_ADDA2);
	VitalWireDelay (ADDA3_ipd,    ADDA3,      tipd_ADDA3);
	VitalWireDelay (ADDA4_ipd,    ADDA4,      tipd_ADDA4);
	VitalWireDelay (ADDA5_ipd,    ADDA5,      tipd_ADDA5);
	VitalWireDelay (ADDA6_ipd,    ADDA6,      tipd_ADDA6);
	VitalWireDelay (ADDA7_ipd,    ADDA7,      tipd_ADDA7);
	VitalWireDelay (ADDA8_ipd,    ADDA8,      tipd_ADDA8);

	VitalWireDelay (ADDB0_ipd,    ADDB0,      tipd_ADDB0);
	VitalWireDelay (ADDB1_ipd,    ADDB1,      tipd_ADDB1);
	VitalWireDelay (ADDB2_ipd,    ADDB2,      tipd_ADDB2);
	VitalWireDelay (ADDB3_ipd,    ADDB3,      tipd_ADDB3);
	VitalWireDelay (ADDB4_ipd,    ADDB4,      tipd_ADDB4);
	VitalWireDelay (ADDB5_ipd,    ADDB5,      tipd_ADDB5);
	VitalWireDelay (ADDB6_ipd,    ADDB6,      tipd_ADDB6);
	VitalWireDelay (ADDB7_ipd,    ADDB7,      tipd_ADDB7);
	VitalWireDelay (ADDB8_ipd,    ADDB8,      tipd_ADDB8);

	VitalWireDelay (DA0_ipd,      DA0,        tipd_DA0);
	VitalWireDelay (DA1_ipd,      DA1,        tipd_DA1);
	VitalWireDelay (DA2_ipd,      DA2,        tipd_DA2);
	VitalWireDelay (DA3_ipd,      DA3,        tipd_DA3);
	VitalWireDelay (DA4_ipd,      DA4,        tipd_DA4);
	VitalWireDelay (DA5_ipd,      DA5,        tipd_DA5);
	VitalWireDelay (DA6_ipd,      DA6,        tipd_DA6);
	VitalWireDelay (DA7_ipd,      DA7,        tipd_DA7);
	VitalWireDelay (EDA0_ipd,     EDA0,       tipd_EDA0);

	VitalWireDelay (DB0_ipd,      DB0,        tipd_DB0);
	VitalWireDelay (DB1_ipd,      DB1,        tipd_DB1);
	VitalWireDelay (DB2_ipd,      DB2,        tipd_DB2);
	VitalWireDelay (DB3_ipd,      DB3,        tipd_DB3);
	VitalWireDelay (DB4_ipd,      DB4,        tipd_DB4);
	VitalWireDelay (DB5_ipd,      DB5,        tipd_DB5);
	VitalWireDelay (DB6_ipd,      DB6,        tipd_DB6);
	VitalWireDelay (DB7_ipd,      DB7,        tipd_DB7);
	VitalWireDelay (EDB0_ipd,     EDB0,       tipd_EDB0);
      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE0_ipd, 
                                ADDA0_ipd, 
                                ADDA1_ipd, 
                                ADDA2_ipd, 
                                ADDA3_ipd, 
                                ADDA4_ipd, 
                                ADDA5_ipd, 
                                ADDA6_ipd, 
                                ADDA7_ipd, 
                                ADDA8_ipd, 
                                WEN0_ipd)

   begin

   if ( OE0_ipd = '0' and WEN0_ipd = '1') then
        rd_add_a(8) <= ADDA8_ipd;
        rd_add_a(7) <= ADDA7_ipd;
        rd_add_a(6) <= ADDA6_ipd;
        rd_add_a(5) <= ADDA5_ipd;
        rd_add_a(4) <= ADDA4_ipd;
        rd_add_a(3) <= ADDA3_ipd;
        rd_add_a(2) <= ADDA2_ipd;
        rd_add_a(1) <= ADDA1_ipd;
        rd_add_a(0) <= ADDA0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_add_b : process(OE1_ipd, 
                                ADDB0_ipd, 
                                ADDB1_ipd, 
                                ADDB2_ipd, 
                                ADDB3_ipd, 
                                ADDB4_ipd, 
                                ADDB5_ipd, 
                                ADDB6_ipd, 
                                ADDB7_ipd, 
                                ADDB8_ipd, 
                                WEN1_ipd)

   begin

   if ( OE1_ipd = '0' and WEN1_ipd = '1') then
        rd_add_b(8) <= ADDB8_ipd;
        rd_add_b(7) <= ADDB7_ipd;
        rd_add_b(6) <= ADDB6_ipd;
        rd_add_b(5) <= ADDB5_ipd;
        rd_add_b(4) <= ADDB4_ipd;
        rd_add_b(3) <= ADDB3_ipd;
        rd_add_b(2) <= ADDB2_ipd;
        rd_add_b(1) <= ADDB1_ipd;
        rd_add_b(0) <= ADDB0_ipd;
   else
	rd_add_b <= x_add_9;
   end if;
   end process wrapper_read_add_b;

   wrapper_write_clk_a : process(WEN0_ipd, RWCLK0_ipd)

   begin
    if (WEN0_ipd = '0' ) then
	wr_clk0 <= RWCLK0_ipd;
    else
	wr_clk0 <= '1';
    end if;
   end process;

   wrapper_write_clk_b : process(WEN1_ipd, RWCLK1_ipd)

   begin
    if (WEN1_ipd = '0' ) then
	wr_clk1 <= RWCLK1_ipd;
    else
	wr_clk1 <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADDA8_ipd,
                            ADDA7_ipd,
                            ADDA6_ipd,
                            ADDA5_ipd,
                            ADDA4_ipd,
                            ADDA3_ipd,
                            ADDA2_ipd,
                            ADDA1_ipd,
                            ADDA0_ipd
                            )

    begin
        wr_add_a(8) <= ADDA8_ipd;
        wr_add_a(7) <= ADDA7_ipd;
        wr_add_a(6) <= ADDA6_ipd;
        wr_add_a(5) <= ADDA5_ipd;
        wr_add_a(4) <= ADDA4_ipd;
        wr_add_a(3) <= ADDA3_ipd;
        wr_add_a(2) <= ADDA2_ipd;
        wr_add_a(1) <= ADDA1_ipd;
        wr_add_a(0) <= ADDA0_ipd;
   end process;

   write_address_b : process(
                            ADDB8_ipd,
                            ADDB7_ipd,
                            ADDB6_ipd,
                            ADDB5_ipd,
                            ADDB4_ipd,
                            ADDB3_ipd,
                            ADDB2_ipd,
                            ADDB1_ipd,
                            ADDB0_ipd
                            )

    begin
        wr_add_b(8) <= ADDB8_ipd;
        wr_add_b(7) <= ADDB7_ipd;
        wr_add_b(6) <= ADDB6_ipd;
        wr_add_b(5) <= ADDB5_ipd;
        wr_add_b(4) <= ADDB4_ipd;
        wr_add_b(3) <= ADDB3_ipd;
        wr_add_b(2) <= ADDB2_ipd;
        wr_add_b(1) <= ADDB1_ipd;
        wr_add_b(0) <= ADDB0_ipd;
   end process;

   wrapper_write_data_a : process(WEN0_ipd, 
                                  EDA0_ipd, 
                                  DA7_ipd, 
                                  DA6_ipd, 
                                  DA5_ipd, 
                                  DA4_ipd, 
                                  DA3_ipd, 
                                  DA2_ipd, 
                                  DA1_ipd, 
                                  DA0_ipd)

   begin
    if (WEN0_ipd = '0') then
        din_a(8)  <= EDA0_ipd;
        din_a(7)  <= DA7_ipd;
        din_a(6)  <= DA6_ipd;
        din_a(5)  <= DA5_ipd;
        din_a(4)  <= DA4_ipd;
        din_a(3)  <= DA3_ipd;
        din_a(2)  <= DA2_ipd;
        din_a(1)  <= DA1_ipd;
        din_a(0)  <= DA0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

   wrapper_write_data_b : process(WEN1_ipd, 
                                  EDA0_ipd, 
                                  DB7_ipd, 
                                  DB6_ipd, 
                                  DB5_ipd, 
                                  DB4_ipd, 
                                  DB3_ipd, 
                                  DB2_ipd, 
                                  DB1_ipd, 
                                  DB0_ipd)

   begin
    if (WEN1_ipd = '0') then
        din_b(8) <= EDB0_ipd;
        din_b(7)  <= DB7_ipd;
        din_b(6)  <= DB6_ipd;
        din_b(5)  <= DB5_ipd;
        din_b(4)  <= DB4_ipd;
        din_b(3)  <= DB3_ipd;
        din_b(2)  <= DB2_ipd;
        din_b(1)  <= DB1_ipd;
        din_b(0)  <= DB0_ipd;
    else
	din_b <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9DAF_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk0, wr_clk1,
                            din_a, din_b,
                            rd_add_a, rd_add_b,
                            wr_add_a, wr_add_b)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
        variable tempaddr_b                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 
	variable rd_address_b                : integer     := 0;

        variable Tviol_WEN0_RWCLK0_posedge   : std_ulogic  := '0';
        variable Tviol_WEN1_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tviol_CE0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_CE1_RWCLK1_posedge    : std_ulogic  := '0';

        variable Tviol_ADDA0_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA1_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA2_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA3_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA4_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA5_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA6_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA7_RWCLK0_posedge  : std_ulogic  := '0';
        variable Tviol_ADDA8_RWCLK0_posedge  : std_ulogic  := '0';

        variable Tviol_ADDB0_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB1_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB2_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB3_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB4_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB5_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB6_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB7_RWCLK1_posedge  : std_ulogic  := '0';
        variable Tviol_ADDB8_RWCLK1_posedge  : std_ulogic  := '0';

        variable Tviol_DA0_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA1_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA2_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA3_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA4_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA5_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA6_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_DA7_RWCLK0_posedge    : std_ulogic  := '0';
        variable Tviol_EDA0_RWCLK0_posedge   : std_ulogic  := '0';

        variable Tviol_DB0_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB1_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB2_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB3_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB4_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB5_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB6_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_DB7_RWCLK1_posedge    : std_ulogic  := '0';
        variable Tviol_EDB0_RWCLK1_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_WEN1_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_CE1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDA0_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA1_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA2_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA3_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA4_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA5_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA6_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA7_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDA8_RWCLK0_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADDB0_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB1_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB2_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB3_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB4_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB5_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB6_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB7_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADDB8_RWCLK1_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DA0_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA1_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA2_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA3_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA4_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA5_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA6_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DA7_RWCLK0_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDA0_RWCLK0_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_DB0_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB1_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB2_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB3_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB4_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB5_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB6_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_DB7_RWCLK1_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_EDB0_RWCLK1_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK0                : std_ulogic := '0';
        variable PInfo_RWCLK0                : VitalPeriodDataType := VitalPeriodDataInit;

        variable PViol_RWCLK1                : std_ulogic := '0';
        variable PInfo_RWCLK1                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN0_RWCLK0_posedge,
          TimingData              => Tmkr_WEN0_RWCLK0_posedge,
          TestSignal              => WEN0_ipd,
          TestSignalName          => "WEN0",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_WEN0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_WEN0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_WEN0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN1_RWCLK1_posedge,
          TimingData              => Tmkr_WEN1_RWCLK1_posedge,
          TestSignal              => WEN1_ipd,
          TestSignalName          => "WEN1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_WEN1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_WEN1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_WEN1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_WEN1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA0_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA0_RWCLK0_posedge,
          TestSignal              => ADDA0_ipd,
          TestSignalName          => "ADDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA1_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA1_RWCLK0_posedge,
          TestSignal              => ADDA1_ipd,
          TestSignalName          => "ADDA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA2_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA2_RWCLK0_posedge,
          TestSignal              => ADDA2_ipd,
          TestSignalName          => "ADDA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA3_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA3_RWCLK0_posedge,
          TestSignal              => ADDA3_ipd,
          TestSignalName          => "ADDA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA4_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA4_RWCLK0_posedge,
          TestSignal              => ADDA4_ipd,
          TestSignalName          => "ADDA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA5_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA5_RWCLK0_posedge,
          TestSignal              => ADDA5_ipd,
          TestSignalName          => "ADDA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA6_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA6_RWCLK0_posedge,
          TestSignal              => ADDA6_ipd,
          TestSignalName          => "ADDA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA7_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA7_RWCLK0_posedge,
          TestSignal              => ADDA7_ipd,
          TestSignalName          => "ADDA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDA8_RWCLK0_posedge,
          TimingData              => Tmkr_ADDA8_RWCLK0_posedge,
          TestSignal              => ADDA8_ipd,
          TestSignalName          => "ADDA8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDA8_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_ADDA8_RWCLK0_noedge_negedge,
          HoldLow                 => thold_ADDA8_RWCLK0_noedge_negedge,
          HoldHigh                => thold_ADDA8_RWCLK0_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB0_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB0_RWCLK1_posedge,
          TestSignal              => ADDB0_ipd,
          TestSignalName          => "ADDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB1_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB1_RWCLK1_posedge,
          TestSignal              => ADDB1_ipd,
          TestSignalName          => "ADDB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB2_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB2_RWCLK1_posedge,
          TestSignal              => ADDB2_ipd,
          TestSignalName          => "ADDB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB3_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB3_RWCLK1_posedge,
          TestSignal              => ADDB3_ipd,
          TestSignalName          => "ADDB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB4_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB4_RWCLK1_posedge,
          TestSignal              => ADDB4_ipd,
          TestSignalName          => "ADDB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB5_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB5_RWCLK1_posedge,
          TestSignal              => ADDB5_ipd,
          TestSignalName          => "ADDB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB6_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB6_RWCLK1_posedge,
          TestSignal              => ADDB6_ipd,
          TestSignalName          => "ADDB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB7_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB7_RWCLK1_posedge,
          TestSignal              => ADDB7_ipd,
          TestSignalName          => "ADDB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADDB8_RWCLK1_posedge,
          TimingData              => Tmkr_ADDB8_RWCLK1_posedge,
          TestSignal              => ADDB8_ipd,
          TestSignalName          => "ADDB8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADDB8_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_ADDB8_RWCLK1_noedge_negedge,
          HoldLow                 => thold_ADDB8_RWCLK1_noedge_negedge,
          HoldHigh                => thold_ADDB8_RWCLK1_noedge_negedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA0_RWCLK0_posedge,
          TimingData              => Tmkr_DA0_RWCLK0_posedge,
          TestSignal              => DA0_ipd,
          TestSignalName          => "DA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA1_RWCLK0_posedge,
          TimingData              => Tmkr_DA1_RWCLK0_posedge,
          TestSignal              => DA1_ipd,
          TestSignalName          => "DA1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA1_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA1_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA1_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA1_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA2_RWCLK0_posedge,
          TimingData              => Tmkr_DA2_RWCLK0_posedge,
          TestSignal              => DA2_ipd,
          TestSignalName          => "DA2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA2_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA2_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA2_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA2_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA3_RWCLK0_posedge,
          TimingData              => Tmkr_DA3_RWCLK0_posedge,
          TestSignal              => DA3_ipd,
          TestSignalName          => "DA3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA3_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA3_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA3_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA3_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA4_RWCLK0_posedge,
          TimingData              => Tmkr_DA4_RWCLK0_posedge,
          TestSignal              => DA4_ipd,
          TestSignalName          => "DA4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA4_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA4_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA4_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA4_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA5_RWCLK0_posedge,
          TimingData              => Tmkr_DA5_RWCLK0_posedge,
          TestSignal              => DA5_ipd,
          TestSignalName          => "DA5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA5_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA5_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA5_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA5_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA6_RWCLK0_posedge,
          TimingData              => Tmkr_DA6_RWCLK0_posedge,
          TestSignal              => DA6_ipd,
          TestSignalName          => "DA6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA6_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA6_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA6_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA6_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DA7_RWCLK0_posedge,
          TimingData              => Tmkr_DA7_RWCLK0_posedge,
          TestSignal              => DA7_ipd,
          TestSignalName          => "DA7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DA7_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_DA7_RWCLK0_noedge_negedge,
          HoldLow                 => thold_DA7_RWCLK0_noedge_negedge,
          HoldHigh                => thold_DA7_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDA0_RWCLK0_posedge,
          TimingData              => Tmkr_EDA0_RWCLK0_posedge,
          TestSignal              => EDA0_ipd,
          TestSignalName          => "EDA0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK0",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDA0_RWCLK0_noedge_negedge,
          SetupLow                => tsetup_EDA0_RWCLK0_noedge_negedge,
          HoldLow                 => thold_EDA0_RWCLK0_noedge_negedge,
          HoldHigh                => thold_EDA0_RWCLK0_noedge_negedge,
          CheckEnabled            => TO_X01(WEN0_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB0_RWCLK1_posedge,
          TimingData              => Tmkr_DB0_RWCLK1_posedge,
          TestSignal              => DB0_ipd,
          TestSignalName          => "DB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB1_RWCLK1_posedge,
          TimingData              => Tmkr_DB1_RWCLK1_posedge,
          TestSignal              => DB1_ipd,
          TestSignalName          => "DB1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB1_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB1_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB1_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB1_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB2_RWCLK1_posedge,
          TimingData              => Tmkr_DB2_RWCLK1_posedge,
          TestSignal              => DB2_ipd,
          TestSignalName          => "DB2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK0_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB2_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB2_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB2_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB2_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB3_RWCLK1_posedge,
          TimingData              => Tmkr_DB3_RWCLK1_posedge,
          TestSignal              => DB3_ipd,
          TestSignalName          => "DB3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB3_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB3_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB3_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB3_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB4_RWCLK1_posedge,
          TimingData              => Tmkr_DB4_RWCLK1_posedge,
          TestSignal              => DB4_ipd,
          TestSignalName          => "DB4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB4_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB4_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB4_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB4_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB5_RWCLK1_posedge,
          TimingData              => Tmkr_DB5_RWCLK1_posedge,
          TestSignal              => DB5_ipd,
          TestSignalName          => "DB5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB5_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB5_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB5_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB5_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB6_RWCLK1_posedge,
          TimingData              => Tmkr_DB6_RWCLK1_posedge,
          TestSignal              => DB6_ipd,
          TestSignalName          => "DB6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB6_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB6_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB6_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB6_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_DB7_RWCLK1_posedge,
          TimingData              => Tmkr_DB7_RWCLK1_posedge,
          TestSignal              => DB7_ipd,
          TestSignalName          => "DB7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_DB7_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_DB7_RWCLK1_noedge_negedge,
          HoldLow                 => thold_DB7_RWCLK1_noedge_negedge,
          HoldHigh                => thold_DB7_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EDB0_RWCLK1_posedge,
          TimingData              => Tmkr_EDB0_RWCLK1_posedge,
          TestSignal              => EDB0_ipd,
          TestSignalName          => "EDB0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK1_ipd,
          RefSignalName           => "RWCLK1",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EDB0_RWCLK1_noedge_negedge,
          SetupLow                => tsetup_EDB0_RWCLK1_noedge_negedge,
          HoldLow                 => thold_EDB0_RWCLK1_noedge_negedge,
          HoldHigh                => thold_EDB0_RWCLK1_noedge_negedge,
          CheckEnabled            => TO_X01(WEN1_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK0,
          PeriodData              => PInfo_RWCLK0,
          TestSignal              => RWCLK0_ipd,
          TestSignalName          => "RWCLK0",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK0_posedge,
          PulseWidthLow           => tpw_RWCLK0_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK1,
          PeriodData              => PInfo_RWCLK1,
          TestSignal              => RWCLK1_ipd,
          TestSignalName          => "RWCLK1",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK1_posedge,
          PulseWidthLow           => tpw_RWCLK1_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9DAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk0'EVENT and wr_clk0 = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk0'EVENT and wr_clk0 = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    -- Port B
    if ( wr_clk1'EVENT and wr_clk1 = '0' and vecX(wr_add_b)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port B."
        severity note ;

    end if;

    if ( wr_clk1'EVENT and wr_clk1 = '0' and not vecX(wr_add_b) ) then
	tempaddr_b := vec2int(wr_add_b);
	memory_array(tempaddr_b) <= din_b;
    end if;

    if( not vecX(rd_add_b) ) then
	rd_address_b := vec2int(rd_add_b);
	data_out_b <= memory_array(rd_address_b);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK0_ipd, OE0_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE OE0_inverted  : std_logic := 'Z';


    BEGIN

      OE0_inverted := NOT (OE0_ipd); 
      con_a := VitalAND2(OE0_inverted, WEN0_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);


      VitalPathDelay01Z ( DA0, GLITCH_DATA_A0, "DA0", DATA_A0,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA0, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA0, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA1, GLITCH_DATA_A1, "DA1", DATA_A1,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA1, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA1, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA1, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA1, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA1, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA1, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA1, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA1, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA1, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA2, GLITCH_DATA_A2, "DA2", DATA_A2,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA2, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA2, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA2, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA2, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA2, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA2, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA2, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA2, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA2, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA3, GLITCH_DATA_A3, "DA3", DATA_A3,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA3, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA3, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA3, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA3, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA3, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA3, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA3, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA3, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA3, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA4, GLITCH_DATA_A4, "DA4", DATA_A4,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA4, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA4, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA4, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA4, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA4, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA4, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA4, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA4, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA4, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA5, GLITCH_DATA_A5, "DA5", DATA_A5,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA5, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA5, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA5, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA5, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA5, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA5, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA5, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA5, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA5, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA6, GLITCH_DATA_A6, "DA6", DATA_A6,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA6, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA6, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA6, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA6, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA6, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA6, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA6, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA6, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA6, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DA7, GLITCH_DATA_A7, "DA7", DATA_A7,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_DA7, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_DA7, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_DA7, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_DA7, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_DA7, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_DA7, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_DA7, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_DA7, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_DA7, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_DA7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDA0, GLITCH_DATA_A8, "EDA0", DATA_A8,
        Paths => (
        0 => ( ADDA0_ipd'LAST_EVENT, tpd_ADDA0_EDA0, TRUE),
        1 => ( ADDA1_ipd'LAST_EVENT, tpd_ADDA1_EDA0, TRUE),
        2 => ( ADDA2_ipd'LAST_EVENT, tpd_ADDA2_EDA0, TRUE),
        3 => ( ADDA3_ipd'LAST_EVENT, tpd_ADDA3_EDA0, TRUE),
        4 => ( ADDA4_ipd'LAST_EVENT, tpd_ADDA4_EDA0, TRUE),
        5 => ( ADDA5_ipd'LAST_EVENT, tpd_ADDA5_EDA0, TRUE),
        6 => ( ADDA6_ipd'LAST_EVENT, tpd_ADDA6_EDA0, TRUE),
        7 => ( ADDA7_ipd'LAST_EVENT, tpd_ADDA7_EDA0, TRUE),
        8 => ( ADDA8_ipd'LAST_EVENT, tpd_ADDA8_EDA0, TRUE),
        9 => ( OE0_ipd'LAST_EVENT, tpd_OE0_EDA0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

    VitalBehavior_ReadB : process(data_out_b, RWCLK1_ipd, OE1_ipd)

    VARIABLE GLITCH_DATA_B0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_B8 : VitalGlitchDataType;
    VARIABLE con_b : std_logic ;
    VARIABLE DATA_B0  : std_logic := 'Z';
    VARIABLE DATA_B1  : std_logic := 'Z';
    VARIABLE DATA_B2  : std_logic := 'Z';
    VARIABLE DATA_B3  : std_logic := 'Z';
    VARIABLE DATA_B4  : std_logic := 'Z';
    VARIABLE DATA_B5  : std_logic := 'Z';
    VARIABLE DATA_B6  : std_logic := 'Z';
    VARIABLE DATA_B7  : std_logic := 'Z';
    VARIABLE DATA_B8  : std_logic := 'Z';
    VARIABLE OE1_inverted  : std_logic := 'Z';

    BEGIN

      OE1_inverted := NOT (OE1_ipd);
      con_b := VitalAND2(OE1_inverted, WEN1_ipd);

      DATA_B0  := VITALBUFIF1(data_out_b(0),con_b);
      DATA_B1  := VITALBUFIF1(data_out_b(1),con_b);
      DATA_B2  := VITALBUFIF1(data_out_b(2),con_b);
      DATA_B3  := VITALBUFIF1(data_out_b(3),con_b);
      DATA_B4  := VITALBUFIF1(data_out_b(4),con_b);
      DATA_B5  := VITALBUFIF1(data_out_b(5),con_b);
      DATA_B6  := VITALBUFIF1(data_out_b(6),con_b);
      DATA_B7  := VITALBUFIF1(data_out_b(7),con_b);
      DATA_B8  := VITALBUFIF1(data_out_b(8),con_b);


      VitalPathDelay01Z ( DB0, GLITCH_DATA_B0, "DB0", DATA_B0,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB0, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB0, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB1, GLITCH_DATA_B1, "DB1", DATA_B1,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB1, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB1, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB1, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB1, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB1, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB1, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB1, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB1, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB1, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB2, GLITCH_DATA_B2, "DB2", DATA_B2,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB2, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB2, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB2, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB2, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB2, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB2, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB2, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB2, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB2, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB3, GLITCH_DATA_B3, "DB3", DATA_B3,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB3, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB3, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB3, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB3, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB3, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB3, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB3, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB3, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB3, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB4, GLITCH_DATA_B4, "DB4", DATA_B4,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB4, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB4, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB4, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB4, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB4, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB4, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB4, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB4, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB4, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB5, GLITCH_DATA_B5, "DB5", DATA_B5,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB5, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB5, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB5, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB5, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB5, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB5, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB5, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB5, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB5, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB6, GLITCH_DATA_B6, "DB6", DATA_B6,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB6, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB6, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB6, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB6, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB6, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB6, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB6, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB6, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB6, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( DB7, GLITCH_DATA_B7, "DB7", DATA_B7,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_DB7, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_DB7, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_DB7, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_DB7, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_DB7, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_DB7, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_DB7, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_DB7, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_DB7, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_DB7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( EDB0, GLITCH_DATA_B8, "EDB0", DATA_B8,
        Paths => (
        0 => ( ADDB0_ipd'LAST_EVENT, tpd_ADDB0_EDB0, TRUE),
        1 => ( ADDB1_ipd'LAST_EVENT, tpd_ADDB1_EDB0, TRUE),
        2 => ( ADDB2_ipd'LAST_EVENT, tpd_ADDB2_EDB0, TRUE),
        3 => ( ADDB3_ipd'LAST_EVENT, tpd_ADDB3_EDB0, TRUE),
        4 => ( ADDB4_ipd'LAST_EVENT, tpd_ADDB4_EDB0, TRUE),
        5 => ( ADDB5_ipd'LAST_EVENT, tpd_ADDB5_EDB0, TRUE),
        6 => ( ADDB6_ipd'LAST_EVENT, tpd_ADDB6_EDB0, TRUE),
        7 => ( ADDB7_ipd'LAST_EVENT, tpd_ADDB7_EDB0, TRUE),
        8 => ( ADDB8_ipd'LAST_EVENT, tpd_ADDB8_EDB0, TRUE),
        9 => ( OE1_ipd'LAST_EVENT, tpd_OE1_EDB0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

   END process VitalBehavior_ReadB;

end VITAL;

configuration CFG_RAMB512X9DAF_1_VITAL of RAMB512X9DAF_1 is
   for VITAL
   end for;
end CFG_RAMB512X9DAF_1_VITAL;

----- CELL RAMB256X18SSR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18SSR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK_D0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D8                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D9                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D10                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D11                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D12                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D13                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D14                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D15                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_ED0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_ED1                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE_RWCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D9_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D9_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D10_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D10_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D11_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D11_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D12_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D12_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D13_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D13_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D14_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D14_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D15_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D15_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED1_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      CE                            :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      D8                            :	inout STD_ULOGIC;
      D9                            :	inout STD_ULOGIC;
      D10                           :	inout STD_ULOGIC;
      D11                           :	inout STD_ULOGIC;
      D12                           :	inout STD_ULOGIC;
      D13                           :	inout STD_ULOGIC;
      D14                           :	inout STD_ULOGIC;
      D15                           :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC;
      ED1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18SSR : entity is TRUE;
end RAMB256X18SSR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18SSR is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL CE_ipd                 :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL D8_ipd                 :   std_logic :='X';
      SIGNAL D9_ipd                 :   std_logic :='X';
      SIGNAL D10_ipd                :   std_logic :='X';
      SIGNAL D11_ipd                :   std_logic :='X';
      SIGNAL D12_ipd                :   std_logic :='X';
      SIGNAL D13_ipd                :   std_logic :='X';
      SIGNAL D14_ipd                :   std_logic :='X';
      SIGNAL D15_ipd                :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';
      SIGNAL ED1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL rd_clk                 :   std_logic  := 'X';

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (CE_ipd,      CE,        tipd_CE);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (D8_ipd,      D8,        tipd_D8);
	VitalWireDelay (D9_ipd,      D9,        tipd_D9);
	VitalWireDelay (D10_ipd,     D10,       tipd_D10);
	VitalWireDelay (D11_ipd,     D11,       tipd_D11);
	VitalWireDelay (D12_ipd,     D12,       tipd_D12);
	VitalWireDelay (D13_ipd,     D13,       tipd_D13);
	VitalWireDelay (D14_ipd,     D14,       tipd_D14);
	VitalWireDelay (D15_ipd,     D15,       tipd_D15);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);
	VitalWireDelay (ED1_ipd,     ED1,       tipd_ED1);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '1' and WEN_ipd = '1') then
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   --wrapper_read_clk_a : process(OE_ipd, RWCLK_ipd, CE_ipd, WEN_ipd)  --071804
   wrapper_read_clk_a : process(RWCLK_ipd)  --071804
   begin
    if rising_edge (RWCLK_ipd)   then  --071804
      if (OE_ipd = '1' and WEN_ipd = '1' and CE_ipd ='0') then
	  rd_clk <= RWCLK_ipd;
      else
	  rd_clk <= '0';
      end if;
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd, CE_ipd)
   -- wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd) --071804
   wrapper_write_clk_a : process(RWCLK_ipd) --071804

   begin
--    if (WEN_ipd = '0' and CE_ipd = '0' ) then
    if rising_edge (RWCLK_ipd) then  --071804
      if (WEN_ipd = '0') then
	  wr_clk <= RWCLK_ipd;
      else
	  wr_clk <= '0';
      end if;
    end if;
   end process;

   write_address_a : process(
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED1_ipd, 
                                  ED0_ipd, 
                                  D15_ipd, 
                                  D14_ipd, 
                                  D13_ipd, 
                                  D12_ipd, 
                                  D11_ipd, 
                                  D10_ipd, 
                                  D9_ipd, 
                                  D8_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(17) <= ED1_ipd;
        din_a(16) <= ED0_ipd;
        din_a(15) <= D15_ipd;
        din_a(14) <= D14_ipd;
        din_a(13) <= D13_ipd;
        din_a(12) <= D12_ipd;
        din_a(11) <= D11_ipd;
        din_a(10) <= D10_ipd;
        din_a(9)  <= D9_ipd;
        din_a(8)  <= D8_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18SSR Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk,
                            rd_clk,
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_CE_RWCLK_posedge    : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D8_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D9_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D10_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D11_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D12_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D13_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D14_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D15_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED1_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D8_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D9_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D10_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D11_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D12_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D13_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D14_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D15_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED1_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK               : std_ulogic := '0';
        variable PInfo_RWCLK               : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_RWCLK_posedge,
          TimingData              => Tmkr_CE_RWCLK_posedge,
          TestSignal              => CE_ipd,
          TestSignalName          => "CE",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE_RWCLK_noedge_posedge,
          SetupLow                => tsetup_CE_RWCLK_noedge_posedge,
          HoldLow                 => thold_CE_RWCLK_noedge_posedge,
          HoldHigh                => thold_CE_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D8_RWCLK_posedge,
          TimingData              => Tmkr_D8_RWCLK_posedge,
          TestSignal              => D8_ipd,
          TestSignalName          => "D8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D8_RWCLK_noedge_posedge,
          HoldLow                 => thold_D8_RWCLK_noedge_posedge,
          HoldHigh                => thold_D8_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D9_RWCLK_posedge,
          TimingData              => Tmkr_D9_RWCLK_posedge,
          TestSignal              => D9_ipd,
          TestSignalName          => "D9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D9_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D9_RWCLK_noedge_posedge,
          HoldLow                 => thold_D9_RWCLK_noedge_posedge,
          HoldHigh                => thold_D9_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D10_RWCLK_posedge,
          TimingData              => Tmkr_D10_RWCLK_posedge,
          TestSignal              => D10_ipd,
          TestSignalName          => "D10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D10_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D10_RWCLK_noedge_posedge,
          HoldLow                 => thold_D10_RWCLK_noedge_posedge,
          HoldHigh                => thold_D10_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D11_RWCLK_posedge,
          TimingData              => Tmkr_D11_RWCLK_posedge,
          TestSignal              => D11_ipd,
          TestSignalName          => "D11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D11_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D11_RWCLK_noedge_posedge,
          HoldLow                 => thold_D11_RWCLK_noedge_posedge,
          HoldHigh                => thold_D11_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D12_RWCLK_posedge,
          TimingData              => Tmkr_D12_RWCLK_posedge,
          TestSignal              => D12_ipd,
          TestSignalName          => "D12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D12_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D12_RWCLK_noedge_posedge,
          HoldLow                 => thold_D12_RWCLK_noedge_posedge,
          HoldHigh                => thold_D12_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D13_RWCLK_posedge,
          TimingData              => Tmkr_D13_RWCLK_posedge,
          TestSignal              => D13_ipd,
          TestSignalName          => "D13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D13_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D13_RWCLK_noedge_posedge,
          HoldLow                 => thold_D13_RWCLK_noedge_posedge,
          HoldHigh                => thold_D13_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D13_RWCLK_posedge,
          TimingData              => Tmkr_D13_RWCLK_posedge,
          TestSignal              => D13_ipd,
          TestSignalName          => "D13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D13_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D13_RWCLK_noedge_posedge,
          HoldLow                 => thold_D13_RWCLK_noedge_posedge,
          HoldHigh                => thold_D13_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D14_RWCLK_posedge,
          TimingData              => Tmkr_D14_RWCLK_posedge,
          TestSignal              => D14_ipd,
          TestSignalName          => "D14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D14_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D14_RWCLK_noedge_posedge,
          HoldLow                 => thold_D14_RWCLK_noedge_posedge,
          HoldHigh                => thold_D14_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D15_RWCLK_posedge,
          TimingData              => Tmkr_D15_RWCLK_posedge,
          TestSignal              => D15_ipd,
          TestSignalName          => "D15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D15_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D15_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED1_RWCLK_posedge,
          TimingData              => Tmkr_ED1_RWCLK_posedge,
          TestSignal              => ED1_ipd,
          TestSignalName          => "ED1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk'EVENT and rd_clk = '1' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VITALBehavior_Write; 


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10 : std_logic := 'Z';
    VARIABLE DATA_A11 : std_logic := 'Z';
    VARIABLE DATA_A12 : std_logic := 'Z';
    VARIABLE DATA_A13 : std_logic := 'Z';
    VARIABLE DATA_A14 : std_logic := 'Z';
    VARIABLE DATA_A15 : std_logic := 'Z';
    VARIABLE DATA_A16 : std_logic := 'Z';
    VARIABLE DATA_A17 : std_logic := 'Z';


    BEGIN

      con_a := VitalAND2(OE_ipd, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10 := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11 := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12 := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13 := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14 := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15 := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16 := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17 := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D1, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D2, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D3, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D4, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D5, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D6, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D7, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D8, GLITCH_DATA_A8, "DA8", DATA_A8,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D8, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D9, GLITCH_DATA_A9, "D9", DATA_A9,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D9, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D10, GLITCH_DATA_A10, "D10", DATA_A10,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D10, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D11, GLITCH_DATA_A11, "D11", DATA_A11,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D11, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D12, GLITCH_DATA_A12, "D12", DATA_A12,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D12, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D13, GLITCH_DATA_A13, "D13", DATA_A13,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D13, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D14, GLITCH_DATA_A14, "D14", DATA_A14,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D14, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D15, GLITCH_DATA_A15, "D15", DATA_A15,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D15, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A16, "ED0", DATA_A16,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_ED0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED1, GLITCH_DATA_A17, "ED1", DATA_A17,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_ED1, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_ED1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB256X18SSR_VITAL of RAMB256X18SSR is
   for VITAL
   end for;
end CFG_RAMB256X18SSR_VITAL;

----- CELL RAMB256X18SSR_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18SSR_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK_D0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D8                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D9                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D10                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D11                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D12                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D13                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D14                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D15                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_ED0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_ED1                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE_RWCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D9_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D9_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D10_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D10_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D11_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D11_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D12_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D12_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D13_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D13_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D14_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D14_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D15_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D15_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED1_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      CE                            :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      D8                            :	inout STD_ULOGIC;
      D9                            :	inout STD_ULOGIC;
      D10                           :	inout STD_ULOGIC;
      D11                           :	inout STD_ULOGIC;
      D12                           :	inout STD_ULOGIC;
      D13                           :	inout STD_ULOGIC;
      D14                           :	inout STD_ULOGIC;
      D15                           :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC;
      ED1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18SSR_1 : entity is TRUE;
end RAMB256X18SSR_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18SSR_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL CE_ipd                 :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL D8_ipd                 :   std_logic :='X';
      SIGNAL D9_ipd                 :   std_logic :='X';
      SIGNAL D10_ipd                :   std_logic :='X';
      SIGNAL D11_ipd                :   std_logic :='X';
      SIGNAL D12_ipd                :   std_logic :='X';
      SIGNAL D13_ipd                :   std_logic :='X';
      SIGNAL D14_ipd                :   std_logic :='X';
      SIGNAL D15_ipd                :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';
      SIGNAL ED1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL rd_clk                 :   std_logic  := 'X';

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (CE_ipd,      CE,        tipd_CE);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (D8_ipd,      D8,        tipd_D8);
	VitalWireDelay (D9_ipd,      D9,        tipd_D9);
	VitalWireDelay (D10_ipd,     D10,       tipd_D10);
	VitalWireDelay (D11_ipd,     D11,       tipd_D11);
	VitalWireDelay (D12_ipd,     D12,       tipd_D12);
	VitalWireDelay (D13_ipd,     D13,       tipd_D13);
	VitalWireDelay (D14_ipd,     D14,       tipd_D14);
	VitalWireDelay (D15_ipd,     D15,       tipd_D15);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);
	VitalWireDelay (ED1_ipd,     ED1,       tipd_ED1);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '0' and WEN_ipd = '1') then
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_clk_a : process(OE_ipd, RWCLK_ipd, CE_ipd, WEN_ipd)

   begin
    if (OE_ipd = '0' and WEN_ipd = '1' and CE_ipd ='0') then
	rd_clk <= RWCLK_ipd;
    else
	rd_clk <= '0';
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd, CE_ipd)
   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd)

   begin
--    if (WEN_ipd = '0' and CE_ipd = '0' ) then
    if (WEN_ipd = '0') then
	wr_clk <= RWCLK_ipd;
    else
	wr_clk <= '0';
    end if;
   end process;

   write_address_a : process(
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED1_ipd, 
                                  ED0_ipd, 
                                  D15_ipd, 
                                  D14_ipd, 
                                  D13_ipd, 
                                  D12_ipd, 
                                  D11_ipd, 
                                  D10_ipd, 
                                  D9_ipd, 
                                  D8_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(17) <= ED1_ipd;
        din_a(16) <= ED0_ipd;
        din_a(15) <= D15_ipd;
        din_a(14) <= D14_ipd;
        din_a(13) <= D13_ipd;
        din_a(12) <= D12_ipd;
        din_a(11) <= D11_ipd;
        din_a(10) <= D10_ipd;
        din_a(9)  <= D9_ipd;
        din_a(8)  <= D8_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18SSR_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk,
                            rd_clk,
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_CE_RWCLK_posedge    : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D8_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D9_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D10_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D11_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D12_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D13_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D14_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D15_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED1_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D8_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D9_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D10_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D11_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D12_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D13_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D14_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D15_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED1_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK               : std_ulogic := '0';
        variable PInfo_RWCLK               : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_RWCLK_posedge,
          TimingData              => Tmkr_CE_RWCLK_posedge,
          TestSignal              => CE_ipd,
          TestSignalName          => "CE",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE_RWCLK_noedge_posedge,
          SetupLow                => tsetup_CE_RWCLK_noedge_posedge,
          HoldLow                 => thold_CE_RWCLK_noedge_posedge,
          HoldHigh                => thold_CE_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D8_RWCLK_posedge,
          TimingData              => Tmkr_D8_RWCLK_posedge,
          TestSignal              => D8_ipd,
          TestSignalName          => "D8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D8_RWCLK_noedge_posedge,
          HoldLow                 => thold_D8_RWCLK_noedge_posedge,
          HoldHigh                => thold_D8_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D9_RWCLK_posedge,
          TimingData              => Tmkr_D9_RWCLK_posedge,
          TestSignal              => D9_ipd,
          TestSignalName          => "D9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D9_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D9_RWCLK_noedge_posedge,
          HoldLow                 => thold_D9_RWCLK_noedge_posedge,
          HoldHigh                => thold_D9_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D10_RWCLK_posedge,
          TimingData              => Tmkr_D10_RWCLK_posedge,
          TestSignal              => D10_ipd,
          TestSignalName          => "D10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D10_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D10_RWCLK_noedge_posedge,
          HoldLow                 => thold_D10_RWCLK_noedge_posedge,
          HoldHigh                => thold_D10_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D11_RWCLK_posedge,
          TimingData              => Tmkr_D11_RWCLK_posedge,
          TestSignal              => D11_ipd,
          TestSignalName          => "D11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D11_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D11_RWCLK_noedge_posedge,
          HoldLow                 => thold_D11_RWCLK_noedge_posedge,
          HoldHigh                => thold_D11_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D12_RWCLK_posedge,
          TimingData              => Tmkr_D12_RWCLK_posedge,
          TestSignal              => D12_ipd,
          TestSignalName          => "D12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D12_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D12_RWCLK_noedge_posedge,
          HoldLow                 => thold_D12_RWCLK_noedge_posedge,
          HoldHigh                => thold_D12_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D13_RWCLK_posedge,
          TimingData              => Tmkr_D13_RWCLK_posedge,
          TestSignal              => D13_ipd,
          TestSignalName          => "D13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D13_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D13_RWCLK_noedge_posedge,
          HoldLow                 => thold_D13_RWCLK_noedge_posedge,
          HoldHigh                => thold_D13_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D13_RWCLK_posedge,
          TimingData              => Tmkr_D13_RWCLK_posedge,
          TestSignal              => D13_ipd,
          TestSignalName          => "D13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D13_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D13_RWCLK_noedge_posedge,
          HoldLow                 => thold_D13_RWCLK_noedge_posedge,
          HoldHigh                => thold_D13_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D14_RWCLK_posedge,
          TimingData              => Tmkr_D14_RWCLK_posedge,
          TestSignal              => D14_ipd,
          TestSignalName          => "D14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D14_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D14_RWCLK_noedge_posedge,
          HoldLow                 => thold_D14_RWCLK_noedge_posedge,
          HoldHigh                => thold_D14_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D15_RWCLK_posedge,
          TimingData              => Tmkr_D15_RWCLK_posedge,
          TestSignal              => D15_ipd,
          TestSignalName          => "D15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D15_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D15_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED1_RWCLK_posedge,
          TimingData              => Tmkr_ED1_RWCLK_posedge,
          TestSignal              => ED1_ipd,
          TestSignalName          => "ED1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk'EVENT and rd_clk = '1' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VITALBehavior_Write; 


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10 : std_logic := 'Z';
    VARIABLE DATA_A11 : std_logic := 'Z';
    VARIABLE DATA_A12 : std_logic := 'Z';
    VARIABLE DATA_A13 : std_logic := 'Z';
    VARIABLE DATA_A14 : std_logic := 'Z';
    VARIABLE DATA_A15 : std_logic := 'Z';
    VARIABLE DATA_A16 : std_logic := 'Z';
    VARIABLE DATA_A17 : std_logic := 'Z';
    VARIABLE OE_inverted : std_logic := 'Z';


    BEGIN

      OE_inverted := NOT (OE_ipd);
      con_a := VitalAND2(OE_inverted, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10 := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11 := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12 := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13 := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14 := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15 := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16 := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17 := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D1, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D2, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D3, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D4, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D5, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D6, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D7, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D8, GLITCH_DATA_A8, "DA8", DATA_A8,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D8, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D9, GLITCH_DATA_A9, "D9", DATA_A9,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D9, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D10, GLITCH_DATA_A10, "D10", DATA_A10,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D10, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D11, GLITCH_DATA_A11, "D11", DATA_A11,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D11, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D12, GLITCH_DATA_A12, "D12", DATA_A12,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D12, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D13, GLITCH_DATA_A13, "D13", DATA_A13,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D13, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D14, GLITCH_DATA_A14, "D14", DATA_A14,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D14, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D15, GLITCH_DATA_A15, "D15", DATA_A15,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D15, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A16, "ED0", DATA_A16,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_ED0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED1, GLITCH_DATA_A17, "ED1", DATA_A17,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_ED1, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_ED1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB256X18SSR_1_VITAL of RAMB256X18SSR_1 is
   for VITAL
   end for;
end CFG_RAMB256X18SSR_1_VITAL;

----- CELL RAMB256X18SSF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18SSF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK_D0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D8                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D9                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D10                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D11                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D12                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D13                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D14                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D15                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_ED0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_ED1                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE_RWCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D9_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D9_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D10_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D10_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D11_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D11_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D12_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D12_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D13_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D13_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D14_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D14_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D15_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D15_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED1_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      CE                            :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      D8                            :	inout STD_ULOGIC;
      D9                            :	inout STD_ULOGIC;
      D10                           :	inout STD_ULOGIC;
      D11                           :	inout STD_ULOGIC;
      D12                           :	inout STD_ULOGIC;
      D13                           :	inout STD_ULOGIC;
      D14                           :	inout STD_ULOGIC;
      D15                           :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC;
      ED1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18SSF : entity is TRUE;
end RAMB256X18SSF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18SSF is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL CE_ipd                 :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL D8_ipd                 :   std_logic :='X';
      SIGNAL D9_ipd                 :   std_logic :='X';
      SIGNAL D10_ipd                :   std_logic :='X';
      SIGNAL D11_ipd                :   std_logic :='X';
      SIGNAL D12_ipd                :   std_logic :='X';
      SIGNAL D13_ipd                :   std_logic :='X';
      SIGNAL D14_ipd                :   std_logic :='X';
      SIGNAL D15_ipd                :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';
      SIGNAL ED1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL rd_clk                 :   std_logic  := 'X';

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (CE_ipd,      CE,        tipd_CE);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (D8_ipd,      D8,        tipd_D8);
	VitalWireDelay (D9_ipd,      D9,        tipd_D9);
	VitalWireDelay (D10_ipd,     D10,       tipd_D10);
	VitalWireDelay (D11_ipd,     D11,       tipd_D11);
	VitalWireDelay (D12_ipd,     D12,       tipd_D12);
	VitalWireDelay (D13_ipd,     D13,       tipd_D13);
	VitalWireDelay (D14_ipd,     D14,       tipd_D14);
	VitalWireDelay (D15_ipd,     D15,       tipd_D15);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);
	VitalWireDelay (ED1_ipd,     ED1,       tipd_ED1);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '1' and WEN_ipd = '1') then
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_clk_a : process(OE_ipd, RWCLK_ipd, CE_ipd, WEN_ipd)

   begin
    if (OE_ipd = '1' and WEN_ipd = '1' and CE_ipd ='0') then
	rd_clk <= RWCLK_ipd;
    else
	rd_clk <= '1';
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd, CE_ipd)
   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd)

   begin
--    if (WEN_ipd = '0' and CE_ipd = '0' ) then
    if (WEN_ipd = '0') then
	wr_clk <= RWCLK_ipd;
    else
	wr_clk <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED1_ipd, 
                                  ED0_ipd, 
                                  D15_ipd, 
                                  D14_ipd, 
                                  D13_ipd, 
                                  D12_ipd, 
                                  D11_ipd, 
                                  D10_ipd, 
                                  D9_ipd, 
                                  D8_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(17) <= ED1_ipd;
        din_a(16) <= ED0_ipd;
        din_a(15) <= D15_ipd;
        din_a(14) <= D14_ipd;
        din_a(13) <= D13_ipd;
        din_a(12) <= D12_ipd;
        din_a(11) <= D11_ipd;
        din_a(10) <= D10_ipd;
        din_a(9)  <= D9_ipd;
        din_a(8)  <= D8_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18SSF Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk,
                            rd_clk,
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_CE_RWCLK_posedge    : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D8_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D9_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D10_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D11_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D12_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D13_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D14_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D15_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED1_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D8_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D9_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D10_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D11_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D12_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D13_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D14_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D15_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED1_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK               : std_ulogic := '0';
        variable PInfo_RWCLK               : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_RWCLK_posedge,
          TimingData              => Tmkr_CE_RWCLK_posedge,
          TestSignal              => CE_ipd,
          TestSignalName          => "CE",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE_RWCLK_noedge_posedge,
          SetupLow                => tsetup_CE_RWCLK_noedge_posedge,
          HoldLow                 => thold_CE_RWCLK_noedge_posedge,
          HoldHigh                => thold_CE_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D8_RWCLK_posedge,
          TimingData              => Tmkr_D8_RWCLK_posedge,
          TestSignal              => D8_ipd,
          TestSignalName          => "D8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D8_RWCLK_noedge_posedge,
          HoldLow                 => thold_D8_RWCLK_noedge_posedge,
          HoldHigh                => thold_D8_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D9_RWCLK_posedge,
          TimingData              => Tmkr_D9_RWCLK_posedge,
          TestSignal              => D9_ipd,
          TestSignalName          => "D9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D9_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D9_RWCLK_noedge_posedge,
          HoldLow                 => thold_D9_RWCLK_noedge_posedge,
          HoldHigh                => thold_D9_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D10_RWCLK_posedge,
          TimingData              => Tmkr_D10_RWCLK_posedge,
          TestSignal              => D10_ipd,
          TestSignalName          => "D10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D10_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D10_RWCLK_noedge_posedge,
          HoldLow                 => thold_D10_RWCLK_noedge_posedge,
          HoldHigh                => thold_D10_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D11_RWCLK_posedge,
          TimingData              => Tmkr_D11_RWCLK_posedge,
          TestSignal              => D11_ipd,
          TestSignalName          => "D11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D11_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D11_RWCLK_noedge_posedge,
          HoldLow                 => thold_D11_RWCLK_noedge_posedge,
          HoldHigh                => thold_D11_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D12_RWCLK_posedge,
          TimingData              => Tmkr_D12_RWCLK_posedge,
          TestSignal              => D12_ipd,
          TestSignalName          => "D12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D12_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D12_RWCLK_noedge_posedge,
          HoldLow                 => thold_D12_RWCLK_noedge_posedge,
          HoldHigh                => thold_D12_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D13_RWCLK_posedge,
          TimingData              => Tmkr_D13_RWCLK_posedge,
          TestSignal              => D13_ipd,
          TestSignalName          => "D13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D13_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D13_RWCLK_noedge_posedge,
          HoldLow                 => thold_D13_RWCLK_noedge_posedge,
          HoldHigh                => thold_D13_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D13_RWCLK_posedge,
          TimingData              => Tmkr_D13_RWCLK_posedge,
          TestSignal              => D13_ipd,
          TestSignalName          => "D13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D13_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D13_RWCLK_noedge_posedge,
          HoldLow                 => thold_D13_RWCLK_noedge_posedge,
          HoldHigh                => thold_D13_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D14_RWCLK_posedge,
          TimingData              => Tmkr_D14_RWCLK_posedge,
          TestSignal              => D14_ipd,
          TestSignalName          => "D14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D14_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D14_RWCLK_noedge_posedge,
          HoldLow                 => thold_D14_RWCLK_noedge_posedge,
          HoldHigh                => thold_D14_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D15_RWCLK_posedge,
          TimingData              => Tmkr_D15_RWCLK_posedge,
          TestSignal              => D15_ipd,
          TestSignalName          => "D15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D15_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D15_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED1_RWCLK_posedge,
          TimingData              => Tmkr_ED1_RWCLK_posedge,
          TestSignal              => ED1_ipd,
          TestSignalName          => "ED1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk'EVENT and rd_clk = '0' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VITALBehavior_Write; 


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10 : std_logic := 'Z';
    VARIABLE DATA_A11 : std_logic := 'Z';
    VARIABLE DATA_A12 : std_logic := 'Z';
    VARIABLE DATA_A13 : std_logic := 'Z';
    VARIABLE DATA_A14 : std_logic := 'Z';
    VARIABLE DATA_A15 : std_logic := 'Z';
    VARIABLE DATA_A16 : std_logic := 'Z';
    VARIABLE DATA_A17 : std_logic := 'Z';


    BEGIN

      con_a := VitalAND2(OE_ipd, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10 := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11 := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12 := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13 := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14 := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15 := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16 := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17 := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D1, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D2, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D3, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D4, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D5, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D6, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D7, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D8, GLITCH_DATA_A8, "DA8", DATA_A8,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D8, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D9, GLITCH_DATA_A9, "D9", DATA_A9,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D9, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D10, GLITCH_DATA_A10, "D10", DATA_A10,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D10, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D11, GLITCH_DATA_A11, "D11", DATA_A11,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D11, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D12, GLITCH_DATA_A12, "D12", DATA_A12,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D12, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D13, GLITCH_DATA_A13, "D13", DATA_A13,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D13, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D14, GLITCH_DATA_A14, "D14", DATA_A14,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D14, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D15, GLITCH_DATA_A15, "D15", DATA_A15,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D15, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A16, "ED0", DATA_A16,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_ED0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED1, GLITCH_DATA_A17, "ED1", DATA_A17,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_ED1, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_ED1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB256X18SSF_VITAL of RAMB256X18SSF is
   for VITAL
   end for;
end CFG_RAMB256X18SSF_VITAL;

----- CELL RAMB256X18SSF_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18SSF_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK_D0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D8                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D9                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D10                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D11                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D12                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D13                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D14                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D15                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_ED0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_ED1                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE_RWCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D9_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D9_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D10_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D10_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D11_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D11_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D12_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D12_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D13_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D13_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D14_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D14_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D15_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D15_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED1_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      CE                            :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      D8                            :	inout STD_ULOGIC;
      D9                            :	inout STD_ULOGIC;
      D10                           :	inout STD_ULOGIC;
      D11                           :	inout STD_ULOGIC;
      D12                           :	inout STD_ULOGIC;
      D13                           :	inout STD_ULOGIC;
      D14                           :	inout STD_ULOGIC;
      D15                           :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC;
      ED1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18SSF_1 : entity is TRUE;
end RAMB256X18SSF_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18SSF_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL CE_ipd                 :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL D8_ipd                 :   std_logic :='X';
      SIGNAL D9_ipd                 :   std_logic :='X';
      SIGNAL D10_ipd                :   std_logic :='X';
      SIGNAL D11_ipd                :   std_logic :='X';
      SIGNAL D12_ipd                :   std_logic :='X';
      SIGNAL D13_ipd                :   std_logic :='X';
      SIGNAL D14_ipd                :   std_logic :='X';
      SIGNAL D15_ipd                :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';
      SIGNAL ED1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL rd_clk                 :   std_logic  := 'X';

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (CE_ipd,      CE,        tipd_CE);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (D8_ipd,      D8,        tipd_D8);
	VitalWireDelay (D9_ipd,      D9,        tipd_D9);
	VitalWireDelay (D10_ipd,     D10,       tipd_D10);
	VitalWireDelay (D11_ipd,     D11,       tipd_D11);
	VitalWireDelay (D12_ipd,     D12,       tipd_D12);
	VitalWireDelay (D13_ipd,     D13,       tipd_D13);
	VitalWireDelay (D14_ipd,     D14,       tipd_D14);
	VitalWireDelay (D15_ipd,     D15,       tipd_D15);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);
	VitalWireDelay (ED1_ipd,     ED1,       tipd_ED1);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '0' and WEN_ipd = '1') then
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_clk_a : process(OE_ipd, RWCLK_ipd, CE_ipd, WEN_ipd)

   begin
    if (OE_ipd = '0' and WEN_ipd = '1' and CE_ipd ='0') then
	rd_clk <= RWCLK_ipd;
    else
	rd_clk <= '1';
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd, CE_ipd)
   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd)

   begin
--    if (WEN_ipd = '0' and CE_ipd = '0' ) then
    if (WEN_ipd = '0') then
	wr_clk <= RWCLK_ipd;
    else
	wr_clk <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED1_ipd, 
                                  ED0_ipd, 
                                  D15_ipd, 
                                  D14_ipd, 
                                  D13_ipd, 
                                  D12_ipd, 
                                  D11_ipd, 
                                  D10_ipd, 
                                  D9_ipd, 
                                  D8_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(17) <= ED1_ipd;
        din_a(16) <= ED0_ipd;
        din_a(15) <= D15_ipd;
        din_a(14) <= D14_ipd;
        din_a(13) <= D13_ipd;
        din_a(12) <= D12_ipd;
        din_a(11) <= D11_ipd;
        din_a(10) <= D10_ipd;
        din_a(9)  <= D9_ipd;
        din_a(8)  <= D8_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18SSF_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk,
                            rd_clk,
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_CE_RWCLK_posedge    : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D8_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D9_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D10_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D11_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D12_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D13_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D14_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D15_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED1_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D8_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D9_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D10_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D11_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D12_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D13_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D14_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D15_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED1_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK               : std_ulogic := '0';
        variable PInfo_RWCLK               : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_RWCLK_posedge,
          TimingData              => Tmkr_CE_RWCLK_posedge,
          TestSignal              => CE_ipd,
          TestSignalName          => "CE",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE_RWCLK_noedge_posedge,
          SetupLow                => tsetup_CE_RWCLK_noedge_posedge,
          HoldLow                 => thold_CE_RWCLK_noedge_posedge,
          HoldHigh                => thold_CE_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D8_RWCLK_posedge,
          TimingData              => Tmkr_D8_RWCLK_posedge,
          TestSignal              => D8_ipd,
          TestSignalName          => "D8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D8_RWCLK_noedge_posedge,
          HoldLow                 => thold_D8_RWCLK_noedge_posedge,
          HoldHigh                => thold_D8_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D9_RWCLK_posedge,
          TimingData              => Tmkr_D9_RWCLK_posedge,
          TestSignal              => D9_ipd,
          TestSignalName          => "D9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D9_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D9_RWCLK_noedge_posedge,
          HoldLow                 => thold_D9_RWCLK_noedge_posedge,
          HoldHigh                => thold_D9_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D10_RWCLK_posedge,
          TimingData              => Tmkr_D10_RWCLK_posedge,
          TestSignal              => D10_ipd,
          TestSignalName          => "D10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D10_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D10_RWCLK_noedge_posedge,
          HoldLow                 => thold_D10_RWCLK_noedge_posedge,
          HoldHigh                => thold_D10_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D11_RWCLK_posedge,
          TimingData              => Tmkr_D11_RWCLK_posedge,
          TestSignal              => D11_ipd,
          TestSignalName          => "D11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D11_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D11_RWCLK_noedge_posedge,
          HoldLow                 => thold_D11_RWCLK_noedge_posedge,
          HoldHigh                => thold_D11_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D12_RWCLK_posedge,
          TimingData              => Tmkr_D12_RWCLK_posedge,
          TestSignal              => D12_ipd,
          TestSignalName          => "D12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D12_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D12_RWCLK_noedge_posedge,
          HoldLow                 => thold_D12_RWCLK_noedge_posedge,
          HoldHigh                => thold_D12_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D13_RWCLK_posedge,
          TimingData              => Tmkr_D13_RWCLK_posedge,
          TestSignal              => D13_ipd,
          TestSignalName          => "D13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D13_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D13_RWCLK_noedge_posedge,
          HoldLow                 => thold_D13_RWCLK_noedge_posedge,
          HoldHigh                => thold_D13_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D13_RWCLK_posedge,
          TimingData              => Tmkr_D13_RWCLK_posedge,
          TestSignal              => D13_ipd,
          TestSignalName          => "D13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D13_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D13_RWCLK_noedge_posedge,
          HoldLow                 => thold_D13_RWCLK_noedge_posedge,
          HoldHigh                => thold_D13_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D14_RWCLK_posedge,
          TimingData              => Tmkr_D14_RWCLK_posedge,
          TestSignal              => D14_ipd,
          TestSignalName          => "D14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D14_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D14_RWCLK_noedge_posedge,
          HoldLow                 => thold_D14_RWCLK_noedge_posedge,
          HoldHigh                => thold_D14_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D15_RWCLK_posedge,
          TimingData              => Tmkr_D15_RWCLK_posedge,
          TestSignal              => D15_ipd,
          TestSignalName          => "D15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D15_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D15_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED1_RWCLK_posedge,
          TimingData              => Tmkr_ED1_RWCLK_posedge,
          TestSignal              => ED1_ipd,
          TestSignalName          => "ED1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk'EVENT and rd_clk = '0' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VITALBehavior_Write; 


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10 : std_logic := 'Z';
    VARIABLE DATA_A11 : std_logic := 'Z';
    VARIABLE DATA_A12 : std_logic := 'Z';
    VARIABLE DATA_A13 : std_logic := 'Z';
    VARIABLE DATA_A14 : std_logic := 'Z';
    VARIABLE DATA_A15 : std_logic := 'Z';
    VARIABLE DATA_A16 : std_logic := 'Z';
    VARIABLE DATA_A17 : std_logic := 'Z';
    VARIABLE OE_inverted : std_logic := 'Z';


    BEGIN

      OE_inverted := NOT (OE_ipd);
      con_a := VitalAND2(OE_inverted, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10 := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11 := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12 := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13 := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14 := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15 := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16 := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17 := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D1, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D2, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D3, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D4, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D5, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D6, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D7, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D8, GLITCH_DATA_A8, "DA8", DATA_A8,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D8, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D9, GLITCH_DATA_A9, "D9", DATA_A9,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D9, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D10, GLITCH_DATA_A10, "D10", DATA_A10,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D10, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D11, GLITCH_DATA_A11, "D11", DATA_A11,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D11, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D12, GLITCH_DATA_A12, "D12", DATA_A12,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D12, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D13, GLITCH_DATA_A13, "D13", DATA_A13,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D13, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D14, GLITCH_DATA_A14, "D14", DATA_A14,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D14, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D15, GLITCH_DATA_A15, "D15", DATA_A15,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D15, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A16, "ED0", DATA_A16,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_ED0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED1, GLITCH_DATA_A17, "ED1", DATA_A17,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_ED1, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_ED1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB256X18SSF_1_VITAL of RAMB256X18SSF_1 is
   for VITAL
   end for;
end CFG_RAMB256X18SSF_1_VITAL;

----- CELL RAMB256X18SAR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18SAR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADD0_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D9_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D9_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D10_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D10_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D11_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D11_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D12_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D12_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D13_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D13_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D14_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D14_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D15_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D15_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED1_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      D8                            :	inout STD_ULOGIC;
      D9                            :	inout STD_ULOGIC;
      D10                           :	inout STD_ULOGIC;
      D11                           :	inout STD_ULOGIC;
      D12                           :	inout STD_ULOGIC;
      D13                           :	inout STD_ULOGIC;
      D14                           :	inout STD_ULOGIC;
      D15                           :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC;
      ED1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18SAR : entity is TRUE;
end RAMB256X18SAR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18SAR is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL D8_ipd                 :   std_logic :='X';
      SIGNAL D9_ipd                 :   std_logic :='X';
      SIGNAL D10_ipd                :   std_logic :='X';
      SIGNAL D11_ipd                :   std_logic :='X';
      SIGNAL D12_ipd                :   std_logic :='X';
      SIGNAL D13_ipd                :   std_logic :='X';
      SIGNAL D14_ipd                :   std_logic :='X';
      SIGNAL D15_ipd                :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';
      SIGNAL ED1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (D8_ipd,      D8,        tipd_D8);
	VitalWireDelay (D9_ipd,      D9,        tipd_D9);
	VitalWireDelay (D10_ipd,     D10,       tipd_D10);
	VitalWireDelay (D11_ipd,     D11,       tipd_D11);
	VitalWireDelay (D12_ipd,     D12,       tipd_D12);
	VitalWireDelay (D13_ipd,     D13,       tipd_D13);
	VitalWireDelay (D14_ipd,     D14,       tipd_D14);
	VitalWireDelay (D15_ipd,     D15,       tipd_D15);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);
	VitalWireDelay (ED1_ipd,     ED1,       tipd_ED1);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '1' and WEN_ipd = '1') then
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd )

   begin
    if (WEN_ipd = '0' ) then
	wr_clk <= RWCLK_ipd;
    else
	wr_clk <= '0';
    end if;
   end process;

   write_address_a : process(
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED1_ipd, 
                                  ED0_ipd, 
                                  D15_ipd, 
                                  D14_ipd, 
                                  D13_ipd, 
                                  D12_ipd, 
                                  D11_ipd, 
                                  D10_ipd, 
                                  D9_ipd, 
                                  D8_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(17) <= ED1_ipd;
        din_a(16) <= ED0_ipd;
        din_a(15) <= D15_ipd;
        din_a(14) <= D14_ipd;
        din_a(13) <= D13_ipd;
        din_a(12) <= D12_ipd;
        din_a(11) <= D11_ipd;
        din_a(10) <= D10_ipd;
        din_a(9)  <= D9_ipd;
        din_a(8)  <= D8_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18SAR Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk, 
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D8_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D9_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D10_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D11_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D12_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D13_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D14_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D15_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED1_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D8_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D9_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D10_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D11_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D12_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D13_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D14_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D15_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED1_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK                : std_ulogic := '0';
        variable PInfo_RWCLK                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D8_RWCLK_posedge,
          TimingData              => Tmkr_D8_RWCLK_posedge,
          TestSignal              => D8_ipd,
          TestSignalName          => "D8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D8_RWCLK_noedge_posedge,
          HoldLow                 => thold_D8_RWCLK_noedge_posedge,
          HoldHigh                => thold_D8_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D9_RWCLK_posedge,
          TimingData              => Tmkr_D9_RWCLK_posedge,
          TestSignal              => D9_ipd,
          TestSignalName          => "D9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D9_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D9_RWCLK_noedge_posedge,
          HoldLow                 => thold_D9_RWCLK_noedge_posedge,
          HoldHigh                => thold_D9_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D10_RWCLK_posedge,
          TimingData              => Tmkr_D10_RWCLK_posedge,
          TestSignal              => D10_ipd,
          TestSignalName          => "D10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D10_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D10_RWCLK_noedge_posedge,
          HoldLow                 => thold_D10_RWCLK_noedge_posedge,
          HoldHigh                => thold_D10_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D11_RWCLK_posedge,
          TimingData              => Tmkr_D11_RWCLK_posedge,
          TestSignal              => D11_ipd,
          TestSignalName          => "D11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D11_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D11_RWCLK_noedge_posedge,
          HoldLow                 => thold_D11_RWCLK_noedge_posedge,
          HoldHigh                => thold_D11_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D12_RWCLK_posedge,
          TimingData              => Tmkr_D12_RWCLK_posedge,
          TestSignal              => D12_ipd,
          TestSignalName          => "D12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D12_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D12_RWCLK_noedge_posedge,
          HoldLow                 => thold_D12_RWCLK_noedge_posedge,
          HoldHigh                => thold_D12_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D13_RWCLK_posedge,
          TimingData              => Tmkr_D13_RWCLK_posedge,
          TestSignal              => D13_ipd,
          TestSignalName          => "D13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D13_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D13_RWCLK_noedge_posedge,
          HoldLow                 => thold_D13_RWCLK_noedge_posedge,
          HoldHigh                => thold_D13_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D14_RWCLK_posedge,
          TimingData              => Tmkr_D14_RWCLK_posedge,
          TestSignal              => D14_ipd,
          TestSignalName          => "D14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D14_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D14_RWCLK_noedge_posedge,
          HoldLow                 => thold_D14_RWCLK_noedge_posedge,
          HoldHigh                => thold_D14_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D15_RWCLK_posedge,
          TimingData              => Tmkr_D15_RWCLK_posedge,
          TestSignal              => D15_ipd,
          TestSignalName          => "D15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D15_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D15_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED1_RWCLK_posedge,
          TimingData              => Tmkr_ED1_RWCLK_posedge,
          TestSignal              => ED1_ipd,
          TestSignalName          => "ED1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10  : std_logic := 'Z';
    VARIABLE DATA_A11  : std_logic := 'Z';
    VARIABLE DATA_A12  : std_logic := 'Z';
    VARIABLE DATA_A13  : std_logic := 'Z';
    VARIABLE DATA_A14  : std_logic := 'Z';
    VARIABLE DATA_A15  : std_logic := 'Z';
    VARIABLE DATA_A16  : std_logic := 'Z';
    VARIABLE DATA_A17  : std_logic := 'Z';

    BEGIN

      con_a := VitalAND2(OE_ipd, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10  := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11  := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12  := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13  := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14  := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15  := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16  := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17  := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D0, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D1, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D1, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D1, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D1, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D1, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D1, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D1, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D1, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D2, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D2, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D2, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D2, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D2, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D2, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D2, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D2, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D3, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D3, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D3, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D3, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D3, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D3, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D3, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D3, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D4, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D4, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D4, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D4, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D4, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D4, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D4, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D4, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D5, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D5, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D5, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D5, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D5, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D5, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D5, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D5, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D6, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D6, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D6, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D6, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D6, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D6, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D6, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D6, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D7, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D7, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D7, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D7, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D7, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D7, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D7, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D7, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D8, GLITCH_DATA_A8, "D8", DATA_A8,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D8, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D8, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D8, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D8, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D8, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D8, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D8, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D8, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D9, GLITCH_DATA_A9, "D9", DATA_A9,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D9, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D9, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D9, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D9, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D9, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D9, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D9, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D9, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D10, GLITCH_DATA_A10, "D10", DATA_A10,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D10, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D10, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D10, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D10, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D10, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D10, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D10, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D10, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D11, GLITCH_DATA_A11, "D11", DATA_A11,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D11, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D11, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D11, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D11, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D11, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D11, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D11, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D11, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D12, GLITCH_DATA_A12, "D12", DATA_A12,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D12, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D12, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D12, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D12, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D12, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D12, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D12, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D12, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D13, GLITCH_DATA_A13, "D13", DATA_A13,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D13, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D13, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D13, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D13, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D13, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D13, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D13, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D13, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D14, GLITCH_DATA_A14, "D14", DATA_A14,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D14, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D14, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D14, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D14, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D14, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D14, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D14, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D14, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D15, GLITCH_DATA_A15, "D15", DATA_A15,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D15, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D15, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D15, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D15, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D15, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D15, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D15, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D15, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A16, "ED0", DATA_A16,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_ED0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_ED0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_ED0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_ED0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_ED0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_ED0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_ED0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_ED0, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED1, GLITCH_DATA_A17, "ED1", DATA_A17,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_ED1, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_ED1, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_ED1, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_ED1, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_ED1, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_ED1, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_ED1, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_ED1, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_ED1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB256X18SAR_VITAL of RAMB256X18SAR is
   for VITAL
   end for;
end CFG_RAMB256X18SAR_VITAL;

----- CELL RAMB256X18SAR_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18SAR_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADD0_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D9_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D9_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D10_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D10_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D11_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D11_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D12_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D12_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D13_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D13_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D14_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D14_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D15_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D15_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED1_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      D8                            :	inout STD_ULOGIC;
      D9                            :	inout STD_ULOGIC;
      D10                           :	inout STD_ULOGIC;
      D11                           :	inout STD_ULOGIC;
      D12                           :	inout STD_ULOGIC;
      D13                           :	inout STD_ULOGIC;
      D14                           :	inout STD_ULOGIC;
      D15                           :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC;
      ED1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18SAR_1 : entity is TRUE;
end RAMB256X18SAR_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18SAR_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL D8_ipd                 :   std_logic :='X';
      SIGNAL D9_ipd                 :   std_logic :='X';
      SIGNAL D10_ipd                :   std_logic :='X';
      SIGNAL D11_ipd                :   std_logic :='X';
      SIGNAL D12_ipd                :   std_logic :='X';
      SIGNAL D13_ipd                :   std_logic :='X';
      SIGNAL D14_ipd                :   std_logic :='X';
      SIGNAL D15_ipd                :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';
      SIGNAL ED1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (D8_ipd,      D8,        tipd_D8);
	VitalWireDelay (D9_ipd,      D9,        tipd_D9);
	VitalWireDelay (D10_ipd,     D10,       tipd_D10);
	VitalWireDelay (D11_ipd,     D11,       tipd_D11);
	VitalWireDelay (D12_ipd,     D12,       tipd_D12);
	VitalWireDelay (D13_ipd,     D13,       tipd_D13);
	VitalWireDelay (D14_ipd,     D14,       tipd_D14);
	VitalWireDelay (D15_ipd,     D15,       tipd_D15);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);
	VitalWireDelay (ED1_ipd,     ED1,       tipd_ED1);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '0' and WEN_ipd = '1') then
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd )

   begin
    if (WEN_ipd = '0' ) then
	wr_clk <= RWCLK_ipd;
    else
	wr_clk <= '0';
    end if;
   end process;

   write_address_a : process(
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED1_ipd, 
                                  ED0_ipd, 
                                  D15_ipd, 
                                  D14_ipd, 
                                  D13_ipd, 
                                  D12_ipd, 
                                  D11_ipd, 
                                  D10_ipd, 
                                  D9_ipd, 
                                  D8_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(17) <= ED1_ipd;
        din_a(16) <= ED0_ipd;
        din_a(15) <= D15_ipd;
        din_a(14) <= D14_ipd;
        din_a(13) <= D13_ipd;
        din_a(12) <= D12_ipd;
        din_a(11) <= D11_ipd;
        din_a(10) <= D10_ipd;
        din_a(9)  <= D9_ipd;
        din_a(8)  <= D8_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18SAR_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk, 
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D8_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D9_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D10_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D11_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D12_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D13_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D14_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D15_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED1_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D8_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D9_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D10_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D11_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D12_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D13_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D14_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D15_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED1_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK                : std_ulogic := '0';
        variable PInfo_RWCLK                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D8_RWCLK_posedge,
          TimingData              => Tmkr_D8_RWCLK_posedge,
          TestSignal              => D8_ipd,
          TestSignalName          => "D8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D8_RWCLK_noedge_posedge,
          HoldLow                 => thold_D8_RWCLK_noedge_posedge,
          HoldHigh                => thold_D8_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D9_RWCLK_posedge,
          TimingData              => Tmkr_D9_RWCLK_posedge,
          TestSignal              => D9_ipd,
          TestSignalName          => "D9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D9_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D9_RWCLK_noedge_posedge,
          HoldLow                 => thold_D9_RWCLK_noedge_posedge,
          HoldHigh                => thold_D9_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D10_RWCLK_posedge,
          TimingData              => Tmkr_D10_RWCLK_posedge,
          TestSignal              => D10_ipd,
          TestSignalName          => "D10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D10_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D10_RWCLK_noedge_posedge,
          HoldLow                 => thold_D10_RWCLK_noedge_posedge,
          HoldHigh                => thold_D10_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D11_RWCLK_posedge,
          TimingData              => Tmkr_D11_RWCLK_posedge,
          TestSignal              => D11_ipd,
          TestSignalName          => "D11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D11_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D11_RWCLK_noedge_posedge,
          HoldLow                 => thold_D11_RWCLK_noedge_posedge,
          HoldHigh                => thold_D11_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D12_RWCLK_posedge,
          TimingData              => Tmkr_D12_RWCLK_posedge,
          TestSignal              => D12_ipd,
          TestSignalName          => "D12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D12_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D12_RWCLK_noedge_posedge,
          HoldLow                 => thold_D12_RWCLK_noedge_posedge,
          HoldHigh                => thold_D12_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D13_RWCLK_posedge,
          TimingData              => Tmkr_D13_RWCLK_posedge,
          TestSignal              => D13_ipd,
          TestSignalName          => "D13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D13_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D13_RWCLK_noedge_posedge,
          HoldLow                 => thold_D13_RWCLK_noedge_posedge,
          HoldHigh                => thold_D13_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D13_RWCLK_posedge,
          TimingData              => Tmkr_D13_RWCLK_posedge,
          TestSignal              => D13_ipd,
          TestSignalName          => "D13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D13_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D13_RWCLK_noedge_posedge,
          HoldLow                 => thold_D13_RWCLK_noedge_posedge,
          HoldHigh                => thold_D13_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D14_RWCLK_posedge,
          TimingData              => Tmkr_D14_RWCLK_posedge,
          TestSignal              => D14_ipd,
          TestSignalName          => "D14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D14_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D14_RWCLK_noedge_posedge,
          HoldLow                 => thold_D14_RWCLK_noedge_posedge,
          HoldHigh                => thold_D14_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D15_RWCLK_posedge,
          TimingData              => Tmkr_D15_RWCLK_posedge,
          TestSignal              => D15_ipd,
          TestSignalName          => "D15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D15_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D15_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED1_RWCLK_posedge,
          TimingData              => Tmkr_ED1_RWCLK_posedge,
          TestSignal              => ED1_ipd,
          TestSignalName          => "ED1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10  : std_logic := 'Z';
    VARIABLE DATA_A11  : std_logic := 'Z';
    VARIABLE DATA_A12  : std_logic := 'Z';
    VARIABLE DATA_A13  : std_logic := 'Z';
    VARIABLE DATA_A14  : std_logic := 'Z';
    VARIABLE DATA_A15  : std_logic := 'Z';
    VARIABLE DATA_A16  : std_logic := 'Z';
    VARIABLE DATA_A17  : std_logic := 'Z';
    VARIABLE OE_inverted  : std_logic := 'Z';

    BEGIN

      OE_inverted := NOT (OE_ipd);
      con_a := VitalAND2(OE_inverted, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10  := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11  := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12  := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13  := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14  := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15  := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16  := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17  := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D0, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D1, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D1, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D1, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D1, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D1, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D1, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D1, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D1, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D2, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D2, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D2, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D2, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D2, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D2, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D2, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D2, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D3, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D3, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D3, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D3, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D3, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D3, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D3, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D3, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D4, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D4, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D4, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D4, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D4, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D4, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D4, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D4, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D5, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D5, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D5, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D5, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D5, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D5, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D5, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D5, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D6, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D6, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D6, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D6, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D6, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D6, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D6, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D6, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D7, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D7, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D7, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D7, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D7, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D7, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D7, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D7, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D8, GLITCH_DATA_A8, "D8", DATA_A8,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D8, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D8, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D8, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D8, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D8, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D8, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D8, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D8, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D9, GLITCH_DATA_A9, "D9", DATA_A9,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D9, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D9, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D9, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D9, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D9, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D9, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D9, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D9, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D10, GLITCH_DATA_A10, "D10", DATA_A10,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D10, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D10, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D10, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D10, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D10, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D10, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D10, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D10, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D11, GLITCH_DATA_A11, "D11", DATA_A11,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D11, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D11, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D11, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D11, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D11, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D11, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D11, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D11, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D12, GLITCH_DATA_A12, "D12", DATA_A12,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D12, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D12, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D12, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D12, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D12, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D12, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D12, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D12, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D13, GLITCH_DATA_A13, "D13", DATA_A13,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D13, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D13, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D13, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D13, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D13, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D13, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D13, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D13, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D14, GLITCH_DATA_A14, "D14", DATA_A14,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D14, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D14, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D14, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D14, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D14, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D14, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D14, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D14, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D15, GLITCH_DATA_A15, "D15", DATA_A15,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D15, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D15, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D15, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D15, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D15, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D15, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D15, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D15, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A16, "ED0", DATA_A16,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_ED0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_ED0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_ED0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_ED0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_ED0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_ED0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_ED0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_ED0, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED1, GLITCH_DATA_A17, "ED1", DATA_A17,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_ED1, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_ED1, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_ED1, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_ED1, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_ED1, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_ED1, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_ED1, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_ED1, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_ED1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB256X18SAR_1_VITAL of RAMB256X18SAR_1 is
   for VITAL
   end for;
end CFG_RAMB256X18SAR_1_VITAL;

----- CELL RAMB256X18SAF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18SAF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADD0_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D9_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D9_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D10_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D10_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D11_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D11_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D12_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D12_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D13_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D13_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D14_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D14_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D15_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D15_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED1_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      D8                            :	inout STD_ULOGIC;
      D9                            :	inout STD_ULOGIC;
      D10                           :	inout STD_ULOGIC;
      D11                           :	inout STD_ULOGIC;
      D12                           :	inout STD_ULOGIC;
      D13                           :	inout STD_ULOGIC;
      D14                           :	inout STD_ULOGIC;
      D15                           :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC;
      ED1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18SAF : entity is TRUE;
end RAMB256X18SAF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18SAF is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL D8_ipd                 :   std_logic :='X';
      SIGNAL D9_ipd                 :   std_logic :='X';
      SIGNAL D10_ipd                :   std_logic :='X';
      SIGNAL D11_ipd                :   std_logic :='X';
      SIGNAL D12_ipd                :   std_logic :='X';
      SIGNAL D13_ipd                :   std_logic :='X';
      SIGNAL D14_ipd                :   std_logic :='X';
      SIGNAL D15_ipd                :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';
      SIGNAL ED1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (D8_ipd,      D8,        tipd_D8);
	VitalWireDelay (D9_ipd,      D9,        tipd_D9);
	VitalWireDelay (D10_ipd,     D10,       tipd_D10);
	VitalWireDelay (D11_ipd,     D11,       tipd_D11);
	VitalWireDelay (D12_ipd,     D12,       tipd_D12);
	VitalWireDelay (D13_ipd,     D13,       tipd_D13);
	VitalWireDelay (D14_ipd,     D14,       tipd_D14);
	VitalWireDelay (D15_ipd,     D15,       tipd_D15);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);
	VitalWireDelay (ED1_ipd,     ED1,       tipd_ED1);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '1' and WEN_ipd = '1') then
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd )

   begin
    if (WEN_ipd = '0' ) then
	wr_clk <= RWCLK_ipd;
    else
	wr_clk <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED1_ipd, 
                                  ED0_ipd, 
                                  D15_ipd, 
                                  D14_ipd, 
                                  D13_ipd, 
                                  D12_ipd, 
                                  D11_ipd, 
                                  D10_ipd, 
                                  D9_ipd, 
                                  D8_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(17) <= ED1_ipd;
        din_a(16) <= ED0_ipd;
        din_a(15) <= D15_ipd;
        din_a(14) <= D14_ipd;
        din_a(13) <= D13_ipd;
        din_a(12) <= D12_ipd;
        din_a(11) <= D11_ipd;
        din_a(10) <= D10_ipd;
        din_a(9)  <= D9_ipd;
        din_a(8)  <= D8_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18SAF Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk, 
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D8_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D9_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D10_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D11_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D12_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D13_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D14_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D15_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED1_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D8_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D9_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D10_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D11_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D12_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D13_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D14_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D15_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED1_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK                : std_ulogic := '0';
        variable PInfo_RWCLK                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D8_RWCLK_posedge,
          TimingData              => Tmkr_D8_RWCLK_posedge,
          TestSignal              => D8_ipd,
          TestSignalName          => "D8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D8_RWCLK_noedge_posedge,
          HoldLow                 => thold_D8_RWCLK_noedge_posedge,
          HoldHigh                => thold_D8_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D9_RWCLK_posedge,
          TimingData              => Tmkr_D9_RWCLK_posedge,
          TestSignal              => D9_ipd,
          TestSignalName          => "D9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D9_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D9_RWCLK_noedge_posedge,
          HoldLow                 => thold_D9_RWCLK_noedge_posedge,
          HoldHigh                => thold_D9_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D10_RWCLK_posedge,
          TimingData              => Tmkr_D10_RWCLK_posedge,
          TestSignal              => D10_ipd,
          TestSignalName          => "D10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D10_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D10_RWCLK_noedge_posedge,
          HoldLow                 => thold_D10_RWCLK_noedge_posedge,
          HoldHigh                => thold_D10_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D11_RWCLK_posedge,
          TimingData              => Tmkr_D11_RWCLK_posedge,
          TestSignal              => D11_ipd,
          TestSignalName          => "D11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D11_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D11_RWCLK_noedge_posedge,
          HoldLow                 => thold_D11_RWCLK_noedge_posedge,
          HoldHigh                => thold_D11_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D12_RWCLK_posedge,
          TimingData              => Tmkr_D12_RWCLK_posedge,
          TestSignal              => D12_ipd,
          TestSignalName          => "D12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D12_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D12_RWCLK_noedge_posedge,
          HoldLow                 => thold_D12_RWCLK_noedge_posedge,
          HoldHigh                => thold_D12_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D13_RWCLK_posedge,
          TimingData              => Tmkr_D13_RWCLK_posedge,
          TestSignal              => D13_ipd,
          TestSignalName          => "D13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D13_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D13_RWCLK_noedge_posedge,
          HoldLow                 => thold_D13_RWCLK_noedge_posedge,
          HoldHigh                => thold_D13_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D13_RWCLK_posedge,
          TimingData              => Tmkr_D13_RWCLK_posedge,
          TestSignal              => D13_ipd,
          TestSignalName          => "D13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D13_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D13_RWCLK_noedge_posedge,
          HoldLow                 => thold_D13_RWCLK_noedge_posedge,
          HoldHigh                => thold_D13_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D14_RWCLK_posedge,
          TimingData              => Tmkr_D14_RWCLK_posedge,
          TestSignal              => D14_ipd,
          TestSignalName          => "D14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D14_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D14_RWCLK_noedge_posedge,
          HoldLow                 => thold_D14_RWCLK_noedge_posedge,
          HoldHigh                => thold_D14_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D15_RWCLK_posedge,
          TimingData              => Tmkr_D15_RWCLK_posedge,
          TestSignal              => D15_ipd,
          TestSignalName          => "D15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D15_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D15_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED1_RWCLK_posedge,
          TimingData              => Tmkr_ED1_RWCLK_posedge,
          TestSignal              => ED1_ipd,
          TestSignalName          => "ED1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10  : std_logic := 'Z';
    VARIABLE DATA_A11  : std_logic := 'Z';
    VARIABLE DATA_A12  : std_logic := 'Z';
    VARIABLE DATA_A13  : std_logic := 'Z';
    VARIABLE DATA_A14  : std_logic := 'Z';
    VARIABLE DATA_A15  : std_logic := 'Z';
    VARIABLE DATA_A16  : std_logic := 'Z';
    VARIABLE DATA_A17  : std_logic := 'Z';

    BEGIN

      con_a := VitalAND2(OE_ipd, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10  := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11  := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12  := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13  := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14  := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15  := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16  := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17  := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D0, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D1, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D1, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D1, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D1, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D1, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D1, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D1, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D1, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D2, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D2, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D2, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D2, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D2, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D2, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D2, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D2, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D3, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D3, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D3, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D3, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D3, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D3, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D3, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D3, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D4, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D4, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D4, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D4, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D4, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D4, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D4, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D4, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D5, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D5, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D5, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D5, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D5, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D5, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D5, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D5, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D6, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D6, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D6, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D6, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D6, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D6, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D6, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D6, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D7, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D7, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D7, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D7, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D7, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D7, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D7, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D7, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D8, GLITCH_DATA_A8, "D8", DATA_A8,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D8, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D8, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D8, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D8, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D8, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D8, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D8, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D8, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D9, GLITCH_DATA_A9, "D9", DATA_A9,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D9, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D9, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D9, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D9, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D9, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D9, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D9, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D9, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D10, GLITCH_DATA_A10, "D10", DATA_A10,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D10, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D10, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D10, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D10, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D10, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D10, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D10, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D10, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D11, GLITCH_DATA_A11, "D11", DATA_A11,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D11, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D11, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D11, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D11, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D11, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D11, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D11, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D11, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D12, GLITCH_DATA_A12, "D12", DATA_A12,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D12, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D12, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D12, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D12, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D12, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D12, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D12, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D12, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D13, GLITCH_DATA_A13, "D13", DATA_A13,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D13, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D13, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D13, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D13, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D13, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D13, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D13, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D13, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D14, GLITCH_DATA_A14, "D14", DATA_A14,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D14, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D14, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D14, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D14, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D14, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D14, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D14, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D14, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D15, GLITCH_DATA_A15, "D15", DATA_A15,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D15, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D15, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D15, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D15, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D15, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D15, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D15, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D15, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A16, "ED0", DATA_A16,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_ED0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_ED0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_ED0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_ED0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_ED0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_ED0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_ED0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_ED0, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED1, GLITCH_DATA_A17, "ED1", DATA_A17,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_ED1, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_ED1, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_ED1, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_ED1, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_ED1, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_ED1, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_ED1, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_ED1, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_ED1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB256X18SAF_VITAL of RAMB256X18SAF is
   for VITAL
   end for;
end CFG_RAMB256X18SAF_VITAL;

----- CELL RAMB256X18SAF_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB256X18SAF_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADD0_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D8                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D9                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D10                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D11                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D12                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D13                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D14                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D15                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_ED1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D8                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D9                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D10                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D11                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D12                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D13                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D14                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D15                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED1                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D9_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D9_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D10_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D10_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D11_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D11_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D12_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D12_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D13_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D13_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D14_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D14_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_D15_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_D15_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      tsetup_ED1_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D8                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D9                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D10                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D11                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D12                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D13                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D14                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D15                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED1                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0A                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0B                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0C                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0D                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0E                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT0F                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT10                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT11                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT12                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      D8                            :	inout STD_ULOGIC;
      D9                            :	inout STD_ULOGIC;
      D10                           :	inout STD_ULOGIC;
      D11                           :	inout STD_ULOGIC;
      D12                           :	inout STD_ULOGIC;
      D13                           :	inout STD_ULOGIC;
      D14                           :	inout STD_ULOGIC;
      D15                           :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC;
      ED1                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB256X18SAF_1 : entity is TRUE;
end RAMB256X18SAF_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB256X18SAF_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL D8_ipd                 :   std_logic :='X';
      SIGNAL D9_ipd                 :   std_logic :='X';
      SIGNAL D10_ipd                :   std_logic :='X';
      SIGNAL D11_ipd                :   std_logic :='X';
      SIGNAL D12_ipd                :   std_logic :='X';
      SIGNAL D13_ipd                :   std_logic :='X';
      SIGNAL D14_ipd                :   std_logic :='X';
      SIGNAL D15_ipd                :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';
      SIGNAL ED1_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(17 downto 0) := z_data_18;

      SIGNAL rd_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(7 downto 0);

      SIGNAL din_a                   :   std_logic_vector(17 downto 0);

      constant init01_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT09)) ;
      constant init0A_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0A)) ;
      constant init0B_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0B)) ;
      constant init0C_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0C)) ;
      constant init0D_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0D)) ;
      constant init0E_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0E)) ;
      constant init0F_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT0F)) ;
      constant init10_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT10)) ;
      constant init11_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT11)) ;
      constant init12_sig              :   std_logic_vector(255 downto 0 ) := ( To_StdLogicVector(INIT12)) ;

      signal memory_array            :   memory_array_typ_256  := FillInit256(init12_sig & init11_sig & 
                                         init10_sig & init0F_sig & init0E_sig & init0D_sig & 
                                         init0C_sig & init0B_sig & init0A_sig & init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (D8_ipd,      D8,        tipd_D8);
	VitalWireDelay (D9_ipd,      D9,        tipd_D9);
	VitalWireDelay (D10_ipd,     D10,       tipd_D10);
	VitalWireDelay (D11_ipd,     D11,       tipd_D11);
	VitalWireDelay (D12_ipd,     D12,       tipd_D12);
	VitalWireDelay (D13_ipd,     D13,       tipd_D13);
	VitalWireDelay (D14_ipd,     D14,       tipd_D14);
	VitalWireDelay (D15_ipd,     D15,       tipd_D15);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);
	VitalWireDelay (ED1_ipd,     ED1,       tipd_ED1);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '0' and WEN_ipd = '1') then
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_8;
   end if;
   end process wrapper_read_add_a;

   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd )

   begin
    if (WEN_ipd = '0' ) then
	wr_clk <= RWCLK_ipd;
    else
	wr_clk <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED1_ipd, 
                                  ED0_ipd, 
                                  D15_ipd, 
                                  D14_ipd, 
                                  D13_ipd, 
                                  D12_ipd, 
                                  D11_ipd, 
                                  D10_ipd, 
                                  D9_ipd, 
                                  D8_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(17) <= ED1_ipd;
        din_a(16) <= ED0_ipd;
        din_a(15) <= D15_ipd;
        din_a(14) <= D14_ipd;
        din_a(13) <= D13_ipd;
        din_a(12) <= D12_ipd;
        din_a(11) <= D11_ipd;
        din_a(10) <= D10_ipd;
        din_a(9)  <= D9_ipd;
        din_a(8)  <= D8_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_18;
    end if;
   end process;

      --------------------
      -- RAMB256X18SAF_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk, 
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D8_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D9_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D10_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D11_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D12_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D13_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D14_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_D15_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';
        variable Tviol_ED1_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D8_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D9_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D10_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D11_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D12_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D13_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D14_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D15_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED1_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK                : std_ulogic := '0';
        variable PInfo_RWCLK                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D8_RWCLK_posedge,
          TimingData              => Tmkr_D8_RWCLK_posedge,
          TestSignal              => D8_ipd,
          TestSignalName          => "D8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D8_RWCLK_noedge_posedge,
          HoldLow                 => thold_D8_RWCLK_noedge_posedge,
          HoldHigh                => thold_D8_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D9_RWCLK_posedge,
          TimingData              => Tmkr_D9_RWCLK_posedge,
          TestSignal              => D9_ipd,
          TestSignalName          => "D9",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D9_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D9_RWCLK_noedge_posedge,
          HoldLow                 => thold_D9_RWCLK_noedge_posedge,
          HoldHigh                => thold_D9_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D10_RWCLK_posedge,
          TimingData              => Tmkr_D10_RWCLK_posedge,
          TestSignal              => D10_ipd,
          TestSignalName          => "D10",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D10_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D10_RWCLK_noedge_posedge,
          HoldLow                 => thold_D10_RWCLK_noedge_posedge,
          HoldHigh                => thold_D10_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D11_RWCLK_posedge,
          TimingData              => Tmkr_D11_RWCLK_posedge,
          TestSignal              => D11_ipd,
          TestSignalName          => "D11",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D11_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D11_RWCLK_noedge_posedge,
          HoldLow                 => thold_D11_RWCLK_noedge_posedge,
          HoldHigh                => thold_D11_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D12_RWCLK_posedge,
          TimingData              => Tmkr_D12_RWCLK_posedge,
          TestSignal              => D12_ipd,
          TestSignalName          => "D12",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D12_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D12_RWCLK_noedge_posedge,
          HoldLow                 => thold_D12_RWCLK_noedge_posedge,
          HoldHigh                => thold_D12_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D13_RWCLK_posedge,
          TimingData              => Tmkr_D13_RWCLK_posedge,
          TestSignal              => D13_ipd,
          TestSignalName          => "D13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D13_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D13_RWCLK_noedge_posedge,
          HoldLow                 => thold_D13_RWCLK_noedge_posedge,
          HoldHigh                => thold_D13_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D13_RWCLK_posedge,
          TimingData              => Tmkr_D13_RWCLK_posedge,
          TestSignal              => D13_ipd,
          TestSignalName          => "D13",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D13_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D13_RWCLK_noedge_posedge,
          HoldLow                 => thold_D13_RWCLK_noedge_posedge,
          HoldHigh                => thold_D13_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D14_RWCLK_posedge,
          TimingData              => Tmkr_D14_RWCLK_posedge,
          TestSignal              => D14_ipd,
          TestSignalName          => "D14",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D14_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D14_RWCLK_noedge_posedge,
          HoldLow                 => thold_D14_RWCLK_noedge_posedge,
          HoldHigh                => thold_D14_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D15_RWCLK_posedge,
          TimingData              => Tmkr_D15_RWCLK_posedge,
          TestSignal              => D15_ipd,
          TestSignalName          => "D15",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D15_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D15_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED1_RWCLK_posedge,
          TimingData              => Tmkr_ED1_RWCLK_posedge,
          TestSignal              => ED1_ipd,
          TestSignalName          => "ED1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB256X18SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A9 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A10 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A11 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A12 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A13 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A14 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A15 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A16 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A17 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE DATA_A9  : std_logic := 'Z';
    VARIABLE DATA_A10  : std_logic := 'Z';
    VARIABLE DATA_A11  : std_logic := 'Z';
    VARIABLE DATA_A12  : std_logic := 'Z';
    VARIABLE DATA_A13  : std_logic := 'Z';
    VARIABLE DATA_A14  : std_logic := 'Z';
    VARIABLE DATA_A15  : std_logic := 'Z';
    VARIABLE DATA_A16  : std_logic := 'Z';
    VARIABLE DATA_A17  : std_logic := 'Z';
    VARIABLE OE_inverted  : std_logic := 'Z';

    BEGIN

      OE_inverted := NOT (OE_ipd);
      con_a := VitalAND2(OE_inverted, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);
      DATA_A9  := VITALBUFIF1(data_out_a(9),con_a);
      DATA_A10  := VITALBUFIF1(data_out_a(10),con_a);
      DATA_A11  := VITALBUFIF1(data_out_a(11),con_a);
      DATA_A12  := VITALBUFIF1(data_out_a(12),con_a);
      DATA_A13  := VITALBUFIF1(data_out_a(13),con_a);
      DATA_A14  := VITALBUFIF1(data_out_a(14),con_a);
      DATA_A15  := VITALBUFIF1(data_out_a(15),con_a);
      DATA_A16  := VITALBUFIF1(data_out_a(16),con_a);
      DATA_A17  := VITALBUFIF1(data_out_a(17),con_a);


      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D0, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D1, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D1, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D1, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D1, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D1, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D1, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D1, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D1, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D2, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D2, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D2, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D2, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D2, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D2, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D2, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D2, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D3, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D3, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D3, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D3, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D3, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D3, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D3, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D3, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D4, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D4, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D4, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D4, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D4, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D4, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D4, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D4, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D5, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D5, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D5, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D5, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D5, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D5, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D5, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D5, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D6, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D6, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D6, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D6, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D6, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D6, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D6, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D6, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D7, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D7, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D7, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D7, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D7, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D7, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D7, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D7, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D8, GLITCH_DATA_A8, "D8", DATA_A8,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D8, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D8, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D8, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D8, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D8, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D8, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D8, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D8, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D8, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D9, GLITCH_DATA_A9, "D9", DATA_A9,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D9, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D9, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D9, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D9, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D9, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D9, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D9, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D9, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D9, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D10, GLITCH_DATA_A10, "D10", DATA_A10,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D10, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D10, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D10, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D10, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D10, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D10, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D10, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D10, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D10, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D11, GLITCH_DATA_A11, "D11", DATA_A11,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D11, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D11, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D11, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D11, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D11, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D11, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D11, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D11, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D11, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D12, GLITCH_DATA_A12, "D12", DATA_A12,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D12, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D12, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D12, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D12, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D12, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D12, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D12, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D12, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D12, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D13, GLITCH_DATA_A13, "D13", DATA_A13,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D13, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D13, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D13, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D13, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D13, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D13, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D13, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D13, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D13, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D14, GLITCH_DATA_A14, "D14", DATA_A14,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D14, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D14, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D14, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D14, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D14, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D14, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D14, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D14, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D14, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D15, GLITCH_DATA_A15, "D15", DATA_A15,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D15, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D15, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D15, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D15, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D15, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D15, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D15, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D15, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_D15, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A16, "ED0", DATA_A16,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_ED0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_ED0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_ED0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_ED0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_ED0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_ED0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_ED0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_ED0, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED1, GLITCH_DATA_A17, "ED1", DATA_A17,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_ED1, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_ED1, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_ED1, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_ED1, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_ED1, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_ED1, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_ED1, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_ED1, TRUE),
        8 => ( OE_ipd'LAST_EVENT, tpd_OE_ED1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB256X18SAF_1_VITAL of RAMB256X18SAF_1 is
   for VITAL
   end for;
end CFG_RAMB256X18SAF_1_VITAL;

----- CELL RAMB512X9SSR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9SSR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK_D0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_ED0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE_RWCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      CE                            :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      ADD8                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9SSR : entity is TRUE;
end RAMB512X9SSR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9SSR is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL CE_ipd                 :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL ADD8_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL rd_clk                 :   std_logic  := 'X';

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512(  init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (CE_ipd,      CE,        tipd_CE);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);
	VitalWireDelay (ADD8_ipd,    ADD8,      tipd_ADD8);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                ADD8_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '1' and WEN_ipd = '1') then
        rd_add_a(8) <= ADD8_ipd;
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   --wrapper_read_clk_a : process(OE_ipd, RWCLK_ipd, CE_ipd, WEN_ipd)
   wrapper_read_clk_a : process(RWCLK_ipd) --071804

   begin
    if rising_edge (RWCLK_ipd) then --071804
     if (OE_ipd = '1' and WEN_ipd = '1' and CE_ipd ='0') then
	rd_clk <= RWCLK_ipd;
     end if;
    else
	rd_clk <= '0';
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd, CE_ipd)
   --wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd)
   wrapper_write_clk_a : process( RWCLK_ipd) --071804

   begin
--    if (WEN_ipd = '0' and CE_ipd = '0' ) then
    if rising_edge (RWCLK_ipd) then--071804
     if (WEN_ipd = '0') then
	wr_clk <= RWCLK_ipd;
     end if;
    else
	wr_clk <= '0';
    end if;
   end process;

   write_address_a : process(
                            ADD8_ipd,
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(8) <= ADD8_ipd;
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED0_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(8) <= ED0_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9SSR Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk,
                            rd_clk,
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_CE_RWCLK_posedge    : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD8_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD8_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK               : std_ulogic := '0';
        variable PInfo_RWCLK               : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_RWCLK_posedge,
          TimingData              => Tmkr_CE_RWCLK_posedge,
          TestSignal              => CE_ipd,
          TestSignalName          => "CE",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE_RWCLK_noedge_posedge,
          SetupLow                => tsetup_CE_RWCLK_noedge_posedge,
          HoldLow                 => thold_CE_RWCLK_noedge_posedge,
          HoldHigh                => thold_CE_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD8_RWCLK_posedge,
          TimingData              => Tmkr_ADD8_RWCLK_posedge,
          TestSignal              => ADD8_ipd,
          TestSignalName          => "ADD8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD8_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD8_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD8_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9SSR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk'EVENT and rd_clk = '1' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VITALBehavior_Write; 


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';


    BEGIN

      con_a := VitalAND2(OE_ipd, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);


      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D1, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D2, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D3, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D4, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D5, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D6, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D7, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A8, "ED0", DATA_A8,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_ED0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB512X9SSR_VITAL of RAMB512X9SSR is
   for VITAL
   end for;
end CFG_RAMB512X9SSR_VITAL;

----- CELL RAMB512X9SSR_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9SSR_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK_D0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_ED0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE_RWCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      CE                            :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      ADD8                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9SSR_1 : entity is TRUE;
end RAMB512X9SSR_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9SSR_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL CE_ipd                 :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL ADD8_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL rd_clk                 :   std_logic  := 'X';

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512(  init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (CE_ipd,      CE,        tipd_CE);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);
	VitalWireDelay (ADD8_ipd,    ADD8,      tipd_ADD8);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                ADD8_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '0' and WEN_ipd = '1') then
        rd_add_a(8) <= ADD8_ipd;
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_clk_a : process(OE_ipd, RWCLK_ipd, CE_ipd, WEN_ipd)

   begin
    if (OE_ipd = '0' and WEN_ipd = '1' and CE_ipd ='0') then
	rd_clk <= RWCLK_ipd;
    else
	rd_clk <= '0';
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd, CE_ipd)
   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd)

   begin
--    if (WEN_ipd = '0' and CE_ipd = '0' ) then
    if (WEN_ipd = '0') then
	wr_clk <= RWCLK_ipd;
    else
	wr_clk <= '0';
    end if;
   end process;

   write_address_a : process(
                            ADD8_ipd,
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(8) <= ADD8_ipd;
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED0_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(8) <= ED0_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9SSR_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk,
                            rd_clk,
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_CE_RWCLK_posedge    : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD8_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD8_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK               : std_ulogic := '0';
        variable PInfo_RWCLK               : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_RWCLK_posedge,
          TimingData              => Tmkr_CE_RWCLK_posedge,
          TestSignal              => CE_ipd,
          TestSignalName          => "CE",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE_RWCLK_noedge_posedge,
          SetupLow                => tsetup_CE_RWCLK_noedge_posedge,
          HoldLow                 => thold_CE_RWCLK_noedge_posedge,
          HoldHigh                => thold_CE_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD8_RWCLK_posedge,
          TimingData              => Tmkr_ADD8_RWCLK_posedge,
          TestSignal              => ADD8_ipd,
          TestSignalName          => "ADD8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD8_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD8_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD8_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9SSR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk'EVENT and rd_clk = '1' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VITALBehavior_Write; 


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE OE_inverted  : std_logic := 'Z';


    BEGIN

      OE_inverted := NOT (OE_ipd);
      con_a := VitalAND2(OE_inverted, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);


      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D1, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D2, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D3, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D4, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D5, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D6, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D7, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A8, "ED0", DATA_A8,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_ED0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB512X9SSR_1_VITAL of RAMB512X9SSR_1 is
   for VITAL
   end for;
end CFG_RAMB512X9SSR_1_VITAL;

----- CELL RAMB512X9SSF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9SSF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK_D0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_ED0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE_RWCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      CE                            :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      ADD8                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9SSF : entity is TRUE;
end RAMB512X9SSF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9SSF is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL CE_ipd                 :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL ADD8_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL rd_clk                 :   std_logic  := 'X';

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512(  init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (CE_ipd,      CE,        tipd_CE);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);
	VitalWireDelay (ADD8_ipd,    ADD8,      tipd_ADD8);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                ADD8_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '1' and WEN_ipd = '1') then
        rd_add_a(8) <= ADD8_ipd;
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_clk_a : process(OE_ipd, RWCLK_ipd, CE_ipd, WEN_ipd)

   begin
    if (OE_ipd = '1' and WEN_ipd = '1' and CE_ipd ='0') then
	rd_clk <= RWCLK_ipd;
    else
	rd_clk <= '1';
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd, CE_ipd)
   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd)

   begin
--    if (WEN_ipd = '0' and CE_ipd = '0' ) then
    if (WEN_ipd = '0') then
	wr_clk <= RWCLK_ipd;
    else
	wr_clk <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADD8_ipd,
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(8) <= ADD8_ipd;
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED0_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(8) <= ED0_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9SSF Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk,
                            rd_clk,
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_CE_RWCLK_posedge    : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD8_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD8_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK               : std_ulogic := '0';
        variable PInfo_RWCLK               : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_RWCLK_posedge,
          TimingData              => Tmkr_CE_RWCLK_posedge,
          TestSignal              => CE_ipd,
          TestSignalName          => "CE",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE_RWCLK_noedge_posedge,
          SetupLow                => tsetup_CE_RWCLK_noedge_posedge,
          HoldLow                 => thold_CE_RWCLK_noedge_posedge,
          HoldHigh                => thold_CE_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD8_RWCLK_posedge,
          TimingData              => Tmkr_ADD8_RWCLK_posedge,
          TestSignal              => ADD8_ipd,
          TestSignalName          => "ADD8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD8_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD8_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD8_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9SSF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk'EVENT and rd_clk = '0' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VITALBehavior_Write; 


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';


    BEGIN

      con_a := VitalAND2(OE_ipd, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);


      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D1, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D2, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D3, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D4, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D5, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D6, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D7, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A8, "ED0", DATA_A8,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_ED0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB512X9SSF_VITAL of RAMB512X9SSF is
   for VITAL
   end for;
end CFG_RAMB512X9SSF_VITAL;

----- CELL RAMB512X9SSF_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9SSF_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_RWCLK_D0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D1                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D2                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D3                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D4                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D5                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D6                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_D7                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_RWCLK_ED0                  :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      tsetup_CE_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;
      thold_CE_RWCLK_noedge_posedge     :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_CE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      CE                            :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      ADD8                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9SSF_1 : entity is TRUE;
end RAMB512X9SSF_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9SSF_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL CE_ipd                 :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL ADD8_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL rd_clk                 :   std_logic  := 'X';

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512(  init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (CE_ipd,      CE,        tipd_CE);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);
	VitalWireDelay (ADD8_ipd,    ADD8,      tipd_ADD8);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                ADD8_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '0' and WEN_ipd = '1') then
        rd_add_a(8) <= ADD8_ipd;
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   wrapper_read_clk_a : process(OE_ipd, RWCLK_ipd, CE_ipd, WEN_ipd)

   begin
    if (OE_ipd = '0' and WEN_ipd = '1' and CE_ipd ='0') then
	rd_clk <= RWCLK_ipd;
    else
	rd_clk <= '1';
    end if;
   end process;

--   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd, CE_ipd)
   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd)

   begin
--    if (WEN_ipd = '0' and CE_ipd = '0' ) then
    if (WEN_ipd = '0') then
	wr_clk <= RWCLK_ipd;
    else
	wr_clk <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADD8_ipd,
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(8) <= ADD8_ipd;
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED0_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(8) <= ED0_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9SSF_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk,
                            rd_clk,
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_CE_RWCLK_posedge    : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD8_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_CE_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD8_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK               : std_ulogic := '0';
        variable PInfo_RWCLK               : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_CE_RWCLK_posedge,
          TimingData              => Tmkr_CE_RWCLK_posedge,
          TestSignal              => CE_ipd,
          TestSignalName          => "CE",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_CE_RWCLK_noedge_posedge,
          SetupLow                => tsetup_CE_RWCLK_noedge_posedge,
          HoldLow                 => thold_CE_RWCLK_noedge_posedge,
          HoldHigh                => thold_CE_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD8_RWCLK_posedge,
          TimingData              => Tmkr_ADD8_RWCLK_posedge,
          TestSignal              => ADD8_ipd,
          TestSignalName          => "ADD8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD8_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD8_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD8_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9SSF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( rd_clk'EVENT and rd_clk = '0' and not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VITALBehavior_Write; 


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE OE_inverted  : std_logic := 'Z';


    BEGIN

      OE_inverted := NOT (OE_ipd);
      con_a := VitalAND2(OE_inverted, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);


      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D1, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D2, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D3, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D4, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D5, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D6, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_D7, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A8, "ED0", DATA_A8,
        Paths => (
        0 => ( RWCLK_ipd'LAST_EVENT, tpd_RWCLK_ED0, TRUE),
        1 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB512X9SSF_1_VITAL of RAMB512X9SSF_1 is
   for VITAL
   end for;
end CFG_RAMB512X9SSF_1_VITAL;

----- CELL RAMB512X9SAR -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9SAR is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADD0_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      ADD8                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9SAR : entity is TRUE;
end RAMB512X9SAR;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9SAR is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL ADD8_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512(init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);
	VitalWireDelay (ADD8_ipd,    ADD8,      tipd_ADD8);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                ADD8_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '1' and WEN_ipd = '1') then
        rd_add_a(8) <= ADD8_ipd;
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd )

   begin
    if (WEN_ipd = '0' ) then
	wr_clk <= RWCLK_ipd;
    else
	wr_clk <= '0';
    end if;
   end process;

   write_address_a : process(
                            ADD8_ipd,
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(8) <= ADD8_ipd;
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED0_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(8) <= ED0_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9SAR Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk, 
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD8_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD8_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK                : std_ulogic := '0';
        variable PInfo_RWCLK                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD8_RWCLK_posedge,
          TimingData              => Tmkr_ADD8_RWCLK_posedge,
          TestSignal              => ADD8_ipd,
          TestSignalName          => "ADD8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD8_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD8_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD8_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9SAR",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';

    BEGIN

      con_a := VitalAND2(OE_ipd, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);

      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D0, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D0, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D1, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D1, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D1, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D1, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D1, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D1, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D1, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D1, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D1, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D2, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D2, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D2, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D2, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D2, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D2, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D2, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D2, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D2, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D3, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D3, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D3, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D3, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D3, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D3, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D3, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D3, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D3, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D4, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D4, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D4, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D4, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D4, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D4, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D4, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D4, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D4, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D5, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D5, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D5, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D5, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D5, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D5, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D5, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D5, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D5, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D6, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D6, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D6, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D6, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D6, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D6, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D6, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D6, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D6, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D7, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D7, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D7, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D7, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D7, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D7, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D7, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D7, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D7, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A8, "ED0", DATA_A8,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_ED0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_ED0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_ED0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_ED0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_ED0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_ED0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_ED0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_ED0, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_ED0, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB512X9SAR_VITAL of RAMB512X9SAR is
   for VITAL
   end for;
end CFG_RAMB512X9SAR_VITAL;

----- CELL RAMB512X9SAR_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9SAR_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADD0_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      ADD8                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9SAR_1 : entity is TRUE;
end RAMB512X9SAR_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9SAR_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL ADD8_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512(init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);
	VitalWireDelay (ADD8_ipd,    ADD8,      tipd_ADD8);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                ADD8_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '0' and WEN_ipd = '1') then
        rd_add_a(8) <= ADD8_ipd;
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd )

   begin
    if (WEN_ipd = '0' ) then
	wr_clk <= RWCLK_ipd;
    else
	wr_clk <= '0';
    end if;
   end process;

   write_address_a : process(
                            ADD8_ipd,
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(8) <= ADD8_ipd;
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED0_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(8) <= ED0_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9SAR_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk, 
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD8_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD8_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK                : std_ulogic := '0';
        variable PInfo_RWCLK                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD8_RWCLK_posedge,
          TimingData              => Tmkr_ADD8_RWCLK_posedge,
          TestSignal              => ADD8_ipd,
          TestSignalName          => "ADD8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD8_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD8_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD8_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9SAR_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '1' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '1' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE OE_inverted  : std_logic := 'Z';

    BEGIN

      OE_inverted := NOT (OE_ipd); 
      con_a := VitalAND2(OE_inverted, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);

      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D0, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D0, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D1, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D1, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D1, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D1, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D1, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D1, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D1, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D1, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D1, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D2, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D2, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D2, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D2, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D2, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D2, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D2, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D2, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D2, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D3, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D3, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D3, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D3, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D3, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D3, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D3, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D3, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D3, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D4, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D4, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D4, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D4, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D4, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D4, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D4, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D4, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D4, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D5, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D5, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D5, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D5, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D5, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D5, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D5, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D5, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D5, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D6, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D6, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D6, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D6, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D6, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D6, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D6, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D6, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D6, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D7, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D7, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D7, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D7, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D7, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D7, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D7, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D7, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D7, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A8, "ED0", DATA_A8,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_ED0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_ED0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_ED0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_ED0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_ED0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_ED0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_ED0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_ED0, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_ED0, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB512X9SAR_1_VITAL of RAMB512X9SAR_1 is
   for VITAL
   end for;
end CFG_RAMB512X9SAR_1_VITAL;

----- CELL RAMB512X9SAF -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9SAF is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADD0_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      ADD8                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9SAF : entity is TRUE;
end RAMB512X9SAF;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9SAF is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL ADD8_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512(init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);
	VitalWireDelay (ADD8_ipd,    ADD8,      tipd_ADD8);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                ADD8_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '1' and WEN_ipd = '1') then
        rd_add_a(8) <= ADD8_ipd;
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd )

   begin
    if (WEN_ipd = '0' ) then
	wr_clk <= RWCLK_ipd;
    else
	wr_clk <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADD8_ipd,
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(8) <= ADD8_ipd;
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED0_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(8) <= ED0_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9SAF Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk, 
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD8_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD8_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK                : std_ulogic := '0';
        variable PInfo_RWCLK                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD8_RWCLK_posedge,
          TimingData              => Tmkr_ADD8_RWCLK_posedge,
          TestSignal              => ADD8_ipd,
          TestSignalName          => "ADD8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD8_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD8_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD8_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9SAF",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';

    BEGIN

      con_a := VitalAND2(OE_ipd, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);

      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D0, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D0, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D1, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D1, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D1, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D1, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D1, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D1, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D1, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D1, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D1, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D2, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D2, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D2, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D2, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D2, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D2, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D2, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D2, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D2, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D3, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D3, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D3, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D3, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D3, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D3, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D3, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D3, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D3, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D4, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D4, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D4, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D4, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D4, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D4, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D4, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D4, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D4, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D5, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D5, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D5, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D5, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D5, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D5, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D5, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D5, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D5, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D6, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D6, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D6, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D6, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D6, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D6, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D6, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D6, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D6, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D7, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D7, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D7, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D7, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D7, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D7, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D7, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D7, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D7, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A8, "ED0", DATA_A8,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_ED0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_ED0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_ED0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_ED0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_ED0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_ED0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_ED0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_ED0, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_ED0, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB512X9SAF_VITAL of RAMB512X9SAF is
   for VITAL
   end for;
end CFG_RAMB512X9SAF_VITAL;

----- CELL RAMB512X9SAF_1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library LAVA1;
use LAVA1.RAM_PACKAGE.all;

-- entity declaration --
entity RAMB512X9SAF_1 is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_ADD0_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD0_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD1_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD2_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD3_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD4_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD5_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD6_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD7_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D0                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D1                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D2                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D3                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D4                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D5                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D6                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_D7                    :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_ADD8_ED0                   :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D0                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D1                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D2                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D3                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D4                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D5                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D6                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_D7                      :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);
      tpd_OE_ED0                     :	VitalDelayType01Z := (0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns, 0.0 ns);

      tsetup_WEN_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      thold_WEN_RWCLK_noedge_posedge    :	VitalDelayType   := 0.0 ns;

      tsetup_ADD0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ADD8_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_ADD8_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;

      tsetup_D0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D0_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D1_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D1_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D2_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D2_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D3_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D3_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D4_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D4_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D5_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D5_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D6_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D6_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_D7_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;
      thold_D7_RWCLK_noedge_posedge   :	VitalDelayType   := 0.0 ns;
      tsetup_ED0_RWCLK_noedge_posedge :	VitalDelayType   := 0.0 ns;
      thold_ED0_RWCLK_noedge_posedge  :	VitalDelayType   := 0.0 ns;

      tpw_RWCLK_posedge                :	VitalDelayType   := 2.0 ns;

      tipd_WEN                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_RWCLK                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_OE                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_ADD0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD5                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD6                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD7                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ADD8                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      tipd_D0                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D1                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D2                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D3                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D4                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D5                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D6                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D7                          :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_ED0                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);

      INIT01                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT02                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT03                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT04                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT05                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT06                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT07                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT08                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
      INIT09                           :	bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

   port(
      WEN                           :	in    STD_ULOGIC;
      RWCLK                         :	in    STD_ULOGIC;
      OE                            :	in    STD_ULOGIC;
      ADD0                          :	in    STD_ULOGIC;
      ADD1                          :	in    STD_ULOGIC;
      ADD2                          :	in    STD_ULOGIC;
      ADD3                          :	in    STD_ULOGIC;
      ADD4                          :	in    STD_ULOGIC;
      ADD5                          :	in    STD_ULOGIC;
      ADD6                          :	in    STD_ULOGIC;
      ADD7                          :	in    STD_ULOGIC;
      ADD8                          :	in    STD_ULOGIC;
      D0                            :	inout STD_ULOGIC;
      D1                            :	inout STD_ULOGIC;
      D2                            :	inout STD_ULOGIC;
      D3                            :	inout STD_ULOGIC;
      D4                            :	inout STD_ULOGIC;
      D5                            :	inout STD_ULOGIC;
      D6                            :	inout STD_ULOGIC;
      D7                            :	inout STD_ULOGIC;
      ED0                           :	inout STD_ULOGIC);
attribute VITAL_LEVEL0 of RAMB512X9SAF_1 : entity is TRUE;
end RAMB512X9SAF_1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of RAMB512X9SAF_1 is
   ATTRIBUTE VITAL_LEVEL1 of VITAL   : ARCHITECTURE is FALSE;


      SIGNAL WEN_ipd                :   std_logic :='X';
      SIGNAL RWCLK_ipd              :   std_logic :='X';
      SIGNAL OE_ipd                 :   std_logic :='X';
      SIGNAL ADD0_ipd               :   std_logic :='X';
      SIGNAL ADD1_ipd               :   std_logic :='X';
      SIGNAL ADD2_ipd               :   std_logic :='X';
      SIGNAL ADD3_ipd               :   std_logic :='X';
      SIGNAL ADD4_ipd               :   std_logic :='X';
      SIGNAL ADD5_ipd               :   std_logic :='X';
      SIGNAL ADD6_ipd               :   std_logic :='X';
      SIGNAL ADD7_ipd               :   std_logic :='X';
      SIGNAL ADD8_ipd               :   std_logic :='X';
      SIGNAL D0_ipd                 :   std_logic :='X';
      SIGNAL D1_ipd                 :   std_logic :='X';
      SIGNAL D2_ipd                 :   std_logic :='X';
      SIGNAL D3_ipd                 :   std_logic :='X';
      SIGNAL D4_ipd                 :   std_logic :='X';
      SIGNAL D5_ipd                 :   std_logic :='X';
      SIGNAL D6_ipd                 :   std_logic :='X';
      SIGNAL D7_ipd                 :   std_logic :='X';
      SIGNAL ED0_ipd                :   std_logic :='X';

      SIGNAL data_out_a              :   std_logic_vector(8 downto 0) := z_data_9;

      SIGNAL rd_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL wr_clk                 :   std_logic  := 'X';

      SIGNAL wr_add_a                :   std_logic_vector(8 downto 0);

      SIGNAL din_a                   :   std_logic_vector(8 downto 0);

      constant init01_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT01)) ;
      constant init02_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT02)) ;
      constant init03_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT03)) ;
      constant init04_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT04)) ;
      constant init05_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT05)) ;
      constant init06_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT06)) ;
      constant init07_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT07)) ;
      constant init08_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT08)) ;
      constant init09_sig              :   std_logic_vector(511 downto 0 ) := ( To_StdLogicVector(INIT09)) ;

      signal memory_array            :   memory_array_typ_512  := FillInit512(init09_sig & 
                                         init08_sig & init07_sig & init06_sig & init05_sig & 
                                         init04_sig & init03_sig & init02_sig & init01_sig);

begin

  ---------------------------------------------------------------------
  -- INPUT PATH DELAYs
  ---------------------------------------------------------------------
  WIREDELAY : BLOCK
  BEGIN

	VitalWireDelay (WEN_ipd,     WEN,       tipd_WEN);
	VitalWireDelay (RWCLK_ipd,   RWCLK,     tipd_RWCLK);
	VitalWireDelay (OE_ipd,      OE,        tipd_OE);

	VitalWireDelay (ADD0_ipd,    ADD0,      tipd_ADD0);
	VitalWireDelay (ADD1_ipd,    ADD1,      tipd_ADD1);
	VitalWireDelay (ADD2_ipd,    ADD2,      tipd_ADD2);
	VitalWireDelay (ADD3_ipd,    ADD3,      tipd_ADD3);
	VitalWireDelay (ADD4_ipd,    ADD4,      tipd_ADD4);
	VitalWireDelay (ADD5_ipd,    ADD5,      tipd_ADD5);
	VitalWireDelay (ADD6_ipd,    ADD6,      tipd_ADD6);
	VitalWireDelay (ADD7_ipd,    ADD7,      tipd_ADD7);
	VitalWireDelay (ADD8_ipd,    ADD8,      tipd_ADD8);

	VitalWireDelay (D0_ipd,      D0,        tipd_D0);
	VitalWireDelay (D1_ipd,      D1,        tipd_D1);
	VitalWireDelay (D2_ipd,      D2,        tipd_D2);
	VitalWireDelay (D3_ipd,      D3,        tipd_D3);
	VitalWireDelay (D4_ipd,      D4,        tipd_D4);
	VitalWireDelay (D5_ipd,      D5,        tipd_D5);
	VitalWireDelay (D6_ipd,      D6,        tipd_D6);
	VitalWireDelay (D7_ipd,      D7,        tipd_D7);
	VitalWireDelay (ED0_ipd,     ED0,       tipd_ED0);

      END BLOCK;


  ---------------------------------------------------------------------
  -- Wrapper Section
  ---------------------------------------------------------------------

   wrapper_read_add_a : process(OE_ipd, 
                                ADD0_ipd, 
                                ADD1_ipd, 
                                ADD2_ipd, 
                                ADD3_ipd, 
                                ADD4_ipd, 
                                ADD5_ipd, 
                                ADD6_ipd, 
                                ADD7_ipd, 
                                ADD8_ipd, 
                                WEN_ipd)

   begin

   if ( OE_ipd = '0' and WEN_ipd = '1') then
        rd_add_a(8) <= ADD8_ipd;
        rd_add_a(7) <= ADD7_ipd;
        rd_add_a(6) <= ADD6_ipd;
        rd_add_a(5) <= ADD5_ipd;
        rd_add_a(4) <= ADD4_ipd;
        rd_add_a(3) <= ADD3_ipd;
        rd_add_a(2) <= ADD2_ipd;
        rd_add_a(1) <= ADD1_ipd;
        rd_add_a(0) <= ADD0_ipd;
   else
	rd_add_a <= x_add_9;
   end if;
   end process wrapper_read_add_a;

   wrapper_write_clk_a : process(WEN_ipd, RWCLK_ipd )

   begin
    if (WEN_ipd = '0' ) then
	wr_clk <= RWCLK_ipd;
    else
	wr_clk <= '1';
    end if;
   end process;

   write_address_a : process(
                            ADD8_ipd,
                            ADD7_ipd,
                            ADD6_ipd,
                            ADD5_ipd,
                            ADD4_ipd,
                            ADD3_ipd,
                            ADD2_ipd,
                            ADD1_ipd,
                            ADD0_ipd
                            )

    begin
        wr_add_a(8) <= ADD8_ipd;
        wr_add_a(7) <= ADD7_ipd;
        wr_add_a(6) <= ADD6_ipd;
        wr_add_a(5) <= ADD5_ipd;
        wr_add_a(4) <= ADD4_ipd;
        wr_add_a(3) <= ADD3_ipd;
        wr_add_a(2) <= ADD2_ipd;
        wr_add_a(1) <= ADD1_ipd;
        wr_add_a(0) <= ADD0_ipd;
   end process;

   wrapper_write_data_a : process(WEN_ipd, 
                                  ED0_ipd, 
                                  D7_ipd, 
                                  D6_ipd, 
                                  D5_ipd, 
                                  D4_ipd, 
                                  D3_ipd, 
                                  D2_ipd, 
                                  D1_ipd, 
                                  D0_ipd)

   begin
    if (WEN_ipd = '0') then
        din_a(8) <= ED0_ipd;
        din_a(7)  <= D7_ipd;
        din_a(6)  <= D6_ipd;
        din_a(5)  <= D5_ipd;
        din_a(4)  <= D4_ipd;
        din_a(3)  <= D3_ipd;
        din_a(2)  <= D2_ipd;
        din_a(1)  <= D1_ipd;
        din_a(0)  <= D0_ipd;
    else
	din_a <= x_data_9;
    end if;
   end process;

      --------------------
      -- RAMB512X9SAF_1 Write Behavior
      --------------------
      VITALBehavior_Write : Process (
                            memory_array,
                            wr_clk, 
                            din_a,
                            rd_add_a,
                            wr_add_a)
  
                

        -- Local variables used for timing checks
  
        variable tempaddr_a                  : integer     := 0;
	variable rd_address_a                : integer     := 0; 

        variable Tviol_WEN_RWCLK_posedge   : std_ulogic  := '0';

        variable Tviol_ADD0_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD1_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD2_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD3_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD4_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD5_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD6_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD7_RWCLK_posedge  : std_ulogic  := '0';
        variable Tviol_ADD8_RWCLK_posedge  : std_ulogic  := '0';

        variable Tviol_D0_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D1_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D2_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D3_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D4_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D5_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D6_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_D7_RWCLK_posedge    : std_ulogic  := '0';
        variable Tviol_ED0_RWCLK_posedge   : std_ulogic  := '0';

        variable Tmkr_WEN_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_ADD0_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD1_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD2_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD3_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD4_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD5_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD6_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD7_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ADD8_RWCLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

        variable Tmkr_D0_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D1_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D2_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D3_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D4_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D5_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D6_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_D7_RWCLK_posedge     : VitalTimingDataType := VitalTimingDataInit;
        variable Tmkr_ED0_RWCLK_posedge    : VitalTimingDataType := VitalTimingDataInit;

        variable PViol_RWCLK                : std_ulogic := '0';
        variable PInfo_RWCLK                : VitalPeriodDataType := VitalPeriodDataInit;

        -- Local variables used for functionality

        begin

    ------------------------
    --  Timing Check Section
    ------------------------
    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_WEN_RWCLK_posedge,
          TimingData              => Tmkr_WEN_RWCLK_posedge,
          TestSignal              => WEN_ipd,
          TestSignalName          => "WEN",
          TestDelay               => 0.1 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0.1 ns,
          SetupHigh               => tsetup_WEN_RWCLK_noedge_posedge,
          SetupLow                => tsetup_WEN_RWCLK_noedge_posedge,
          HoldLow                 => thold_WEN_RWCLK_noedge_posedge,
          HoldHigh                => thold_WEN_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD0_RWCLK_posedge,
          TimingData              => Tmkr_ADD0_RWCLK_posedge,
          TestSignal              => ADD0_ipd,
          TestSignalName          => "ADD0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD0_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD1_RWCLK_posedge,
          TimingData              => Tmkr_ADD1_RWCLK_posedge,
          TestSignal              => ADD1_ipd,
          TestSignalName          => "ADD1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD1_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD1_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD1_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD2_RWCLK_posedge,
          TimingData              => Tmkr_ADD2_RWCLK_posedge,
          TestSignal              => ADD2_ipd,
          TestSignalName          => "ADD2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD2_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD2_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD2_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD3_RWCLK_posedge,
          TimingData              => Tmkr_ADD3_RWCLK_posedge,
          TestSignal              => ADD3_ipd,
          TestSignalName          => "ADD3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD3_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD3_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD3_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD4_RWCLK_posedge,
          TimingData              => Tmkr_ADD4_RWCLK_posedge,
          TestSignal              => ADD4_ipd,
          TestSignalName          => "ADD4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD4_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD4_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD4_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD5_RWCLK_posedge,
          TimingData              => Tmkr_ADD5_RWCLK_posedge,
          TestSignal              => ADD5_ipd,
          TestSignalName          => "ADD5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD5_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD5_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD5_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD6_RWCLK_posedge,
          TimingData              => Tmkr_ADD6_RWCLK_posedge,
          TestSignal              => ADD6_ipd,
          TestSignalName          => "ADD6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD6_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD6_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD6_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD7_RWCLK_posedge,
          TimingData              => Tmkr_ADD7_RWCLK_posedge,
          TestSignal              => ADD7_ipd,
          TestSignalName          => "ADD7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD7_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD7_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD7_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ADD8_RWCLK_posedge,
          TimingData              => Tmkr_ADD8_RWCLK_posedge,
          TestSignal              => ADD8_ipd,
          TestSignalName          => "ADD8",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ADD8_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ADD8_RWCLK_noedge_posedge,
          HoldLow                 => thold_ADD8_RWCLK_noedge_posedge,
          HoldHigh                => thold_ADD8_RWCLK_noedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
         VitalSetupHoldCheck (
          Violation               => Tviol_D0_RWCLK_posedge,
          TimingData              => Tmkr_D0_RWCLK_posedge,
          TestSignal              => D0_ipd,
          TestSignalName          => "D0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D0_RWCLK_noedge_posedge,
          HoldLow                 => thold_D0_RWCLK_noedge_posedge,
          HoldHigh                => thold_D0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D1_RWCLK_posedge,
          TimingData              => Tmkr_D1_RWCLK_posedge,
          TestSignal              => D1_ipd,
          TestSignalName          => "D1",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D1_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D1_RWCLK_noedge_posedge,
          HoldLow                 => thold_D1_RWCLK_noedge_posedge,
          HoldHigh                => thold_D1_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D2_RWCLK_posedge,
          TimingData              => Tmkr_D2_RWCLK_posedge,
          TestSignal              => D2_ipd,
          TestSignalName          => "D2",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D2_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D2_RWCLK_noedge_posedge,
          HoldLow                 => thold_D2_RWCLK_noedge_posedge,
          HoldHigh                => thold_D2_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D3_RWCLK_posedge,
          TimingData              => Tmkr_D3_RWCLK_posedge,
          TestSignal              => D3_ipd,
          TestSignalName          => "D3",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D3_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D3_RWCLK_noedge_posedge,
          HoldLow                 => thold_D3_RWCLK_noedge_posedge,
          HoldHigh                => thold_D3_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D4_RWCLK_posedge,
          TimingData              => Tmkr_D4_RWCLK_posedge,
          TestSignal              => D4_ipd,
          TestSignalName          => "D4",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D4_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D4_RWCLK_noedge_posedge,
          HoldLow                 => thold_D4_RWCLK_noedge_posedge,
          HoldHigh                => thold_D4_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D5_RWCLK_posedge,
          TimingData              => Tmkr_D5_RWCLK_posedge,
          TestSignal              => D5_ipd,
          TestSignalName          => "D5",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D5_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D5_RWCLK_noedge_posedge,
          HoldLow                 => thold_D5_RWCLK_noedge_posedge,
          HoldHigh                => thold_D5_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D6_RWCLK_posedge,
          TimingData              => Tmkr_D6_RWCLK_posedge,
          TestSignal              => D6_ipd,
          TestSignalName          => "D6",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D6_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D6_RWCLK_noedge_posedge,
          HoldLow                 => thold_D6_RWCLK_noedge_posedge,
          HoldHigh                => thold_D6_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_D7_RWCLK_posedge,
          TimingData              => Tmkr_D7_RWCLK_posedge,
          TestSignal              => D7_ipd,
          TestSignalName          => "D7",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_D7_RWCLK_noedge_posedge,
          SetupLow                => tsetup_D7_RWCLK_noedge_posedge,
          HoldLow                 => thold_D7_RWCLK_noedge_posedge,
          HoldHigh                => thold_D7_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_ED0_RWCLK_posedge,
          TimingData              => Tmkr_ED0_RWCLK_posedge,
          TestSignal              => ED0_ipd,
          TestSignalName          => "ED0",
          TestDelay               => 0 ns,
          RefSignal               => RWCLK_ipd,
          RefSignalName           => "RWCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_ED0_RWCLK_noedge_posedge,
          SetupLow                => tsetup_ED0_RWCLK_noedge_posedge,
          HoldLow                 => thold_ED0_RWCLK_noedge_posedge,
          HoldHigh                => thold_ED0_RWCLK_noedge_posedge,
          CheckEnabled            => TO_X01(WEN_ipd) /= '1',
          RefTransition           => 'F',
          HeaderMsg               => InstancePath & "/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_RWCLK,
          PeriodData              => PInfo_RWCLK,
          TestSignal              => RWCLK_ipd,
          TestSignalName          => "RWCLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_RWCLK_posedge,
          PulseWidthLow           => tpw_RWCLK_posedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/RAMB512X9SAF_1",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;


    -------------------------
    --  Functionality Section
    -------------------------

    -- Port A
    if ( wr_clk'EVENT and wr_clk = '0' and vecX(wr_add_a)) then

        assert false
        report "Illegal Address Input: Undefined  Address at the Port A."
        severity note ;

    end if;

    if ( wr_clk'EVENT and wr_clk = '0' and not vecX(wr_add_a) ) then
	tempaddr_a := vec2int(wr_add_a);
	memory_array(tempaddr_a) <= din_a;
    end if;

    if ( not vecX(rd_add_a) ) then
	rd_address_a := vec2int(rd_add_a);
	data_out_a <= memory_array(rd_address_a);
    end if;

    end process VitalBehavior_Write;


    VitalBehavior_ReadA : process(data_out_a, RWCLK_ipd, OE_ipd)

    VARIABLE GLITCH_DATA_A0 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A1 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A2 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A3 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A4 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A5 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A6 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A7 : VitalGlitchDataType;
    VARIABLE GLITCH_DATA_A8 : VitalGlitchDataType;
    VARIABLE con_a : std_logic ;
    VARIABLE DATA_A0  : std_logic := 'Z';
    VARIABLE DATA_A1  : std_logic := 'Z';
    VARIABLE DATA_A2  : std_logic := 'Z';
    VARIABLE DATA_A3  : std_logic := 'Z';
    VARIABLE DATA_A4  : std_logic := 'Z';
    VARIABLE DATA_A5  : std_logic := 'Z';
    VARIABLE DATA_A6  : std_logic := 'Z';
    VARIABLE DATA_A7  : std_logic := 'Z';
    VARIABLE DATA_A8  : std_logic := 'Z';
    VARIABLE OE_inverted  : std_logic := 'Z';

    BEGIN

      OE_inverted := NOT (OE_ipd);
      con_a := VitalAND2(OE_inverted, WEN_ipd);

      DATA_A0  := VITALBUFIF1(data_out_a(0),con_a);
      DATA_A1  := VITALBUFIF1(data_out_a(1),con_a);
      DATA_A2  := VITALBUFIF1(data_out_a(2),con_a);
      DATA_A3  := VITALBUFIF1(data_out_a(3),con_a);
      DATA_A4  := VITALBUFIF1(data_out_a(4),con_a);
      DATA_A5  := VITALBUFIF1(data_out_a(5),con_a);
      DATA_A6  := VITALBUFIF1(data_out_a(6),con_a);
      DATA_A7  := VITALBUFIF1(data_out_a(7),con_a);
      DATA_A8  := VITALBUFIF1(data_out_a(8),con_a);

      VitalPathDelay01Z ( D0, GLITCH_DATA_A0, "D0", DATA_A0,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D0, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D0, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D1, GLITCH_DATA_A1, "D1", DATA_A1,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D1, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D1, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D1, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D1, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D1, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D1, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D1, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D1, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D1, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D1, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D2, GLITCH_DATA_A2, "D2", DATA_A2,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D2, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D2, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D2, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D2, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D2, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D2, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D2, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D2, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D2, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D2, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D3, GLITCH_DATA_A3, "D3", DATA_A3,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D3, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D3, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D3, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D3, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D3, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D3, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D3, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D3, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D3, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D3, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D4, GLITCH_DATA_A4, "D4", DATA_A4,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D4, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D4, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D4, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D4, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D4, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D4, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D4, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D4, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D4, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D4, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D5, GLITCH_DATA_A5, "D5", DATA_A5,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D5, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D5, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D5, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D5, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D5, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D5, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D5, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D5, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D5, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D5, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D6, GLITCH_DATA_A6, "D6", DATA_A6,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D6, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D6, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D6, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D6, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D6, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D6, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D6, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D6, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D6, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D6, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( D7, GLITCH_DATA_A7, "D7", DATA_A7,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_D7, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_D7, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_D7, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_D7, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_D7, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_D7, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_D7, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_D7, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_D7, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_D7, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

      VitalPathDelay01Z ( ED0, GLITCH_DATA_A8, "ED0", DATA_A8,
        Paths => (
        0 => ( ADD0_ipd'LAST_EVENT, tpd_ADD0_ED0, TRUE),
        1 => ( ADD1_ipd'LAST_EVENT, tpd_ADD1_ED0, TRUE),
        2 => ( ADD2_ipd'LAST_EVENT, tpd_ADD2_ED0, TRUE),
        3 => ( ADD3_ipd'LAST_EVENT, tpd_ADD3_ED0, TRUE),
        4 => ( ADD4_ipd'LAST_EVENT, tpd_ADD4_ED0, TRUE),
        5 => ( ADD5_ipd'LAST_EVENT, tpd_ADD5_ED0, TRUE),
        6 => ( ADD6_ipd'LAST_EVENT, tpd_ADD6_ED0, TRUE),
        7 => ( ADD7_ipd'LAST_EVENT, tpd_ADD7_ED0, TRUE),
        8 => ( ADD8_ipd'LAST_EVENT, tpd_ADD8_ED0, TRUE),
        9 => ( OE_ipd'LAST_EVENT, tpd_OE_ED0, TRUE )),
        DefaultDelay=>VitalZeroDelay01Z,
        Mode=>VitalInertial,
        XON=>TRUE,
        MsgOn=>TRUE,
        MsgSeverity=>WARNING );

    END process VitalBehavior_ReadA;

end VITAL;

configuration CFG_RAMB512X9SAF_1_VITAL of RAMB512X9SAF_1 is
   for VITAL
   end for;
end CFG_RAMB512X9SAF_1_VITAL;

----- CELL SHIFT8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity SHIFT8 is
   generic(
      TimingChecksOn: Boolean := TRUE;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := False;
      tpd_CLK_SO                      :   VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A0                        :   VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A1                        :   VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A2                        :   VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SI                        :   VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_EN                         :   VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CLK                        :   VitalDelayType01 := (0.000 ns, 0.000 ns);

      tsetup_A0_CLK_posedge_posedge  :   VitalDelayType := 0.01 ns;
      tsetup_A0_CLK_negedge_posedge  :   VitalDelayType := 0.01 ns;
      tsetup_A1_CLK_posedge_posedge  :   VitalDelayType := 0.01 ns;
      tsetup_A1_CLK_negedge_posedge  :   VitalDelayType := 0.01 ns;
      tsetup_A2_CLK_posedge_posedge  :   VitalDelayType := 0.01 ns;
      tsetup_A2_CLK_negedge_posedge  :   VitalDelayType := 0.01 ns;

      tsetup_EN_CLK_posedge_posedge   :   VitalDelayType := 0.01 ns;
      tsetup_EN_CLK_negedge_posedge   :   VitalDelayType := 0.01 ns;
      tsetup_SI_CLK_posedge_posedge  :   VitalDelayType := 0.01 ns;
      tsetup_SI_CLK_negedge_posedge  :   VitalDelayType := 0.01 ns;

      thold_A0_CLK_posedge_posedge   :   VitalDelayType := 0.01 ns;
      thold_A0_CLK_negedge_posedge   :   VitalDelayType := 0.01 ns;
      thold_A1_CLK_posedge_posedge   :   VitalDelayType := 0.01 ns;
      thold_A1_CLK_negedge_posedge   :   VitalDelayType := 0.01 ns;
      thold_A2_CLK_posedge_posedge   :   VitalDelayType := 0.01 ns;
      thold_A2_CLK_negedge_posedge   :   VitalDelayType := 0.01 ns;

      thold_EN_CLK_posedge_posedge    :   VitalDelayType := 0.01 ns;
      thold_EN_CLK_negedge_posedge    :   VitalDelayType := 0.01 ns;
      thold_SI_CLK_posedge_posedge   :   VitalDelayType := 0.01 ns;
      thold_SI_CLK_negedge_posedge   :   VitalDelayType := 0.01 ns;

      tpw_CLK_posedge : VitalDelayType := 0.01 ns;
      tpw_CLK_negedge : VitalDelayType := 0.01 ns;

      INIT : bit_vector := X"00"
  );

  port (
        SO  : out STD_ULOGIC;
        A0 : in STD_ULOGIC;
        A1 : in STD_ULOGIC;
        A2 : in STD_ULOGIC;
        EN  : in STD_ULOGIC;        
        CLK : in STD_ULOGIC;
        SI : in STD_ULOGIC
       ); 

attribute VITAL_LEVEL0 of SHIFT8 : entity is TRUE;

end SHIFT8;

--- Architecture 

library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of SHIFT8 is

  attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;

  -- Local signals used to propagate input wire delay

  signal A0_ipd  : std_ulogic := 'X';
  signal A1_ipd  : std_ulogic := 'X';
  signal A2_ipd  : std_ulogic := 'X';

  signal A0_ipd_n  : std_ulogic := 'X';
  signal A1_ipd_n  : std_ulogic := 'X';
  signal A2_ipd_n  : std_ulogic := 'X';

  signal SI_ipd  : std_ulogic := 'X';
  signal EN_ipd   : std_ulogic := 'X';
  signal CLK_ipd  : std_ulogic := 'X';

  signal SO_zd    : std_ulogic := 'X';

  signal SHIFTER  : std_logic_vector (8 downto 0) := ('X' & To_StdLogicVector(INIT));

 
begin 

  ----------------------
  --  INPUT PATH DELAYs
  ----------------------
  WireDelay : block
  begin
    VitalWireDelay (A0_ipd, A0, tipd_A0);
    VitalWireDelay (A1_ipd, A1, tipd_A1);
    VitalWireDelay (A2_ipd, A2, tipd_A2);

    VitalWireDelay (SI_ipd, SI, tipd_SI);
    VitalWireDelay (EN_ipd,  EN,  tipd_EN);
    VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
  end block;


    A0_ipd_n <= not A0_ipd;
    A1_ipd_n <= not A1_ipd;
    A2_ipd_n <= not A2_ipd;

  --------------------
  -- BEHAVIOR SECTIOIN
  --------------------
  VITALOutputBehavior : process(A0_ipd_n, A1_ipd_n, A2_ipd_n, SHIFTER)

    variable O_zd : std_logic := 'X';

  begin -- process

    O_zd := VitalMUX
             (data    => SHIFTER(7 downto 0), 
              dselect => (A2_ipd_n, A1_ipd_n, A0_ipd_n));
    SO_zd <= O_zd;

  end process VITALOutputBehavior;

  VITALShiftBehavior : process

    variable Initial : boolean := TRUE;

  begin -- process

    if (Initial) then
        wait until ((EN_ipd = '1' or EN_ipd = '0') and
                   (CLK_ipd'last_value = '0' or CLK_ipd'last_value = '1') and
                   (CLK_ipd = '0' or CLK_ipd = '1'));
        Initial := FALSE;
    end if;

    if (CLK_ipd'event AND CLK_ipd = '1') then
            if (EN_ipd = '0') then
                    for I in 7 downto 1 loop
                        SHIFTER(I) <= SHIFTER(I-1); -- shift
                    end loop;
                SHIFTER(0) <= SI_ipd;
            elsif (EN_ipd = 'X') then
                SHIFTER <= (others => 'X');
            end if;
    elsif (CLK_ipd'event AND CLK_ipd = 'X') then
            if (EN_ipd /= '1') then
                SHIFTER <= (others => 'X');
            end if;
    end if;

    wait on CLK_ipd;

  end process VITALShiftBehavior;


    ------------------------
    --  Timing Check Section
    ------------------------
  VITALTiming : process (A0_ipd, A1_ipd, A2_ipd, CLK_ipd, EN_ipd, SI_ipd, SO_zd)

    -- Local variables used for timing checks
    variable Tviol_A0_CLK_posedge  : std_ulogic := '0';
    variable Tviol_A1_CLK_posedge  : std_ulogic := '0';
    variable Tviol_A2_CLK_posedge  : std_ulogic := '0';

    variable Tviol_SI_CLK_posedge  : std_ulogic := '0';
    variable Tviol_EN_CLK_posedge   : std_ulogic := '0';

    variable Tmkr_A0_CLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_A1_CLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_A2_CLK_posedge   : VitalTimingDataType := VitalTimingDataInit;

    variable Tmkr_SI_CLK_posedge   : VitalTimingDataType := VitalTimingDataInit;
    variable Tmkr_EN_CLK_posedge    : VitalTimingDataType := VitalTimingDataInit;
 
    variable PViol_CLK : std_ulogic := '0';
    variable PInfo_CLK : VitalPeriodDataType := VitalPeriodDataInit;

    -- Local variables used for functionality
    variable Violation : std_ulogic := '0';
    variable SO_zdt : std_ulogic := '0';
    variable SO_GlitchData : VitalGlitchDataType;

   begin

    SO_zdt := SO_zd;

    if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_SI_CLK_posedge,
          TimingData              => Tmkr_SI_CLK_posedge,
          TestSignal              => SI_ipd,
          TestSignalName          => "SI",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_SI_CLK_posedge_posedge,
          SetupLow                => tsetup_SI_CLK_negedge_posedge,
          HoldLow                 => thold_SI_CLK_posedge_posedge,
          HoldHigh                => thold_SI_CLK_negedge_posedge,
          CheckEnabled            => (TO_X01(EN_ipd) = '0'),
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/SHIFT8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_A0_CLK_posedge,
          TimingData              => Tmkr_A0_CLK_posedge,
          TestSignal              => A0_ipd,
          TestSignalName          => "A0",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_A0_CLK_posedge_posedge,
          SetupLow                => tsetup_A0_CLK_negedge_posedge,
          HoldLow                 => thold_A0_CLK_posedge_posedge,
          HoldHigh                => thold_A0_CLK_negedge_posedge,
          CheckEnabled            => (TO_X01(EN_ipd) = '0'),
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/SHIFT8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_A1_CLK_posedge,
          TimingData              => Tmkr_A1_CLK_posedge,
          TestSignal              => A1_ipd,
          TestSignalName          => "A1",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_A1_CLK_posedge_posedge,
          SetupLow                => tsetup_A1_CLK_negedge_posedge,
          HoldLow                 => thold_A1_CLK_posedge_posedge,
          HoldHigh                => thold_A1_CLK_negedge_posedge,
          CheckEnabled            => (TO_X01(EN_ipd) = '0'),
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/SHIFT8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_A2_CLK_posedge,
          TimingData              => Tmkr_A2_CLK_posedge,
          TestSignal              => A2_ipd,
          TestSignalName          => "A2",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_A2_CLK_posedge_posedge,
          SetupLow                => tsetup_A2_CLK_negedge_posedge,
          HoldLow                 => thold_A2_CLK_posedge_posedge,
          HoldHigh                => thold_A2_CLK_negedge_posedge,
          CheckEnabled            => (TO_X01(EN_ipd) = '0'),
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/SHIFT8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_EN_CLK_posedge,
          TimingData              => Tmkr_EN_CLK_posedge,
          TestSignal              => EN_ipd,
          TestSignalName          => "EN",
          TestDelay               => 0 ns,
          RefSignal               => CLK_ipd,
          RefSignalName           => "CLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_EN_CLK_posedge_posedge,
          SetupLow                => tsetup_EN_CLK_negedge_posedge,
          HoldLow                 => thold_EN_CLK_posedge_posedge,
          HoldHigh                => thold_EN_CLK_negedge_posedge,
          CheckEnabled            => TRUE,
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/SHIFT8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalPeriodPulseCheck (
          Violation               => Pviol_CLK,
          PeriodData              => PInfo_CLK,
          TestSignal              => CLK_ipd,
          TestSignalName          => "CLK",
          TestDelay               => 0 ns,
          Period                  => 0 ns,
          PulseWidthHigh          => tpw_CLK_posedge,
          PulseWidthLow           => tpw_CLK_negedge,
          CheckEnabled            => TRUE,
          HeaderMsg               => InstancePath &"/SHIFT8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

    end if;

    Violation := Tviol_SI_CLK_posedge or Tviol_EN_CLK_posedge or
                 Tviol_A0_CLK_posedge or Tviol_A1_CLK_posedge or
                 Tviol_A2_CLK_posedge or Pviol_CLK;

    SO_zdt := Violation XOR SO_zdt;

    ----------------------
    --  Path Delay Section
    ----------------------
    VitalPathDelay01 (
      OutSignal => SO,
      GlitchData => SO_GlitchData,
      OutSignalName => "SO",
      OutTemp => SO_zdt,
      Paths => (0 => (CLK_ipd'last_event, tpd_CLK_SO, TRUE)),
      Mode => VitalInertial,
      Xon => Xon,
      MsgOn => MsgOn,
      MsgSeverity => WARNING);

  end process VITALTiming;

end VITAL;

configuration CFG_SHIFT8_VITAL of SHIFT8 is
   for VITAL
   end for;
end CFG_SHIFT8_VITAL;


----- CELL UCP_LSB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity UCP_LSB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_SD_S0                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LOAD_S0                    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CYIBAR_S0                  :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_LOAD_COUT                  :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CYIBAR_COUT                :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_LOAD                      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CYIBAR                    :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      SD                             :	in    STD_ULOGIC;
      LOAD                           :	in    STD_ULOGIC;
      CYIBAR                         :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of UCP_LSB : entity is TRUE;
end UCP_LSB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of UCP_LSB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL SD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL LOAD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CYIBAR_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (SD_ipd, SD, tipd_SD);
   VitalWireDelay (LOAD_ipd, LOAD, tipd_LOAD);
   VitalWireDelay (CYIBAR_ipd, CYIBAR, tipd_CYIBAR);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, SD_ipd, LOAD_ipd, CYIBAR_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd :=
       ((NOT CYIBAR_ipd)) XOR ((((NOT LOAD_ipd)) AND (D_ipd)) OR ((LOAD_ipd)
         AND (SD_ipd)));
      COUT_zd := ((((NOT LOAD_ipd)) AND (D_ipd)) OR ((LOAD_ipd)
         AND (SD_ipd))) AND ((NOT CYIBAR_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (SD_ipd'last_event, tpd_SD_S0, TRUE),
                 1 => (LOAD_ipd'last_event, tpd_LOAD_S0, TRUE),
                 2 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 3 => (CYIBAR_ipd'last_event, tpd_CYIBAR_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (LOAD_ipd'last_event, tpd_LOAD_COUT, TRUE),
                 1 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 2 => (CYIBAR_ipd'last_event, tpd_CYIBAR_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_UCP_LSB_VITAL of UCP_LSB is
   for VITAL
   end for;
end CFG_UCP_LSB_VITAL;


----- CELL UC_LSB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity UC_LSB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_S0                  :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CIN_COUT                :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CIN                    :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      CIN                         :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of UC_LSB : entity is TRUE;
end UC_LSB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of UC_LSB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CIN_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (CIN_ipd, CIN, tipd_CIN);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, CIN_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := (CIN_ipd) XOR (D_ipd);
      COUT_zd := (CIN_ipd) AND (D_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 1 => (CIN_ipd'last_event, tpd_CIN_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_UC_LSB_VITAL of UC_LSB is
   for VITAL
   end for;
end CFG_UC_LSB_VITAL;


----- CELL UDC_LSB -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity UDC_LSB is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True;
      tpd_D_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_UD_S0                       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CYIBAR_S0                  :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_D_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_UD_COUT                     :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tpd_CYIBAR_COUT                :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_UD                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CYIBAR                    :	VitalDelayType01 := (0.000 ns, 0.000 ns));

   port(
      D                              :	in    STD_ULOGIC;
      UD                             :	in    STD_ULOGIC;
      CYIBAR                         :	in    STD_ULOGIC;
      S0                             :	out   STD_ULOGIC;
      COUT                           :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of UDC_LSB : entity is TRUE;
end UDC_LSB;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of UDC_LSB is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL D_ipd	 : STD_ULOGIC := 'X';
   SIGNAL UD_ipd	 : STD_ULOGIC := 'X';
   SIGNAL CYIBAR_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (D_ipd, D, tipd_D);
   VitalWireDelay (UD_ipd, UD, tipd_UD);
   VitalWireDelay (CYIBAR_ipd, CYIBAR, tipd_CYIBAR);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (D_ipd, UD_ipd, CYIBAR_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 3) := (others => 'X');
   ALIAS S0_zd : STD_LOGIC is Results(1);
   ALIAS COUT_zd : STD_LOGIC is Results(2);

   -- output glitch detection variables
   VARIABLE S0_GlitchData	: VitalGlitchDataType;
   VARIABLE COUT_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      S0_zd := D_ipd XOR UD_ipd XOR (NOT CYIBAR_ipd);
      COUT_zd := (D_ipd AND UD_ipd) OR (NOT CYIBAR_ipd AND (D_ipd)) OR (UD_ipd AND (NOT CYIBAR_ipd));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => S0,
       GlitchData => S0_GlitchData,
       OutSignalName => "S0",
       OutTemp => S0_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_S0, TRUE),
                 1 => (CYIBAR_ipd'last_event, tpd_CYIBAR_S0, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);
      VitalPathDelay01 (
       OutSignal => COUT,
       GlitchData => COUT_GlitchData,
       OutSignalName => "COUT",
       OutTemp => COUT_zd,
       Paths => (0 => (D_ipd'last_event, tpd_D_COUT, TRUE),
                 1 => (CYIBAR_ipd'last_event, tpd_CYIBAR_COUT, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_UDC_LSB_VITAL of UDC_LSB is
   for VITAL
   end for;
end CFG_UDC_LSB_VITAL;


----- CELL VCC -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;


-- entity declaration --
entity VCC is
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := False;
      MsgOn: Boolean := True);

   port(
      X                              :	out   STD_ULOGIC := '1');
attribute VITAL_LEVEL0 of VCC : entity is TRUE;
end VCC;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL of VCC is
   attribute VITAL_LEVEL0 of VITAL : architecture is TRUE;


begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   --  empty
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   X <= '1';


end VITAL;

configuration CFG_VCC_VITAL of VCC is
   for VITAL
   end for;
end CFG_VCC_VITAL;

----- VITAL model for cell CDRX_10B12B -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library LAVA1;
use LAVA1.components.all;

-- entity declaration --
entity CDRX_10B12B is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "12";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PLL_DLY  : string  := "0.0";
      --ct020805 SYMPAT   : string  := "00000000111111000000";
	SYMPAT   : string  := "111111000000";

      F_LKDBW  : string  := "00001111";
      F_LKTBW  : string  := "00111111";
      F_TKDBW  : string  := "00011111";
      F_TKTBW  : string  := "01111111";
      F_LOCK   : string  := "011";

      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tipd_REFCLK    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SIN       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CDRRST    :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      SIN               : in    STD_ULOGIC;
      REFCLK            : in    STD_ULOGIC;
      CDRRST            : in    STD_ULOGIC;
      RXD0              : out   STD_ULOGIC;
      RXD1              : out   STD_ULOGIC;
      RXD2              : out   STD_ULOGIC;
      RXD3              : out   STD_ULOGIC;
      RXD4              : out   STD_ULOGIC;
      RXD5              : out   STD_ULOGIC;
      RXD6              : out   STD_ULOGIC;
      RXD7              : out   STD_ULOGIC;
      RXD8              : out   STD_ULOGIC;
      RXD9              : out   STD_ULOGIC;
      RECCLK            : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC;
      SYDT              : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CDRX_10B12B : entity is FALSE;
end CDRX_10B12B;


architecture VITAL of CDRX_10B12B is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL REFCLK_ipd	 : STD_ULOGIC := '0';
  SIGNAL SIN_ipd	 : STD_ULOGIC := '0';
  SIGNAL CDRRST_ipd	 : STD_ULOGIC := '0';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL clklock_half_period1 : TIME :=100 ns;
  SIGNAL clklock_half_period0 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly1 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly0 : TIME :=100 ns;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_falling_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;

  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;

  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  --ct020805 SIGNAL sympat_sig1  : std_logic_vector(19 downto 0) := str2std(sympat);
  --SIGNAL sympat_sig  : std_logic_vector(19 downto 0); -- := str2std(sympat);

  SIGNAL sympat_sig1  : std_logic_vector(11 downto 0) := str2std(sympat);
  SIGNAL sympat_sig  : std_logic_vector(11 downto 0); -- := str2std(sympat);


  CONSTANT clockboost: integer := str2int(mult) / str2int(div);
  CONSTANT tpd: time := 1.0 ns * str2real(pll_dly);

  SIGNAL  RECCLK_sig     : std_logic := '0';
  SIGNAL  CDRLOCK        : std_logic := '0';

  SIGNAL  intrecclk      : std_logic := '0';
  SIGNAL  inthsrecclk    : std_logic_vector(15 downto 0);
  SIGNAL  store_buffer   : std_logic_vector(15 downto 0);
  SIGNAL  shift_buffer, shift_buffer_d   : std_logic_vector(15 downto 0) := (others => '0');
  SIGNAL  aclk, sclk     : std_logic := '0';
  SIGNAL  sclksel        : std_logic_vector(15 downto 0);
  SIGNAL  data_ins, data_ina, data_inaa  : std_logic := '0';
  SIGNAL  time_data, time_clock, time_delta  : time ;
  SIGNAL  transition     : std_logic := '0';
  SIGNAL  dn_ss, dn_s, up_s, dn_clk, up_clk  : std_logic := '0';
  SIGNAL  cntrst, pcntrst   : std_logic := '0';
  SIGNAL  dn_cnt0, up_cnt0, dn_cnt, up_cnt  : std_logic_vector(7 downto 0) := (others => '0');
  SIGNAL  sub_cnt    : std_logic_vector(8 downto 0) := (others => '0');  
  SIGNAL  add_cnt, diff_cnt    : std_logic_vector(7 downto 0) := (others => '0');
  SIGNAL  lkdbw      : std_logic_vector(7 downto 0) := str2std(F_LKDBW);
  SIGNAL  lktbw      : std_logic_vector(7 downto 0) := str2std(F_LKTBW);
  SIGNAL  tkdbw      : std_logic_vector(7 downto 0) := str2std(F_TKDBW);
  SIGNAL  tktbw      : std_logic_vector(7 downto 0) := str2std(F_TKTBW);
  SIGNAL  dbw, tbw   : std_logic_vector(7 downto 0) := (others => '0');
  SIGNAL  diffcmp, totce, totcmp, totcmp_d    : std_logic := '0';
  SIGNAL  pre_pull, pre_push, pull, push      : std_logic := '0';
  SIGNAL  lock_rst   : std_logic := '0';
  SIGNAL  lock_cnt   : std_logic_vector(2 downto 0) := "000";
  SIGNAL  lockcmp, lockcmp_d1, lockcmp_d2  : std_logic := '0';
  SIGNAL  lock_int, lock0, lock1, lock2   : std_logic  := '0';
  SIGNAL  lock_pulse  : std_logic := '0';
  SIGNAL  align, pre_align  : std_logic  := '0';
  SIGNAL  rsypt0, rsypt1, rsypt2   : std_logic := '0';
  SIGNAL  divcnt          : std_logic_vector(2 downto 0) := "000";
  SIGNAL  intrecclk1, intrecclk2      : std_logic := '0';
  SIGNAL  divcnt_start      : std_logic := '0';

BEGIN
   -- ct020805
   sympat_sig(0) <= sympat_sig1(11);
   sympat_sig(1) <= sympat_sig1(10);
   sympat_sig(2) <= sympat_sig1(9);
   sympat_sig(3) <= sympat_sig1(8);
   sympat_sig(4) <= sympat_sig1(7);
   sympat_sig(5) <= sympat_sig1(6);
   sympat_sig(6) <= sympat_sig1(5);
   sympat_sig(7) <= sympat_sig1(4);
   sympat_sig(8) <= sympat_sig1(3);
   sympat_sig(9) <= sympat_sig1(2);
   sympat_sig(10) <= sympat_sig1(1);
   sympat_sig(11) <= sympat_sig1(0);

   WireDelay : block
   begin
   VitalWireDelay (REFCLK_ipd, REFCLK, tipd_REFCLK);
   VitalWireDelay (CDRRST_ipd, CDRRST, tipd_CDRRST);
   VitalWireDelay (SIN_ipd, SIN, tipd_SIN);
   end block;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

       clklock_half_period <= (clklock_half_period0 + clklock_half_period1)/2;

  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     IF clklock_rising_edge_count = 0 THEN
        clklock_last_rising_edge <= NOW;	
	start_inclk <= REFCLK_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
       clklock_half_period0 <= (NOW - clklock_last_falling_edge)* str2int(div)/str2int(mult);
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     elsif clklock_rising_edge_count = 2 THEN
       clklock_half_period_minus_dly0 <= (NOW - clklock_last_falling_edge) + tpd;
       --clklock_half_period <= (clklock_half_period0 + clklock_half_period1)/2;
     END IF;
     END IF;
 
  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='0');
     clklock_falling_edge_count <= clklock_falling_edge_count +1;	  	
     IF clklock_falling_edge_count = 0 THEN	
	clklock_last_falling_edge <= NOW;
	clklock_half_period1 <= (NOW - clklock_last_rising_edge)* str2int(div)/str2int(mult); 
     ELSIF clklock_falling_edge_count = 1 THEN
        clklock_half_period_minus_dly1 <= (NOW - clklock_last_rising_edge) + tpd;
     END IF;
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc + 1 THEN
         if(clockboost >1) then
	   FOR i IN 1 TO (2*clockboost) LOOP 	     
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

process
begin
    wait until CLK_OUT_sig_d_start = '1'; LOOP
     wait for clklock_half_period1;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not;
     wait for clklock_half_period0;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not ;
   END LOOP;
end process;

process
begin
   wait until (clklock_falling_edge_count >= lock_cyc + 1);
    wait for clklock_half_period_minus_dly0;
   CLK_OUT_start <= '1';
end process;

process
begin
   wait until  CLK_OUT_start = '1'; LOOP
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d;
     wait for clklock_half_period1;
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d ;
     wait for clklock_half_period0;
     END LOOP;
end process;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ;

    CSLOCK  <= CSLOCK_sig;
    RECCLK <= RECCLK_sig;

--#################
--#16-phase clocks#
--#################

    inthsrecclk(0) <= CLK_OUT_plus_delay;
    inthsrecclk(1) <= inthsrecclk(0) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(2) <= inthsrecclk(1) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(3) <= inthsrecclk(2) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(4) <= inthsrecclk(3) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(5) <= inthsrecclk(4) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(6) <= inthsrecclk(5) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(7) <= inthsrecclk(6) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(8) <= inthsrecclk(7) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(9) <= inthsrecclk(8) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(10) <= inthsrecclk(9) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(11) <= inthsrecclk(10) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(12) <= inthsrecclk(11) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(13) <= inthsrecclk(12) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(14) <= inthsrecclk(13) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(15) <= inthsrecclk(14) after (clklock_half_period*2*str2int(div)/str2int(mult));

--#################
--#digitial filter#
--#################

  process(sclk, SIN_ipd)
  begin
     if (sclk'event and sclk = '1') then
         data_ins <= SIN_ipd;
     end if;
  end process;

  process
  begin
      WAIT UNTIL (SIN_ipd'EVENT); 
         time_data <= NOW;
  end process;

  process
  begin
      WAIT UNTIL (aclk'EVENT AND aclk='1');
         time_clock <= NOW;
  end process;

  process(time_data, time_clock)
  begin
     if(time_data >= time_clock) then
          time_delta <= time_data - time_clock;
     else
          time_delta <= time_clock - time_data;
     end if;
  end process;

  process(aclk, SIN_ipd)
  begin
     if (aclk'event and aclk = '1') then
         data_inaa <= SIN_ipd;
     end if;
  end process;

  process(aclk, time_delta, data_inaa)
  begin
     if(aclk = '1') then
        if (time_delta < 100 ps) then
            data_ina <= 'X';
        else
            data_ina <= data_inaa;
        end if;
     end if;
  end process;
         
  transition <= data_ins XOR data_ina;

  process(sclk, transition)
  begin
    if (sclk = '1') then
        dn_ss <= transition;
    end if;
  end process;

  process(sclk)
  begin
    if (sclk'event and sclk = '1') then
        dn_s <= dn_ss;
    end if;
  end process;

  process(sclk)
  begin
    if (sclk'event and sclk = '1') then
        up_s <= transition;
    end if;
  end process;

  dn_clk <= dn_s and aclk;
  up_clk <= up_s and aclk;

  process(dn_clk, cntrst)
  begin
      if (cntrst = '1') then
          dn_cnt0 <= "00000000";
      elsif((dn_clk'event and dn_clk = '1') or (dn_clk'event and dn_clk = 'X')) then
          dn_cnt0 <= dn_cnt0 + "00000001";
      end if;
  end process;

  process(up_clk, cntrst)
  begin
      if (cntrst = '1') then
          up_cnt0 <= "00000000";
      elsif((up_clk'event and up_clk = '1') or (up_clk'event and up_clk = 'X')) then
          up_cnt0 <= dn_cnt0 + "00000001";
      end if;
  end process;

  process(aclk)
  begin
    if(aclk'event and aclk = '1') then
        dn_cnt <= dn_cnt0;
        up_cnt <= up_cnt0;
    end if;
  end process;

  process(aclk, cntrst)
  begin
    if(cntrst = '1') then
        sub_cnt <= "000000000";
        add_cnt <= "00000000";
    elsif(aclk'event and aclk = '1') then
        add_cnt <= dn_cnt + up_cnt;
    end if;
  end process;

  dbw <= tkdbw when (CDRLOCK = '1') else lkdbw;
  tbw <= tktbw when (CDRLOCK = '1') else lktbw;

  diff_cnt <= not (sub_cnt(7 downto 0)) when (sub_cnt(8) = '1') else sub_cnt(7 downto 0);

  process(aclk, cntrst)
  begin
    if(cntrst = '1') then
        diffcmp <= '0';
    elsif(aclk'event and aclk = '1') then
       if(diff_cnt >= dbw) then
          diffcmp <= '1';
       else
          diffcmp <= '0';
       end if;
    end if;
  end process;

  totce <= '1' when (add_cnt(7 downto 1) = tbw(7 downto 1)) else '0';

  process(aclk, CDRRST_ipd)
  begin
    if(CDRRST_ipd = '1') then
       totcmp <= '0';
    elsif(aclk'event and aclk = '1') then
       totcmp <= totce;
    end if;
  end process;

  process(aclk, CDRRST_ipd)
  begin
    if(CDRRST_ipd = '1') then
       totcmp_d <= '0';
    elsif(aclk'event and aclk = '1') then
       totcmp_d <= totcmp;
    end if;
  end process;

  cntrst <= CDRRST_ipd or totcmp;
  pcntrst <= CDRRST_ipd or totcmp_d;

  process(aclk, pcntrst) 
  begin
    if(pcntrst = '1') then
       pre_push <= '0';
       pre_pull <= '0';
    elsif(aclk'event and aclk = '1') then
       if(totce = '1') then
           pre_push <= diffcmp and not sub_cnt(8);
           pre_pull <= diffcmp and sub_cnt(8);
       end if;
    end if;
  end process;

  process(aclk, CDRRST_ipd)
  begin
    if(CDRRST_ipd = '1') then
        push <= '0';
        pull <= '0';
    elsif(aclk'event and aclk = '1') then
        push <= pre_push;
        pull <= pre_pull;
    end if;
  end process;

--########################
--#phase shift and select#
--########################

  process(aclk, CDRRST_ipd)
  begin
    if(CDRRST_ipd = '1') then
        sclksel <= X"0100";
    elsif(aclk'event and aclk = '1') then
        if(pull = '1') then
            sclksel <= sclksel(0) & sclksel(15 downto 1);
        elsif(push = '1') then
            sclksel <= sclksel(14 downto 0) & sclksel(15);
        end if;
    end if;
  end process;

  process(sclksel, inthsrecclk)
  begin
     case sclksel is
        when X"0001"  =>  
                   aclk <= inthsrecclk(8);
                   sclk <= inthsrecclk(0);
        when X"0002"  => 
                   aclk <= inthsrecclk(9);
                   sclk <= inthsrecclk(1);
        when X"0004"  => 
                   aclk <= inthsrecclk(10);
                   sclk <= inthsrecclk(2);
        when X"0008"  => 
                   aclk <= inthsrecclk(11);
                   sclk <= inthsrecclk(3);
        when X"0010"  => 
                   aclk <= inthsrecclk(12);
                   sclk <= inthsrecclk(4);
        when X"0020"  => 
                   aclk <= inthsrecclk(13);
                   sclk <= inthsrecclk(5);
        when X"0040"  => 
                   aclk <= inthsrecclk(14);
                   sclk <= inthsrecclk(6);
        when X"0080"  => 
                   aclk <= inthsrecclk(15);
                   sclk <= inthsrecclk(7);
        when X"0100"  => 
                   aclk <= inthsrecclk(0);
                   sclk <= inthsrecclk(8);
        when X"0200"  => 
                   aclk <= inthsrecclk(1);
                   sclk <= inthsrecclk(9);
        when X"0400"  => 
                   aclk <= inthsrecclk(2);
                   sclk <= inthsrecclk(10);
        when X"0800"  => 
                   aclk <= inthsrecclk(3);
                   sclk <= inthsrecclk(11);
        when X"1000"  => 
                   aclk <= inthsrecclk(4);
                   sclk <= inthsrecclk(12);
        when X"2000"  => 
                   aclk <= inthsrecclk(5);
                   sclk <= inthsrecclk(13);
        when X"4000"  => 
                   aclk <= inthsrecclk(6);
                   sclk <= inthsrecclk(14);
        when X"8000"  => 
                   aclk <= inthsrecclk(7);
                   sclk <= inthsrecclk(15);
        when others   => 
                   aclk <= inthsrecclk(0);
                   sclk <= inthsrecclk(8);
     end case;
   end process;

--#############
--#LOCK detect#
--#############

   lock_rst <= CDRRST_ipd or pull or push;

   process(totcmp, lock_rst)
   begin
     if (lock_rst = '1') then
         lock_cnt <= "000";
     elsif(totcmp'event and totcmp = '1') then
         lock_cnt <= lock_cnt + "001";
     end if;
   end process;

   lockcmp <= '1' when (lock_cnt = str2std(F_LOCK)) else '0';

   process(aclk, CDRRST_ipd)
   begin
     if (CDRRST_ipd = '1') then
          lockcmp_d1 <= '0';
          lockcmp_d2 <= '0';
     elsif (aclk'event and aclk = '1') then
          lockcmp_d1 <= lockcmp;
          lockcmp_d2 <= lockcmp_d1;
     end if;
   end process;

   lock_pulse <= lockcmp_d1 and not lockcmp_d2;

   process(CDRRST_ipd, lock_pulse)
   begin
     if (CDRRST_ipd = '1') then
         lock_int <= '0';
     elsif (lock_pulse = '1') then
         lock_int <= '1';
     end if;
   end process;

   process(sclk, CDRRST_ipd)
   begin
     if (CDRRST_ipd = '1') then
          lock0 <= '0';
          lock1 <= '1';
     elsif (sclk'event and sclk = '1') then
          lock0 <= lock_int;
          lock1 <= lock0;
     end if;
   end process;

   lock2 <= lock1 after 10 ps;

   process(RECCLK_sig, CDRRST_ipd)
   begin
     if (CDRRST_ipd = '1') then
          CDRLOCK <= '0';
     elsif (RECCLK_sig'event and RECCLK_sig = '1') then
          CDRLOCK <= lock2;
     end if;
   end process;

--######################################
--#SYNC detect & recover data and clock#
--######################################

   process(sclk)
   begin
     if (sclk'event and sclk = '1') then
         shift_buffer(15) <= data_ins;
         shift_buffer(14 downto 0) <= shift_buffer(15 downto 1);
     end if;
   end process;

   process(sclk, CDRRST_ipd)
   begin
     if (CDRRST_ipd = '1') then
         pre_align <= '0';
     elsif (sclk'event and sclk = '1') then
         --ct020805 if (shift_buffer(15 downto 4) = sympat_sig(19 downto 8)) then
         if (shift_buffer(15 downto 4) = sympat_sig(11 downto 0)) then
               pre_align <= '1';
         else  pre_align <= '0';
         end if;
     end if;
   end process;

   process(sclk, CDRRST_ipd)
   begin
     if (CDRRST_ipd = '1') then
         align <= '0';
         rsypt0 <= '0';
     elsif (sclk'event and sclk = '1') then
         align <= pre_align;
         rsypt0 <= pre_align;
     end if;
   end process;

   process(sclk, CDRRST_ipd)
   begin
     if (CDRRST_ipd = '1') then
         rsypt1 <= '0';
     elsif (sclk'event and sclk = '1') then
         rsypt1 <= rsypt0;
     end if;
   end process;

   rsypt2 <= rsypt1 after 10 ps;

   process(divcnt, divcnt_start)
   begin
      if(divcnt_start = '1') then
       if (divcnt = "010") then
            intrecclk1 <= '0';
       else
            intrecclk1 <= '1';
       end if;
      end if;
   end process;

   divcnt_start <= divcnt_start or align;
   process(sclk, align, divcnt)
   begin
     if (align'event and align = '1') then
         divcnt <= "111";
     elsif (sclk'event and sclk = '1' and divcnt_start = '1') then
         if (divcnt = "010") then
              divcnt <= "111";
         else
              divcnt <= divcnt - "001";
         end if;
     end if;
   end process;

   process(sclk)
   begin
     if (sclk'event and sclk = '1') then
          intrecclk2 <= intrecclk1;
     end if;
   end process;

   process(intrecclk2, align)
   begin
     if (align = '1') then
          intrecclk <= '0';
     elsif (intrecclk2'event and intrecclk2 = '1') then
          intrecclk <= not intrecclk;
     end if;
   end process;

   process(sclk)
   begin
     if (sclk'event and sclk = '1') then
          RECCLK_sig <= intrecclk;
     end if;
   end process;

   process(RECCLK_sig, CDRRST_ipd)
   begin
     if (CDRRST_ipd = '1') then
          SYDT <= '0';
     elsif (RECCLK_sig'event and RECCLK_sig = '1') then
          SYDT <= rsypt2;
     end if;
   end process;

   shift_buffer_d <= shift_buffer after 10 ps;

   process(RECCLK_sig)
   begin
     if (RECCLK_sig'event and RECCLK_sig = '1') then
          store_buffer <= shift_buffer_d;
     end if;
   end process;

   RXD0 <= store_buffer(2);
   RXD1 <= store_buffer(3);
   RXD2 <= store_buffer(4);
   RXD3 <= store_buffer(5);
   RXD4 <= store_buffer(6);
   RXD5 <= store_buffer(7);
   RXD6 <= store_buffer(8);
   RXD7 <= store_buffer(9);
   RXD8 <= store_buffer(10);
   RXD9 <= store_buffer(11);

end VITAL;

configuration CFG_CDRX_10B12B_VITAL of CDRX_10B12B is 
        for VITAL
        end for; 
end CFG_CDRX_10B12B_VITAL;

----- VITAL model for cell CDRX_8B10B -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;

library IEEE;
use IEEE.VITAL_Timing.all;
library LAVA1;
use LAVA1.components.all;

-- entity declaration --
entity CDRX_8B10B is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "10";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PLL_DLY  : string  := "0.0";
      SYMPAT   : string  := "11000001010011111010";

      F_LKDBW  : string  := "00011001";
      F_LKTBW  : string  := "01111111";
      F_TKDBW  : string  := "00011001";
      F_TKTBW  : string  := "01111111";
      F_LOCK   : string  := "011";

      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tipd_REFCLK    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SIN       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CDRRST    :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      SIN               : in    STD_ULOGIC;
      REFCLK            : in    STD_ULOGIC;
      CDRRST            : in    STD_ULOGIC;
      RXD0              : out   STD_ULOGIC;
      RXD1              : out   STD_ULOGIC;
      RXD2              : out   STD_ULOGIC;
      RXD3              : out   STD_ULOGIC;
      RXD4              : out   STD_ULOGIC;
      RXD5              : out   STD_ULOGIC;
      RXD6              : out   STD_ULOGIC;
      RXD7              : out   STD_ULOGIC;
      RXD8              : out   STD_ULOGIC;
      RXD9              : out   STD_ULOGIC;
      RECCLK            : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC;
      SYDT              : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CDRX_8B10B : entity is FALSE;
end CDRX_8B10B;


architecture VITAL of CDRX_8B10B is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL REFCLK_ipd	 : STD_ULOGIC := '0';
  SIGNAL SIN_ipd	 : STD_ULOGIC := '0';
  SIGNAL CDRRST_ipd	 : STD_ULOGIC := '0';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL clklock_half_period1 : TIME :=100 ns;
  SIGNAL clklock_half_period0 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly1 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly0 : TIME :=100 ns;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_falling_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;

  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;

  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  SIGNAL sympat_sig1  : std_logic_vector(19 downto 0) := str2std(sympat);
  SIGNAL sympat_sig  : std_logic_vector(19 downto 0); -- := str2std(sympat);

  CONSTANT clockboost: integer := str2int(mult) / str2int(div);
  CONSTANT tpd: time := 1.0 ns * str2real(pll_dly);

  SIGNAL  RECCLK_sig     : std_logic := '0';
  SIGNAL  CDRLOCK        : std_logic := '0';

  SIGNAL  intrecclk      : std_logic := '0';
  SIGNAL  inthsrecclk    : std_logic_vector(15 downto 0);
  SIGNAL  store_buffer   : std_logic_vector(15 downto 0);
  SIGNAL  shift_buffer, shift_buffer_d   : std_logic_vector(15 downto 0) := (others => '0');
  SIGNAL  aclk, sclk     : std_logic := '0';
  SIGNAL  sclksel        : std_logic_vector(15 downto 0);
  SIGNAL  data_ins, data_ina, data_inaa  : std_logic := '0';
  SIGNAL  time_data, time_clock, time_delta  : time ;
  SIGNAL  transition     : std_logic := '0';
  SIGNAL  dn_ss, dn_s, up_s, dn_clk, up_clk  : std_logic := '0';
  SIGNAL  cntrst, pcntrst   : std_logic := '0';
  SIGNAL  dn_cnt0, up_cnt0, dn_cnt, up_cnt  : std_logic_vector(7 downto 0) := (others => '0');
  SIGNAL  sub_cnt    : std_logic_vector(8 downto 0) := (others => '0');  
  SIGNAL  add_cnt, diff_cnt    : std_logic_vector(7 downto 0) := (others => '0');
  SIGNAL  lkdbw      : std_logic_vector(7 downto 0) := str2std(F_LKDBW);
  SIGNAL  lktbw      : std_logic_vector(7 downto 0) := str2std(F_LKTBW);
  SIGNAL  tkdbw      : std_logic_vector(7 downto 0) := str2std(F_TKDBW);
  SIGNAL  tktbw      : std_logic_vector(7 downto 0) := str2std(F_TKTBW);
  SIGNAL  dbw, tbw   : std_logic_vector(7 downto 0) := (others => '0');
  SIGNAL  diffcmp, totce, totcmp, totcmp_d    : std_logic := '0';
  SIGNAL  pre_pull, pre_push, pull, push      : std_logic := '0';
  SIGNAL  lock_rst   : std_logic := '0';
  SIGNAL  lock_cnt   : std_logic_vector(2 downto 0) := "000";
  SIGNAL  lockcmp, lockcmp_d1, lockcmp_d2  : std_logic := '0';
  SIGNAL  lock_int, lock0, lock1, lock2   : std_logic  := '0';
  SIGNAL  lock_pulse  : std_logic := '0';
  SIGNAL  align, pre_align1, pre_align2  : std_logic  := '0';
  SIGNAL  rsypt0, rsypt1, rsypt2   : std_logic := '0';
  SIGNAL  divcnt          : std_logic_vector(2 downto 0) := "000";
  SIGNAL  intrecclk1, intrecclk2      : std_logic := '0';
  SIGNAL  divcnt_start      : std_logic := '0';

BEGIN
   sympat_sig(0) <= sympat_sig1(19);
   sympat_sig(1) <= sympat_sig1(18);
   sympat_sig(2) <= sympat_sig1(17);
   sympat_sig(3) <= sympat_sig1(16);
   sympat_sig(4) <= sympat_sig1(15);
   sympat_sig(5) <= sympat_sig1(14);
   sympat_sig(6) <= sympat_sig1(13);
   sympat_sig(7) <= sympat_sig1(12);
   sympat_sig(8) <= sympat_sig1(11);
   sympat_sig(9) <= sympat_sig1(10);
   sympat_sig(10) <= sympat_sig1(9);
   sympat_sig(11) <= sympat_sig1(8);
   sympat_sig(12) <= sympat_sig1(7);
   sympat_sig(13) <= sympat_sig1(6);
   sympat_sig(14) <= sympat_sig1(5);
   sympat_sig(15) <= sympat_sig1(4);
   sympat_sig(16) <= sympat_sig1(3);
   sympat_sig(17) <= sympat_sig1(2);
   sympat_sig(18) <= sympat_sig1(1);
   sympat_sig(19) <= sympat_sig1(0);

   WireDelay : block
   begin
   VitalWireDelay (REFCLK_ipd, REFCLK, tipd_REFCLK);
   VitalWireDelay (CDRRST_ipd, CDRRST, tipd_CDRRST);
   VitalWireDelay (SIN_ipd, SIN, tipd_SIN);
   end block;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

       clklock_half_period <= (clklock_half_period0 + clklock_half_period1)/2;

  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     IF clklock_rising_edge_count = 0 THEN
        clklock_last_rising_edge <= NOW;	
	start_inclk <= REFCLK_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
       clklock_half_period0 <= (NOW - clklock_last_falling_edge)* str2int(div)/str2int(mult);
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     elsif clklock_rising_edge_count = 2 THEN
       clklock_half_period_minus_dly0 <= (NOW - clklock_last_falling_edge) + tpd;
       --clklock_half_period <= (clklock_half_period0 + clklock_half_period1)/2;
     END IF;
     END IF;
 
  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='0');
     clklock_falling_edge_count <= clklock_falling_edge_count +1;	  	
     IF clklock_falling_edge_count = 0 THEN	
	clklock_last_falling_edge <= NOW;
	clklock_half_period1 <= (NOW - clklock_last_rising_edge)* str2int(div)/str2int(mult); 
     ELSIF clklock_falling_edge_count = 1 THEN
        clklock_half_period_minus_dly1 <= (NOW - clklock_last_rising_edge) + tpd;
     END IF;
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc + 1 THEN
         if(clockboost >1) then
	   FOR i IN 1 TO (2*clockboost) LOOP 	       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

process
begin
    wait until CLK_OUT_sig_d_start = '1'; LOOP
     wait for clklock_half_period1;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not;
     wait for clklock_half_period0;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not ;
   END LOOP;
end process;

process
begin
   wait until (clklock_falling_edge_count >= lock_cyc + 1);
    wait for clklock_half_period_minus_dly0;
   CLK_OUT_start <= '1';
end process;

process
begin
   wait until  CLK_OUT_start = '1'; LOOP
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d;
     wait for clklock_half_period1;
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d ;
     wait for clklock_half_period0;
     END LOOP;
end process;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ;

    CSLOCK  <= CSLOCK_sig;
    RECCLK <= RECCLK_sig;

--#################
--#16-phase clocks#
--#################

    inthsrecclk(0) <= CLK_OUT_plus_delay;
    inthsrecclk(1) <= inthsrecclk(0) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(2) <= inthsrecclk(1) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(3) <= inthsrecclk(2) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(4) <= inthsrecclk(3) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(5) <= inthsrecclk(4) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(6) <= inthsrecclk(5) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(7) <= inthsrecclk(6) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(8) <= inthsrecclk(7) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(9) <= inthsrecclk(8) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(10) <= inthsrecclk(9) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(11) <= inthsrecclk(10) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(12) <= inthsrecclk(11) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(13) <= inthsrecclk(12) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(14) <= inthsrecclk(13) after (clklock_half_period*2*str2int(div)/str2int(mult));
    inthsrecclk(15) <= inthsrecclk(14) after (clklock_half_period*2*str2int(div)/str2int(mult));

--#################
--#digitial filter#
--#################

  process(sclk, SIN_ipd)
  begin
     if (sclk'event and sclk = '1') then
         data_ins <= SIN_ipd;
     end if;
  end process;

  process
  begin
      WAIT UNTIL (SIN_ipd'EVENT); 
         time_data <= NOW;
  end process;

  process
  begin
      WAIT UNTIL (aclk'EVENT AND aclk='1');
         time_clock <= NOW;
  end process;

  process(time_data, time_clock)
  begin
     if(time_data >= time_clock) then
          time_delta <= time_data - time_clock;
     else
          time_delta <= time_clock - time_data;
     end if;
  end process;

  process(aclk, SIN_ipd)
  begin
     if (aclk'event and aclk = '1') then
         data_inaa <= SIN_ipd;
     end if;
  end process;

  process(aclk, time_delta, data_inaa)
  begin
     if(aclk = '1') then
        if (time_delta < 100 ps) then
            data_ina <= 'X';
        else
            data_ina <= data_inaa;
        end if;
     end if;
  end process;
         
  transition <= data_ins XOR data_ina;

  process(sclk, transition)
  begin
    if (sclk = '1') then
        dn_ss <= transition;
    end if;
  end process;

  process(sclk)
  begin
    if (sclk'event and sclk = '1') then
        dn_s <= dn_ss;
    end if;
  end process;

  process(sclk)
  begin
    if (sclk'event and sclk = '1') then
        up_s <= transition;
    end if;
  end process;

  dn_clk <= dn_s and aclk;
  up_clk <= up_s and aclk;

  process(dn_clk, cntrst)
  begin
      if (cntrst = '1') then
          dn_cnt0 <= "00000000";
      elsif((dn_clk'event and dn_clk = '1') or (dn_clk'event and dn_clk = 'X')) then
          dn_cnt0 <= dn_cnt0 + "00000001";
      end if;
  end process;

  process(up_clk, cntrst)
  begin
      if (cntrst = '1') then
          up_cnt0 <= "00000000";
      elsif((up_clk'event and up_clk = '1') or (up_clk'event and up_clk = 'X')) then
          up_cnt0 <= dn_cnt0 + "00000001";
      end if;
  end process;

  process(aclk)
  begin
    if(aclk'event and aclk = '1') then
        dn_cnt <= dn_cnt0;
        up_cnt <= up_cnt0;
    end if;
  end process;

  process(aclk, cntrst)
  begin
    if(cntrst = '1') then
        sub_cnt <= "000000000";
        add_cnt <= "00000000";
    elsif(aclk'event and aclk = '1') then
        add_cnt <= dn_cnt + up_cnt;
    end if;
  end process;

  dbw <= tkdbw when (CDRLOCK = '1') else lkdbw;
  tbw <= tktbw when (CDRLOCK = '1') else lktbw;

  diff_cnt <= not (sub_cnt(7 downto 0)) when (sub_cnt(8) = '1') else sub_cnt(7 downto 0);

  process(aclk, cntrst)
  begin
    if(cntrst = '1') then
        diffcmp <= '0';
    elsif(aclk'event and aclk = '1') then
       if(diff_cnt >= dbw) then
          diffcmp <= '1';
       else
          diffcmp <= '0';
       end if;
    end if;
  end process;

  totce <= '1' when (add_cnt(7 downto 1) = tbw(7 downto 1)) else '0';

  process(aclk, CDRRST_ipd)
  begin
    if(CDRRST_ipd = '1') then
       totcmp <= '0';
    elsif(aclk'event and aclk = '1') then
       totcmp <= totce;
    end if;
  end process;

  process(aclk, CDRRST_ipd)
  begin
    if(CDRRST_ipd = '1') then
       totcmp_d <= '0';
    elsif(aclk'event and aclk = '1') then
       totcmp_d <= totcmp;
    end if;
  end process;

  cntrst <= CDRRST_ipd or totcmp;
  pcntrst <= CDRRST_ipd or totcmp_d;

  process(aclk, pcntrst) 
  begin
    if(pcntrst = '1') then
       pre_push <= '0';
       pre_pull <= '0';
    elsif(aclk'event and aclk = '1') then
       if(totce = '1') then
           pre_push <= diffcmp and not sub_cnt(8);
           pre_pull <= diffcmp and sub_cnt(8);
       end if;
    end if;
  end process;

  process(aclk, CDRRST_ipd)
  begin
    if(CDRRST_ipd = '1') then
        push <= '0';
        pull <= '0';
    elsif(aclk'event and aclk = '1') then
        push <= pre_push;
        pull <= pre_pull;
    end if;
  end process;

--########################
--#phase shift and select#
--########################

  process(aclk, CDRRST_ipd)
  begin
    if(CDRRST_ipd = '1') then
        sclksel <= X"0100";
    elsif(aclk'event and aclk = '1') then
        if(pull = '1') then
            sclksel <= sclksel(0) & sclksel(15 downto 1);
        elsif(push = '1') then
            sclksel <= sclksel(14 downto 0) & sclksel(15);
        end if;
    end if;
  end process;

  process(sclksel, inthsrecclk)
  begin
     case sclksel is
        when X"0001"  =>  
                   aclk <= inthsrecclk(8);
                   sclk <= inthsrecclk(0);
        when X"0002"  => 
                   aclk <= inthsrecclk(9);
                   sclk <= inthsrecclk(1);
        when X"0004"  => 
                   aclk <= inthsrecclk(10);
                   sclk <= inthsrecclk(2);
        when X"0008"  => 
                   aclk <= inthsrecclk(11);
                   sclk <= inthsrecclk(3);
        when X"0010"  => 
                   aclk <= inthsrecclk(12);
                   sclk <= inthsrecclk(4);
        when X"0020"  => 
                   aclk <= inthsrecclk(13);
                   sclk <= inthsrecclk(5);
        when X"0040"  => 
                   aclk <= inthsrecclk(14);
                   sclk <= inthsrecclk(6);
        when X"0080"  => 
                   aclk <= inthsrecclk(15);
                   sclk <= inthsrecclk(7);
        when X"0100"  => 
                   aclk <= inthsrecclk(0);
                   sclk <= inthsrecclk(8);
        when X"0200"  => 
                   aclk <= inthsrecclk(1);
                   sclk <= inthsrecclk(9);
        when X"0400"  => 
                   aclk <= inthsrecclk(2);
                   sclk <= inthsrecclk(10);
        when X"0800"  => 
                   aclk <= inthsrecclk(3);
                   sclk <= inthsrecclk(11);
        when X"1000"  => 
                   aclk <= inthsrecclk(4);
                   sclk <= inthsrecclk(12);
        when X"2000"  => 
                   aclk <= inthsrecclk(5);
                   sclk <= inthsrecclk(13);
        when X"4000"  => 
                   aclk <= inthsrecclk(6);
                   sclk <= inthsrecclk(14);
        when X"8000"  => 
                   aclk <= inthsrecclk(7);
                   sclk <= inthsrecclk(15);
        when others   => 
                   aclk <= inthsrecclk(0);
                   sclk <= inthsrecclk(8);
     end case;
   end process;

--#############
--#LOCK detect#
--#############

   lock_rst <= CDRRST_ipd or pull or push;

   process(totcmp, lock_rst)
   begin
     if (lock_rst = '1') then
         lock_cnt <= "000";
     elsif(totcmp'event and totcmp = '1') then
         lock_cnt <= lock_cnt + "001";
     end if;
   end process;

   lockcmp <= '1' when (lock_cnt = str2std(F_LOCK)) else '0';

   process(aclk, CDRRST_ipd)
   begin
     if (CDRRST_ipd = '1') then
          lockcmp_d1 <= '0';
          lockcmp_d2 <= '0';
     elsif (aclk'event and aclk = '1') then
          lockcmp_d1 <= lockcmp;
          lockcmp_d2 <= lockcmp_d1;
     end if;
   end process;

   lock_pulse <= lockcmp_d1 and not lockcmp_d2;

   process(CDRRST_ipd, lock_pulse)
   begin
     if (CDRRST_ipd = '1') then
         lock_int <= '0';
     elsif (lock_pulse = '1') then
         lock_int <= '1';
     end if;
   end process;

   process(sclk, CDRRST_ipd)
   begin
     if (CDRRST_ipd = '1') then
          lock0 <= '0';
          lock1 <= '1';
     elsif (sclk'event and sclk = '1') then
          lock0 <= lock_int;
          lock1 <= lock0;
     end if;
   end process;

   lock2 <= lock1 after 10 ps;

   process(RECCLK_sig, CDRRST_ipd)
   begin
     if (CDRRST_ipd = '1') then
          CDRLOCK <= '0';
     elsif (RECCLK_sig'event and RECCLK_sig = '1') then
          CDRLOCK <= lock2;
     end if;
   end process;

--######################################
--#SYNC detect & recover data and clock#
--######################################

   process(sclk)
   begin
     if (sclk'event and sclk = '1') then
         shift_buffer(15) <= data_ins;
         shift_buffer(14 downto 0) <= shift_buffer(15 downto 1);
     end if;
   end process;

   process(sclk, CDRRST_ipd)
   begin
     if (CDRRST_ipd = '1') then
         pre_align1 <= '0';
         pre_align2 <= '0';
     elsif (sclk'event and sclk = '1') then
         if (shift_buffer(15 downto 6) = sympat_sig(9 downto 0)) then
               pre_align1 <= '1';
         else  pre_align1 <= '0';
         end if;

         if (shift_buffer(15 downto 6) = sympat_sig(19 downto 10)) then
               pre_align2 <= '1' ;
         else  pre_align2 <= '0';
         end if;
     end if;
   end process;

   process(sclk, CDRRST_ipd)
   begin
     if (CDRRST_ipd = '1') then
         align <= '0';
         rsypt0 <= '0';
     elsif (sclk'event and sclk = '1') then
         align <= pre_align1 or pre_align2;
         rsypt0 <= pre_align1 or pre_align2;
     end if;
   end process;

   process(sclk, CDRRST_ipd)
   begin
     if (CDRRST_ipd = '1') then
         rsypt1 <= '0';
     elsif (sclk'event and sclk = '1') then
         rsypt1 <= rsypt0;
     end if;
   end process;

   rsypt2 <= rsypt1 after 10 ps;

   process(divcnt, divcnt_start)
   begin
      if(divcnt_start = '1') then
       if (divcnt = "011") then
            intrecclk1 <= '0';
       else
            intrecclk1 <= '1';
       end if;
      end if;
   end process;

   divcnt_start <= divcnt_start or align;
   process(sclk, align, divcnt)
   begin
     if (align'event and align = '1') then
         divcnt <= "111";
     elsif (sclk'event and sclk = '1' and divcnt_start = '1') then
         if (divcnt = "011") then
              divcnt <= "111";
         else
              divcnt <= divcnt - "001";
         end if;
     end if;
   end process;

   process(sclk)
   begin
     if (sclk'event and sclk = '1') then
          intrecclk2 <= intrecclk1;
     end if;
   end process;

   process(intrecclk2, align)
   begin
     if (align = '1') then
          intrecclk <= '0';
     elsif (intrecclk2'event and intrecclk2 = '1') then
          intrecclk <= not intrecclk;
     end if;
   end process;

   process(sclk)
   begin
     if (sclk'event and sclk = '1') then
          RECCLK_sig <= intrecclk;
     end if;
   end process;

   process(RECCLK_sig, CDRRST_ipd)
   begin
     if (CDRRST_ipd = '1') then
          SYDT <= '0';
     elsif (RECCLK_sig'event and RECCLK_sig = '1') then
          SYDT <= rsypt2;
     end if;
   end process;

   shift_buffer_d <= shift_buffer after 10 ps;

   process(RECCLK_sig)
   begin
     if (RECCLK_sig'event and RECCLK_sig = '1') then
          store_buffer <= shift_buffer_d;
     end if;
   end process;

   RXD0 <= store_buffer(3);
   RXD1 <= store_buffer(4);
   RXD2 <= store_buffer(5);
   RXD3 <= store_buffer(6);
   RXD4 <= store_buffer(7);
   RXD5 <= store_buffer(8);
   RXD6 <= store_buffer(9);
   RXD7 <= store_buffer(10);
   RXD8 <= store_buffer(11);
   RXD9 <= store_buffer(12);

end VITAL;

configuration CFG_CDRX_8B10B_VITAL of CDRX_8B10B is 
        for VITAL
        end for; 
end CFG_CDRX_8B10B_VITAL;

----- VITAL model for cell CDRX_SS_4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library lava1;
use lava1.components.all;

-- entity declaration --
entity CDRX_SS_4 is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "4";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PLL_DLY  : string  := "0.0";
      SYMPAT   : string  := "110011001100";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tipd_CAL       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SIN       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SS_CLKIN   :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      SIN               : in    STD_ULOGIC;
      CAL               : in    STD_ULOGIC;
      SS_CLKIN          : in    STD_ULOGIC;
      RXD0              : out   STD_ULOGIC;
      RXD1              : out   STD_ULOGIC;
      RXD2              : out   STD_ULOGIC;
      RXD3              : out   STD_ULOGIC;
      RECCLK            : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC;
      SYDT              : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CDRX_SS_4 : entity is FALSE;
end CDRX_SS_4;

architecture VITAL of CDRX_SS_4 is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL SS_CLKIN_ipd	 : STD_ULOGIC := 'X';
  SIGNAL SIN_ipd	 : STD_ULOGIC := 'X';
  SIGNAL CAL_ipd         : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;
  SIGNAL clk_in_period : TIME ;
  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_2d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_2d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  SIGNAL inthsrecclk    : std_logic := '0';
  SIGNAL intrecclk      : std_logic := '0';
  SIGNAL intrecclk_d    : std_logic := '0';
  SIGNAL intrecclk_d1   : std_logic := '0';
  SIGNAL intrecclk_d2   : std_logic := '0';

  SIGNAL sync_valid        : std_logic := '0';
  SIGNAL sync_valid_store  : std_logic := '0';
  SIGNAL sync_found        : std_logic := '0';
  SIGNAL sync_detect       : std_logic := '0';
  SIGNAL sync_detect_d     : std_logic := '0';
  SIGNAL sync_detect_d1    : std_logic := '0';
  SIGNAL sync_detect_d2    : std_logic := '0';

  SIGNAL symstr_buffer    : std_logic_vector(11 downto 0) := (others=>'0');
  SIGNAL store_buffer     : std_logic_vector(3 downto 0) := (others=>'0');
  SIGNAL shift_buffer     : std_logic_vector(3 downto 0) := (others=>'0');

  SIGNAL sympat_sig  : std_logic_vector(11 downto 0) := str2std(sympat);

  CONSTANT clockboost: real := real(str2int(mult)) / real(str2int(div));
  CONSTANT tpd: time := 1.0 ns * str2real(pll_dly);

BEGIN

   WireDelay : block
   begin
   VitalWireDelay (SS_CLKIN_ipd, SS_CLKIN, tipd_SS_CLKIN);
   VitalWireDelay (CAL_ipd, CAL, tipd_CAL);
   VitalWireDelay (SIN_ipd, SIN, tipd_SIN);
   end block;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

  WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     clklock_last_rising_edge <= NOW;
     IF clklock_rising_edge_count = 0 THEN	
	start_inclk <= SS_CLKIN_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     END IF;
     END IF;
 
  --ct09010527466 WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='0');	 
  WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='1');	   	
     IF clklock_rising_edge_count = 1 THEN	
        clklock_half_period <= (NOW - clklock_last_rising_edge)/(clockboost*2.0);

	--ct09010527466clklock_half_period <= (NOW - clklock_last_rising_edge)/clockboost;  
	--ct09010527466clklock_last_falling_edge <= NOW;
     END IF;
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc THEN
        if(clockboost >1.0) then
	   FOR i IN 1 TO integer(2.0*clockboost) LOOP 	       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

    intrecclk <= SS_CLKIN;


    CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not after clklock_half_period when clock_count > 0 else
                     CLK_OUT_sig_d_not;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_sig_2d <= CLK_OUT_sig_d after clklock_half_period; 
    CLK_OUT_sig_3d <= CLK_OUT_sig_2d after clklock_half_period + tpd;

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    inthsrecclk <= CLK_OUT_plus_delay;

    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ;

    --ct102804 intrecclk  <= SS_CLKIN;
    RECCLK     <= intrecclk ;
    CSLOCK  <= CSLOCK_sig;

process(inthsrecclk,SS_CLKIN)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d <= SS_CLKIN;
    end if;
end process;

process(inthsrecclk,intrecclk_d1)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d1 <= intrecclk_d;
    end if;
end process;

process(inthsrecclk,intrecclk_d1)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d2 <= intrecclk_d1;
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
       shift_buffer(3)  <= SIN_ipd;
       shift_buffer(2)  <= shift_buffer(3);
       shift_buffer(1)  <= shift_buffer(2);
       shift_buffer(0)  <= shift_buffer(1);

       symstr_buffer(11) <= SIN_ipd;
       symstr_buffer(10) <= symstr_buffer(11);
       symstr_buffer(9)  <= symstr_buffer(10);
       symstr_buffer(8)  <= symstr_buffer(9);
       symstr_buffer(7)  <= symstr_buffer(8);
       symstr_buffer(6)  <= symstr_buffer(7);
       symstr_buffer(5)  <= symstr_buffer(6);
       symstr_buffer(4)  <= symstr_buffer(5);
       symstr_buffer(3)  <= symstr_buffer(4);
       symstr_buffer(2)  <= symstr_buffer(3);
       symstr_buffer(1)  <= symstr_buffer(2);
       symstr_buffer(0)  <= symstr_buffer(1);
    end if;
end process;

process(inthsrecclk, symstr_buffer)
begin
    if(symstr_buffer(11 downto 0) = sympat_sig(11 downto 0)) then
         sync_found <= '1';
    else
         sync_found <= '0';
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_valid <= sync_found or sync_valid;
    end if;
end process;

sync_valid_store <= sync_valid and not sync_detect_d;

process(intrecclk)
begin
    if(intrecclk'event and intrecclk='1') then
         sync_detect <= sync_valid_store and not sync_detect;
    end if;
end process;

process(intrecclk_d1,shift_buffer)
begin
    if(intrecclk_d1'event and intrecclk_d1='1') then
         store_buffer <= shift_buffer; 
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_detect_d <= sync_detect_d2; 
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_detect_d2 <= sync_detect_d1; 
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_detect_d1 <= sync_detect or sync_detect_d1; 
    end if;
end process;

RXD0 <= store_buffer(0) and sync_detect_d;
RXD1 <= store_buffer(1) and sync_detect_d;
RXD2 <= store_buffer(2) and sync_detect_d;
RXD3 <= store_buffer(3) and sync_detect_d;

SYDT <= sync_valid_store;
end VITAL;

configuration CFG_CDRX_SS_4_VITAL of CDRX_SS_4 is 
        for VITAL
        end for; 
end CFG_CDRX_SS_4_VITAL;
----- VITAL model for cell CDRX_SS_6 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library lava1;
use lava1.components.all;

-- entity declaration --
entity CDRX_SS_6 is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "6";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PLL_DLY  : string  := "0.0";
      SYMPAT   : string  := "111000111000";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tipd_CAL       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SIN       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SS_CLKIN   :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      SIN               : in    STD_ULOGIC;
      CAL               : in    STD_ULOGIC;
      SS_CLKIN          : in    STD_ULOGIC;
      RXD0              : out   STD_ULOGIC;
      RXD1              : out   STD_ULOGIC;
      RXD2              : out   STD_ULOGIC;
      RXD3              : out   STD_ULOGIC;
      RXD4              : out   STD_ULOGIC;
      RXD5              : out   STD_ULOGIC;
      RECCLK            : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC;
      SYDT              : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CDRX_SS_6 : entity is FALSE;
end CDRX_SS_6;


architecture VITAL of CDRX_SS_6 is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL SS_CLKIN_ipd	 : STD_ULOGIC := 'X';
  SIGNAL SIN_ipd	 : STD_ULOGIC := 'X';
  SIGNAL CAL_ipd         : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;
  SIGNAL clk_in_period : TIME ;
  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_2d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_2d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  SIGNAL inthsrecclk    : std_logic := '0';
  SIGNAL intrecclk      : std_logic := '0';
  SIGNAL intrecclk_d    : std_logic := '0';
  SIGNAL intrecclk_d1   : std_logic := '0';
  SIGNAL intrecclk_d2   : std_logic := '0';

  SIGNAL sync_valid        : std_logic := '0';
  SIGNAL sync_valid_store  : std_logic := '0';
  SIGNAL sync_found        : std_logic := '0';
  SIGNAL sync_detect       : std_logic := '0';
  SIGNAL sync_detect_d     : std_logic := '0';
  SIGNAL sync_detect_d1    : std_logic := '0';
  SIGNAL sync_detect_d2    : std_logic := '0';

  SIGNAL symstr_buffer    : std_logic_vector(11 downto 0) := (others=>'0');
  SIGNAL store_buffer     : std_logic_vector(5 downto 0) := (others=>'0');
  SIGNAL shift_buffer     : std_logic_vector(5 downto 0) := (others=>'0');

  SIGNAL sympat_sig  : std_logic_vector(11 downto 0) := str2std(sympat);

  CONSTANT clockboost: real := real(str2int(mult)) / real(str2int(div));
  CONSTANT tpd: time := 1.0 ns * str2real(pll_dly);

BEGIN

   WireDelay : block
   begin
   VitalWireDelay (SS_CLKIN_ipd, SS_CLKIN, tipd_SS_CLKIN);
   VitalWireDelay (CAL_ipd, CAL, tipd_CAL);
   VitalWireDelay (SIN_ipd, SIN, tipd_SIN);
   end block;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

  WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     clklock_last_rising_edge <= NOW;
     IF clklock_rising_edge_count = 0 THEN	
	start_inclk <= SS_CLKIN_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     END IF;
     END IF;
 
  --ct09010527466 WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='0');	 
  WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='1');	   	
     IF clklock_rising_edge_count = 1 THEN	
        clklock_half_period <= (NOW - clklock_last_rising_edge)/(clockboost*2.0);

	--ct09010527466clklock_half_period <= (NOW - clklock_last_rising_edge)/clockboost;  
	--ct09010527466clklock_last_falling_edge <= NOW;
     END IF;

END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc THEN
        if(clockboost >1.0) then
	   FOR i IN 1 TO integer(2.0*clockboost) LOOP 	       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

    intrecclk <= SS_CLKIN_ipd;


    CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not after clklock_half_period when clock_count > 0 else
                     CLK_OUT_sig_d_not;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_sig_2d <= CLK_OUT_sig_d after clklock_half_period; 
    CLK_OUT_sig_3d <= CLK_OUT_sig_2d after clklock_half_period + tpd;

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    inthsrecclk <= CLK_OUT_plus_delay;

    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ;

    --ct102804 intrecclk  <= SS_CLKIN;
    RECCLK     <= intrecclk ;
    CSLOCK  <= CSLOCK_sig;

process(inthsrecclk,SS_CLKIN)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d <= SS_CLKIN;
    end if;
end process;

process(inthsrecclk,intrecclk_d1)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d1 <= intrecclk_d;
    end if;
end process;

process(inthsrecclk,intrecclk_d1)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d2 <= intrecclk_d1;
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
       shift_buffer(5)  <= SIN_ipd;
       shift_buffer(4)  <= shift_buffer(5);
       shift_buffer(3)  <= shift_buffer(4);
       shift_buffer(2)  <= shift_buffer(3);
       shift_buffer(1)  <= shift_buffer(2);
       shift_buffer(0)  <= shift_buffer(1);

       symstr_buffer(11) <= SIN_ipd;
       symstr_buffer(10) <= symstr_buffer(11);
       symstr_buffer(9)  <= symstr_buffer(10);
       symstr_buffer(8)  <= symstr_buffer(9);
       symstr_buffer(7)  <= symstr_buffer(8);
       symstr_buffer(6)  <= symstr_buffer(7);
       symstr_buffer(5)  <= symstr_buffer(6);
       symstr_buffer(4)  <= symstr_buffer(5);
       symstr_buffer(3)  <= symstr_buffer(4);
       symstr_buffer(2)  <= symstr_buffer(3);
       symstr_buffer(1)  <= symstr_buffer(2);
       symstr_buffer(0)  <= symstr_buffer(1);
    end if;
end process;

process(inthsrecclk, symstr_buffer)
begin
    if(symstr_buffer(11 downto 0) = sympat_sig(11 downto 0)) then
         sync_found <= '1';
    else
         sync_found <= '0';
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_valid <= sync_found or sync_valid;
    end if;
end process;

sync_valid_store <= sync_valid and not sync_detect_d;

process(intrecclk)
begin
    if(intrecclk'event and intrecclk='1') then
         sync_detect <= sync_valid_store and not sync_detect;
    end if;
end process;

process(intrecclk_d1)
begin
    if(intrecclk_d1'event and intrecclk_d1='1') then
         store_buffer <= shift_buffer; 
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_detect_d <= sync_detect_d2; 
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_detect_d2 <= sync_detect_d1; 
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_detect_d1 <= sync_detect or sync_detect_d1; 
    end if;
end process;

RXD0 <= store_buffer(0) and sync_detect_d;
RXD1 <= store_buffer(1) and sync_detect_d;
RXD2 <= store_buffer(2) and sync_detect_d;
RXD3 <= store_buffer(3) and sync_detect_d;
RXD4 <= store_buffer(4) and sync_detect_d;
RXD5 <= store_buffer(5) and sync_detect_d;

SYDT <= sync_valid_store;
end VITAL;

configuration CFG_CDRX_SS_6_VITAL of CDRX_SS_6 is 
        for VITAL
        end for; 
end CFG_CDRX_SS_6_VITAL;
----- VITAL model for cell CDRX_SS_8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library lava1;
use lava1.components.all;

-- entity declaration --
entity CDRX_SS_8 is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "8";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PLL_DLY  : string  := "0.0";
      SYMPAT   : string  := "000011110000";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tipd_CAL       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SIN       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SS_CLKIN   :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      SIN               : in    STD_ULOGIC;
      CAL               : in    STD_ULOGIC;
      SS_CLKIN          : in    STD_ULOGIC;
      RXD0              : out   STD_ULOGIC;
      RXD1              : out   STD_ULOGIC;
      RXD2              : out   STD_ULOGIC;
      RXD3              : out   STD_ULOGIC;
      RXD4              : out   STD_ULOGIC;
      RXD5              : out   STD_ULOGIC;
      RXD6              : out   STD_ULOGIC;
      RXD7              : out   STD_ULOGIC;
      RECCLK            : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC;
      SYDT              : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CDRX_SS_8 : entity is FALSE;
end CDRX_SS_8;


architecture VITAL of CDRX_SS_8 is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL SS_CLKIN_ipd	 : STD_ULOGIC := 'X';
  SIGNAL SIN_ipd	 : STD_ULOGIC := 'X';
  SIGNAL CAL_ipd         : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;
  SIGNAL clk_in_period : TIME ;
  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_2d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_2d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  SIGNAL inthsrecclk    : std_logic := '0';
  SIGNAL intrecclk      : std_logic := '0';
  SIGNAL intrecclk_d    : std_logic := '0';
  SIGNAL intrecclk_d1   : std_logic := '0';
  SIGNAL intrecclk_d2   : std_logic := '0';

  SIGNAL sync_valid        : std_logic := '0';
  SIGNAL sync_valid_store  : std_logic := '0';
  SIGNAL sync_found        : std_logic := '0';
  SIGNAL sync_detect       : std_logic := '0';
  SIGNAL sync_detect_d     : std_logic := '0';
  SIGNAL sync_detect_d1    : std_logic := '0';
  SIGNAL sync_detect_d2    : std_logic := '0';

  SIGNAL symstr_buffer    : std_logic_vector(11 downto 0) := (others=>'0');
  SIGNAL store_buffer     : std_logic_vector(7 downto 0) := (others=>'0');
  SIGNAL shift_buffer     : std_logic_vector(7 downto 0) := (others=>'0');

  SIGNAL sympat_sig  : std_logic_vector(11 downto 0) := str2std(sympat);

  CONSTANT clockboost: real := real(str2int(mult)) / real(str2int(div));
  CONSTANT tpd: time := 1.0 ns * str2real(pll_dly);

BEGIN

   WireDelay : block
   begin
   VitalWireDelay (SS_CLKIN_ipd, SS_CLKIN, tipd_SS_CLKIN);
   VitalWireDelay (CAL_ipd, CAL, tipd_CAL);
   VitalWireDelay (SIN_ipd, SIN, tipd_SIN);
   end block;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

  WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     clklock_last_rising_edge <= NOW;
     IF clklock_rising_edge_count = 0 THEN	
	start_inclk <= SS_CLKIN_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     END IF;
     END IF;

  --ct09010527466 WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='0');	 
  WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='1');	   	
     IF clklock_rising_edge_count = 1 THEN	
        clklock_half_period <= (NOW - clklock_last_rising_edge)/(clockboost*2.0);

	--ct09010527466clklock_half_period <= (NOW - clklock_last_rising_edge)/clockboost;  
	--ct09010527466clklock_last_falling_edge <= NOW;
     END IF;

END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc THEN
        if(clockboost >1.0) then
	   FOR i IN 1 TO integer(2.0*clockboost) LOOP 	       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

    intrecclk <= SS_CLKIN_ipd;


    CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not after clklock_half_period when clock_count > 0 else
                     CLK_OUT_sig_d_not;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_sig_2d <= CLK_OUT_sig_d after clklock_half_period; 
    CLK_OUT_sig_3d <= CLK_OUT_sig_2d after clklock_half_period + tpd;

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    inthsrecclk <= CLK_OUT_plus_delay;

    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ;

    --ct102804 intrecclk  <= SS_CLKIN;
    RECCLK     <= intrecclk ;
    CSLOCK  <= CSLOCK_sig;

process(inthsrecclk,SS_CLKIN)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d <= SS_CLKIN;
    end if;
end process;

process(inthsrecclk,intrecclk_d1)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d1 <= intrecclk_d;
    end if;
end process;

process(inthsrecclk,intrecclk_d1)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d2 <= intrecclk_d1;
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
       shift_buffer(7)  <= SIN_ipd;
       shift_buffer(6)  <= shift_buffer(7);
       shift_buffer(5)  <= shift_buffer(6);
       shift_buffer(4)  <= shift_buffer(5);
       shift_buffer(3)  <= shift_buffer(4);
       shift_buffer(2)  <= shift_buffer(3);
       shift_buffer(1)  <= shift_buffer(2);
       shift_buffer(0)  <= shift_buffer(1);

       symstr_buffer(11) <= SIN_ipd;
       symstr_buffer(10) <= symstr_buffer(11);
       symstr_buffer(9)  <= symstr_buffer(10);
       symstr_buffer(8)  <= symstr_buffer(9);
       symstr_buffer(7)  <= symstr_buffer(8);
       symstr_buffer(6)  <= symstr_buffer(7);
       symstr_buffer(5)  <= symstr_buffer(6);
       symstr_buffer(4)  <= symstr_buffer(5);
       symstr_buffer(3)  <= symstr_buffer(4);
       symstr_buffer(2)  <= symstr_buffer(3);
       symstr_buffer(1)  <= symstr_buffer(2);
       symstr_buffer(0)  <= symstr_buffer(1);
    end if;
end process;

process(inthsrecclk, symstr_buffer)
begin
    if(symstr_buffer(11 downto 0) = sympat_sig(11 downto 0)) then
         sync_found <= '1';
    else
         sync_found <= '0';
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_valid <= sync_found or sync_valid;
    end if;
end process;

sync_valid_store <= sync_valid and not sync_detect_d;

process(intrecclk)
begin
    if(intrecclk'event and intrecclk='1') then
         sync_detect <= sync_valid_store and not sync_detect;
    end if;
end process;

process(intrecclk_d1)
begin
    if(intrecclk_d1'event and intrecclk_d1='1') then
         store_buffer <= shift_buffer; 
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_detect_d <= sync_detect_d2; 
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_detect_d2 <= sync_detect_d1; 
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_detect_d1 <= sync_detect or sync_detect_d1; 
    end if;
end process;

RXD0 <= store_buffer(0) and sync_detect_d;
RXD1 <= store_buffer(1) and sync_detect_d;
RXD2 <= store_buffer(2) and sync_detect_d;
RXD3 <= store_buffer(3) and sync_detect_d;
RXD4 <= store_buffer(4) and sync_detect_d;
RXD5 <= store_buffer(5) and sync_detect_d;
RXD6 <= store_buffer(6) and sync_detect_d;
RXD7 <= store_buffer(7) and sync_detect_d;

SYDT <= sync_valid_store;
end VITAL;

configuration CFG_CDRX_SS_8_VITAL of CDRX_SS_8 is 
        for VITAL
        end for; 
end CFG_CDRX_SS_8_VITAL;

----- VITAL model for cell CDRX_SS_10 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library lava1;
use lava1.components.all;

-- entity declaration --
entity CDRX_SS_10 is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "10";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PLL_DLY  : string  := "0.0";
      SYMPAT   : string  := "001111100000";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tipd_CAL       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SIN       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SS_CLKIN   :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      SIN               : in    STD_ULOGIC;
      CAL               : in    STD_ULOGIC;
      SS_CLKIN          : in    STD_ULOGIC;
      RXD0              : out   STD_ULOGIC;
      RXD1              : out   STD_ULOGIC;
      RXD2              : out   STD_ULOGIC;
      RXD3              : out   STD_ULOGIC;
      RXD4              : out   STD_ULOGIC;
      RXD5              : out   STD_ULOGIC;
      RXD6              : out   STD_ULOGIC;
      RXD7              : out   STD_ULOGIC;
      RXD8              : out   STD_ULOGIC;
      RXD9              : out   STD_ULOGIC;
      RECCLK            : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC;
      SYDT              : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of CDRX_SS_10 : entity is FALSE;
end CDRX_SS_10;


architecture VITAL of CDRX_SS_10 is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL SS_CLKIN_ipd	 : STD_ULOGIC := 'X';
  SIGNAL SIN_ipd	 : STD_ULOGIC := 'X';
  SIGNAL CAL_ipd         : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;
  SIGNAL clk_in_period : TIME ;
  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_2d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_2d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  SIGNAL inthsrecclk    : std_logic := '0';
  SIGNAL intrecclk      : std_logic := '0';
  SIGNAL intrecclk_d    : std_logic := '0';
  SIGNAL intrecclk_d1   : std_logic := '0';
  SIGNAL intrecclk_d2   : std_logic := '0';

  SIGNAL sync_valid        : std_logic := '0';
  SIGNAL sync_valid_store  : std_logic := '0';
  SIGNAL sync_found        : std_logic := '0';
  SIGNAL sync_detect       : std_logic := '0';
  SIGNAL sync_detect_d     : std_logic := '0';
  SIGNAL sync_detect_d1    : std_logic := '0';
  SIGNAL sync_detect_d2    : std_logic := '0';

  SIGNAL symstr_buffer    : std_logic_vector(11 downto 0) := (others=>'0');
  SIGNAL store_buffer     : std_logic_vector(9 downto 0) := (others=>'0');
  SIGNAL shift_buffer     : std_logic_vector(9 downto 0) := (others=>'0');

  SIGNAL sympat_sig  : std_logic_vector(11 downto 0) := str2std(sympat);

  CONSTANT clockboost: real := real(str2int(mult)) / real(str2int(div));
  CONSTANT tpd: time := 1.0 ns * str2real(pll_dly);

BEGIN

   WireDelay : block
   begin
   VitalWireDelay (SS_CLKIN_ipd, SS_CLKIN, tipd_SS_CLKIN);
   VitalWireDelay (CAL_ipd, CAL, tipd_CAL);
   VitalWireDelay (SIN_ipd, SIN, tipd_SIN);
   end block;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

  WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     clklock_last_rising_edge <= NOW;
     IF clklock_rising_edge_count = 0 THEN	
	start_inclk <= SS_CLKIN_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     END IF;
     END IF;
  --ct09010527466 WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='0');	 
  WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='1');	   	
     IF clklock_rising_edge_count = 1 THEN	
        clklock_half_period <= (NOW - clklock_last_rising_edge)/(clockboost*2.0);

	--ct09010527466clklock_half_period <= (NOW - clklock_last_rising_edge)/clockboost;  
	--ct09010527466clklock_last_falling_edge <= NOW;
     END IF;

  
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc THEN
        if(clockboost >1.0) then
	   FOR i IN 1 TO integer(2.0*clockboost) LOOP 	       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

    intrecclk <= SS_CLKIN_ipd;


    CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not after clklock_half_period when clock_count > 0 else
                     CLK_OUT_sig_d_not;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_sig_2d <= CLK_OUT_sig_d after clklock_half_period; 
    CLK_OUT_sig_3d <= CLK_OUT_sig_2d after clklock_half_period + tpd;

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    inthsrecclk <= CLK_OUT_plus_delay;

    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ;

    --ct102804 intrecclk  <= SS_CLKIN;
    RECCLK     <= intrecclk ;
    CSLOCK  <= CSLOCK_sig;

process(inthsrecclk,SS_CLKIN)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d <= SS_CLKIN;
    end if;
end process;

process(inthsrecclk,intrecclk_d1)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d1 <= intrecclk_d;
    end if;
end process;

process(inthsrecclk,intrecclk_d1)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d2 <= intrecclk_d1;
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
       shift_buffer(9)  <= SIN_ipd;
       shift_buffer(8)  <= shift_buffer(9);
       shift_buffer(7)  <= shift_buffer(8);
       shift_buffer(6)  <= shift_buffer(7);
       shift_buffer(5)  <= shift_buffer(6);
       shift_buffer(4)  <= shift_buffer(5);
       shift_buffer(3)  <= shift_buffer(4);
       shift_buffer(2)  <= shift_buffer(3);
       shift_buffer(1)  <= shift_buffer(2);
       shift_buffer(0)  <= shift_buffer(1);

       symstr_buffer(11) <= SIN_ipd;
       symstr_buffer(10) <= symstr_buffer(11);
       symstr_buffer(9)  <= symstr_buffer(10);
       symstr_buffer(8)  <= symstr_buffer(9);
       symstr_buffer(7)  <= symstr_buffer(8);
       symstr_buffer(6)  <= symstr_buffer(7);
       symstr_buffer(5)  <= symstr_buffer(6);
       symstr_buffer(4)  <= symstr_buffer(5);
       symstr_buffer(3)  <= symstr_buffer(4);
       symstr_buffer(2)  <= symstr_buffer(3);
       symstr_buffer(1)  <= symstr_buffer(2);
       symstr_buffer(0)  <= symstr_buffer(1);
    end if;
end process;

process(inthsrecclk, symstr_buffer)
begin
    if(symstr_buffer(11 downto 0) = sympat_sig(11 downto 0)) then
         sync_found <= '1';
    else
         sync_found <= '0';
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_valid <= sync_found or sync_valid;
    end if;
end process;

sync_valid_store <= sync_valid and not sync_detect_d;

process(intrecclk)
begin
    if(intrecclk'event and intrecclk='1') then
         sync_detect <= sync_valid_store and not sync_detect;
    end if;
end process;

process(intrecclk_d1)
begin
    if(intrecclk_d1'event and intrecclk_d1='1') then
         store_buffer <= shift_buffer; 
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_detect_d <= sync_detect_d2; 
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_detect_d2 <= sync_detect_d1; 
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
         sync_detect_d1 <= sync_detect or sync_detect_d1; 
    end if;
end process;

RXD0 <= store_buffer(0) and sync_detect_d;
RXD1 <= store_buffer(1) and sync_detect_d;
RXD2 <= store_buffer(2) and sync_detect_d;
RXD3 <= store_buffer(3) and sync_detect_d;
RXD4 <= store_buffer(4) and sync_detect_d;
RXD5 <= store_buffer(5) and sync_detect_d;
RXD6 <= store_buffer(6) and sync_detect_d;
RXD7 <= store_buffer(7) and sync_detect_d;
RXD8 <= store_buffer(8) and sync_detect_d;
RXD9 <= store_buffer(9) and sync_detect_d;

SYDT <= sync_valid_store;
end VITAL;

configuration CFG_CDRX_SS_10_VITAL of CDRX_SS_10 is 
        for VITAL
        end for; 
end CFG_CDRX_SS_10_VITAL;


----- VITAL model for cell HSLB_10B12B -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library lava1;
use lava1.components.all;

-- entity declaration --
entity HSLB_10B12B is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "12";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PLL_DLY  : string  := "1";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tipd_REFCLK    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CDRRST    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD0      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD1      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD2      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD3      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD4      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD5      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD6      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD7      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD8      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD9      :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      REFCLK            : in    STD_ULOGIC;
      CDRRST            : in    STD_ULOGIC;
      TXD0              : in    STD_ULOGIC;
      TXD1              : in    STD_ULOGIC;
      TXD2              : in    STD_ULOGIC;
      TXD3              : in    STD_ULOGIC;
      TXD4              : in    STD_ULOGIC;
      TXD5              : in    STD_ULOGIC;
      TXD6              : in    STD_ULOGIC;
      TXD7              : in    STD_ULOGIC;
      TXD8              : in    STD_ULOGIC;
      TXD9              : in    STD_ULOGIC;
      RXD0              : out   STD_ULOGIC;
      RXD1              : out   STD_ULOGIC;
      RXD2              : out   STD_ULOGIC;
      RXD3              : out   STD_ULOGIC;
      RXD4              : out   STD_ULOGIC;
      RXD5              : out   STD_ULOGIC;
      RXD6              : out   STD_ULOGIC;
      RXD7              : out   STD_ULOGIC;
      RXD8              : out   STD_ULOGIC;
      RXD9              : out   STD_ULOGIC;
      RECCLK            : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of HSLB_10B12B : entity is FALSE;
end HSLB_10B12B;


architecture VITAL of HSLB_10B12B is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL REFCLK_ipd	 : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;
  SIGNAL clk_in_period : TIME ;
  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_2d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_2d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  SIGNAL inthsrecclk    : std_logic := '0';
  SIGNAL intrecclk      : std_logic := '0';
  SIGNAL intrecclk_d    : std_logic := '0';
  SIGNAL intrecclk_d1   : std_logic := '0';
  SIGNAL intrecclk_d2   : std_logic := '0';

  SIGNAL sec_clk : STD_LOGIC ;
  SIGNAL sec_clk_count : INTEGER := 0 ;
  SIGNAL sec_out_sig : std_logic := '0' ;

  CONSTANT clockboost: real := real(str2int(mult)) / real(str2int(div));
  CONSTANT tpd: time := 1.0 ns * str2real(pll_dly);

BEGIN

   WireDelay : block
   begin
   VitalWireDelay (REFCLK_ipd, REFCLK, tipd_REFCLK);
   end block;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     clklock_last_rising_edge <= NOW;
     IF clklock_rising_edge_count = 0 THEN	
	start_inclk <= REFCLK_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     END IF;
     END IF;
 
  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='0');	  	
     IF clklock_rising_edge_count = 1 THEN	
	clklock_half_period <= (NOW - clklock_last_rising_edge)/clockboost; 	
	clklock_last_falling_edge <= NOW;
     END IF;
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc THEN
        if(clockboost >1.0) then
	   FOR i IN 1 TO integer(2.0*clockboost) LOOP 	       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

    intrecclk <= REFCLK_ipd;


    CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not after clklock_half_period when clock_count > 0 else
                     CLK_OUT_sig_d_not;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_sig_2d <= CLK_OUT_sig_d after clklock_half_period; 
    CLK_OUT_sig_3d <= CLK_OUT_sig_2d after clklock_half_period + tpd;

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    inthsrecclk <= CLK_OUT_plus_delay;

    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ;

    RECCLK  <= inthsrecclk;
    CSLOCK  <= CSLOCK_sig;

end VITAL;

configuration CFG_HSLB_10B12B_VITAL of HSLB_10B12B is 
        for VITAL
        end for; 
end CFG_HSLB_10B12B_VITAL;
----- VITAL model for cell HSLB_8B10B -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library lava1;
use lava1.components.all;

-- entity declaration --
entity HSLB_8B10B is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "10";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PLL_DLY  : string  := "1";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tipd_REFCLK    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_CDRRST    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD0      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD1      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD2      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD3      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD4      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD5      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD6      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD7      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD8      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD9      :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      REFCLK            : in    STD_ULOGIC;
      CDRRST            : in    STD_ULOGIC;
      TXD0              : in    STD_ULOGIC;
      TXD1              : in    STD_ULOGIC;
      TXD2              : in    STD_ULOGIC;
      TXD3              : in    STD_ULOGIC;
      TXD4              : in    STD_ULOGIC;
      TXD5              : in    STD_ULOGIC;
      TXD6              : in    STD_ULOGIC;
      TXD7              : in    STD_ULOGIC;
      TXD8              : in    STD_ULOGIC;
      TXD9              : in    STD_ULOGIC;
      RXD0              : out   STD_ULOGIC;
      RXD1              : out   STD_ULOGIC;
      RXD2              : out   STD_ULOGIC;
      RXD3              : out   STD_ULOGIC;
      RXD4              : out   STD_ULOGIC;
      RXD5              : out   STD_ULOGIC;
      RXD6              : out   STD_ULOGIC;
      RXD7              : out   STD_ULOGIC;
      RXD8              : out   STD_ULOGIC;
      RXD9              : out   STD_ULOGIC;
      RECCLK            : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of HSLB_8B10B : entity is FALSE;
end HSLB_8B10B;


architecture VITAL of HSLB_8B10B is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL REFCLK_ipd	 : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;
  SIGNAL clk_in_period : TIME ;
  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_2d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_2d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  SIGNAL inthsrecclk    : std_logic := '0';
  SIGNAL intrecclk      : std_logic := '0';
  SIGNAL intrecclk_d    : std_logic := '0';
  SIGNAL intrecclk_d1   : std_logic := '0';
  SIGNAL intrecclk_d2   : std_logic := '0';

  SIGNAL sec_clk : STD_LOGIC ;
  SIGNAL sec_clk_count : INTEGER := 0 ;
  SIGNAL sec_out_sig : std_logic := '0' ;

  CONSTANT clockboost: real := real(str2int(mult)) / real(str2int(div));
  CONSTANT tpd: time := 1.0 ns * str2real(pll_dly);

BEGIN

   WireDelay : block
   begin
   VitalWireDelay (REFCLK_ipd, REFCLK, tipd_REFCLK);
   end block;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     clklock_last_rising_edge <= NOW;
     IF clklock_rising_edge_count = 0 THEN	
	start_inclk <= REFCLK_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     END IF;
     END IF;
 
  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='0');	  	
     IF clklock_rising_edge_count = 1 THEN	
	clklock_half_period <= (NOW - clklock_last_rising_edge)/clockboost; 	
	clklock_last_falling_edge <= NOW;
     END IF;
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc THEN
        if(clockboost >1.0) then
	   FOR i IN 1 TO integer(2.0*clockboost) LOOP 	       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

    intrecclk <= REFCLK_ipd;


    CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not after clklock_half_period when clock_count > 0 else
                     CLK_OUT_sig_d_not;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_sig_2d <= CLK_OUT_sig_d after clklock_half_period; 
    CLK_OUT_sig_3d <= CLK_OUT_sig_2d after clklock_half_period + tpd;

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    inthsrecclk <= CLK_OUT_plus_delay;

    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ;

    RECCLK  <= inthsrecclk;
    CSLOCK  <= CSLOCK_sig;

end VITAL;

configuration CFG_HSLB_8B10B_VITAL of HSLB_8B10B is 
        for VITAL
        end for; 
end CFG_HSLB_8B10B_VITAL;
----- VITAL model for cell RX_SS_4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library lava1;
use lava1.components.all;

-- entity declaration --
entity RX_SS_4 is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "4";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PHASE_ADJ  : string  := "0.0";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tipd_SIN       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SS_CLKIN   :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      SIN               : in    STD_ULOGIC;
      SS_CLKIN          : in    STD_ULOGIC;
      RXD0              : out   STD_ULOGIC;
      RXD1              : out   STD_ULOGIC;
      RXD2              : out   STD_ULOGIC;
      RXD3              : out   STD_ULOGIC;
      RECCLK            : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of RX_SS_4 : entity is FALSE;
end RX_SS_4;


architecture VITAL of RX_SS_4 is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL SS_CLKIN_ipd	 : STD_ULOGIC := 'X';
  SIGNAL SIN_ipd	 : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;
  SIGNAL clk_in_period : TIME ;
  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_2d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_2d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  SIGNAL inthsrecclk    : std_logic := '0';
  SIGNAL intrecclk      : std_logic := '0';
  SIGNAL intrecclk_d    : std_logic := '0';
  SIGNAL intrecclk_d1   : std_logic := '0';
  SIGNAL intrecclk_d2   : std_logic := '0';

  SIGNAL store_buffer     : std_logic_vector(3 downto 0) := (others=>'0');
  SIGNAL shift_buffer     : std_logic_vector(3 downto 0) := (others=>'0');

  CONSTANT clockboost: real := real(str2int(mult)) / real(str2int(div));
  CONSTANT tpd: time := 1.0 ns * str2real(PHASE_ADJ);

BEGIN

   WireDelay : block
   begin
   VitalWireDelay (SS_CLKIN_ipd, SS_CLKIN, tipd_SS_CLKIN);
   VitalWireDelay (SIN_ipd, SIN, tipd_SIN);
   end block;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

  WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     clklock_last_rising_edge <= NOW;
     IF clklock_rising_edge_count = 0 THEN	
	start_inclk <= SS_CLKIN_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     END IF;
     END IF;
 
  WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='0');	  	
     IF clklock_rising_edge_count = 1 THEN	
	clklock_half_period <= (NOW - clklock_last_rising_edge)/clockboost; 	
	clklock_last_falling_edge <= NOW;
     END IF;
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc THEN
        if(clockboost >1.0) then
	   FOR i IN 1 TO integer(2.0*clockboost) LOOP 	       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

    intrecclk <= SS_CLKIN_ipd;


    CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not after clklock_half_period when clock_count > 0 else
                     CLK_OUT_sig_d_not;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_sig_2d <= CLK_OUT_sig_d after clklock_half_period; 
    CLK_OUT_sig_3d <= CLK_OUT_sig_2d after clklock_half_period + tpd;

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    inthsrecclk <= CLK_OUT_plus_delay;

    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ;

    RECCLK  <= intrecclk_d1;
    CSLOCK  <= CSLOCK_sig;

process(inthsrecclk,SS_CLKIN)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d <= SS_CLKIn;
    end if;
end process;

process(inthsrecclk,intrecclk_d1)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d1 <= intrecclk_d;
    end if;
end process;

process(inthsrecclk,intrecclk_d1)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d2 <= intrecclk_d1;
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
       shift_buffer(3)  <= SIN_ipd;
       shift_buffer(2)  <= shift_buffer(3);
       shift_buffer(1)  <= shift_buffer(2);
       shift_buffer(0)  <= shift_buffer(1);
    end if;
end process;

process(intrecclk_d1)
begin
    if(intrecclk_d1'event and intrecclk_d1='1') then
         store_buffer <= shift_buffer; 
    end if;
end process;

RXD0 <= store_buffer(0);
RXD1 <= store_buffer(1);
RXD2 <= store_buffer(2);
RXD3 <= store_buffer(3);

end VITAL;

configuration CFG_RX_SS_4_VITAL of RX_SS_4 is 
        for VITAL
        end for; 
end CFG_RX_SS_4_VITAL;
----- VITAL model for cell RX_SS_6 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library lava1;
use lava1.components.all;

-- entity declaration --
entity RX_SS_6 is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "6";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PHASE_ADJ  : string  := "0.0";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tipd_CAL       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SIN       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SS_CLKIN   :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      SIN               : in    STD_ULOGIC;
      SS_CLKIN          : in    STD_ULOGIC;
      RXD0              : out   STD_ULOGIC;
      RXD1              : out   STD_ULOGIC;
      RXD2              : out   STD_ULOGIC;
      RXD3              : out   STD_ULOGIC;
      RXD4              : out   STD_ULOGIC;
      RXD5              : out   STD_ULOGIC;
      RECCLK            : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of RX_SS_6 : entity is FALSE;
end RX_SS_6;

architecture VITAL of RX_SS_6 is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL SS_CLKIN_ipd	 : STD_ULOGIC := 'X';
  SIGNAL SIN_ipd	 : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;
  SIGNAL clk_in_period : TIME ;
  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_2d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_2d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  SIGNAL inthsrecclk    : std_logic := '0';
  SIGNAL intrecclk      : std_logic := '0';
  SIGNAL intrecclk_d    : std_logic := '0';
  SIGNAL intrecclk_d1   : std_logic := '0';
  SIGNAL intrecclk_d2   : std_logic := '0';

  SIGNAL store_buffer     : std_logic_vector(5 downto 0) := (others=>'0');
  SIGNAL shift_buffer     : std_logic_vector(5 downto 0) := (others=>'0');

  CONSTANT clockboost: real := real(str2int(mult)) / real(str2int(div));
  CONSTANT tpd: time := 1.0 ns * str2real(PHASE_ADJ);

BEGIN

   WireDelay : block
   begin
   VitalWireDelay (SS_CLKIN_ipd, SS_CLKIN, tipd_SS_CLKIN);
   VitalWireDelay (SIN_ipd, SIN, tipd_SIN);
   end block;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

  WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     clklock_last_rising_edge <= NOW;
     IF clklock_rising_edge_count = 0 THEN	
	start_inclk <= SS_CLKIN_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     END IF;
     END IF;
 
  WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='0');	  	
     IF clklock_rising_edge_count = 1 THEN	
	clklock_half_period <= (NOW - clklock_last_rising_edge)/clockboost; 	
	clklock_last_falling_edge <= NOW;
     END IF;
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc THEN
        if(clockboost >1.0) then
	   FOR i IN 1 TO integer(2.0*clockboost) LOOP 	       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

    intrecclk <= SS_CLKIN_ipd;


    CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not after clklock_half_period when clock_count > 0 else
                     CLK_OUT_sig_d_not;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_sig_2d <= CLK_OUT_sig_d after clklock_half_period; 
    CLK_OUT_sig_3d <= CLK_OUT_sig_2d after clklock_half_period + tpd;

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    inthsrecclk <= CLK_OUT_plus_delay;

    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ;

    RECCLK  <= intrecclk_d1;
    CSLOCK  <= CSLOCK_sig;

process(inthsrecclk,SS_CLKIN)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d <= SS_CLKIn;
    end if;
end process;

process(inthsrecclk,intrecclk_d1)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d1 <= intrecclk_d;
    end if;
end process;

process(inthsrecclk,intrecclk_d1)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d2 <= intrecclk_d1;
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
       shift_buffer(5)  <= SIN_ipd;
       shift_buffer(4)  <= shift_buffer(5);
       shift_buffer(3)  <= shift_buffer(4);
       shift_buffer(2)  <= shift_buffer(3);
       shift_buffer(1)  <= shift_buffer(2);
       shift_buffer(0)  <= shift_buffer(1);
    end if;
end process;

process(intrecclk_d1)
begin
    if(intrecclk_d1'event and intrecclk_d1='1') then
         store_buffer <= shift_buffer; 
    end if;
end process;

RXD0 <= store_buffer(0);
RXD1 <= store_buffer(1);
RXD2 <= store_buffer(2);
RXD3 <= store_buffer(3);
RXD4 <= store_buffer(4);
RXD5 <= store_buffer(5);

end VITAL;

configuration CFG_RX_SS_6_VITAL of RX_SS_6 is 
        for VITAL
        end for; 
end CFG_RX_SS_6_VITAL;
----- VITAL model for cell RX_SS_8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library lava1;
use lava1.components.all;

-- entity declaration --
entity RX_SS_8 is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "8";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PHASE_ADJ  : string  := "0.0";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tipd_SIN       :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_SS_CLKIN   :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      SIN               : in    STD_ULOGIC;
      SS_CLKIN          : in    STD_ULOGIC;
      RXD0              : out   STD_ULOGIC;
      RXD1              : out   STD_ULOGIC;
      RXD2              : out   STD_ULOGIC;
      RXD3              : out   STD_ULOGIC;
      RXD4              : out   STD_ULOGIC;
      RXD5              : out   STD_ULOGIC;
      RXD6              : out   STD_ULOGIC;
      RXD7              : out   STD_ULOGIC;
      RECCLK            : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of RX_SS_8 : entity is FALSE;
end RX_SS_8;

architecture VITAL of RX_SS_8 is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL SS_CLKIN_ipd	 : STD_ULOGIC := 'X';
  SIGNAL SIN_ipd	 : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;
  SIGNAL clk_in_period : TIME ;
  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_2d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_2d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  SIGNAL inthsrecclk    : std_logic := '0';
  SIGNAL intrecclk      : std_logic := '0';
  SIGNAL intrecclk_d    : std_logic := '0';
  SIGNAL intrecclk_d1   : std_logic := '0';
  SIGNAL intrecclk_d2   : std_logic := '0';

  SIGNAL store_buffer     : std_logic_vector(7 downto 0) := (others=>'0');
  SIGNAL shift_buffer     : std_logic_vector(7 downto 0) := (others=>'0');

  CONSTANT clockboost: real := real(str2int(mult)) / real(str2int(div));
  CONSTANT tpd: time := 1.0 ns * str2real(PHASE_ADJ);

BEGIN

   WireDelay : block
   begin
   VitalWireDelay (SS_CLKIN_ipd, SS_CLKIN, tipd_SS_CLKIN);
   VitalWireDelay (SIN_ipd, SIN, tipd_SIN);
   end block;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

  WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     clklock_last_rising_edge <= NOW;
     IF clklock_rising_edge_count = 0 THEN	
	start_inclk <= SS_CLKIN_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     END IF;
     END IF;
 
  WAIT UNTIL (SS_CLKIN_ipd'EVENT AND SS_CLKIN_ipd='0');	  	
     IF clklock_rising_edge_count = 1 THEN	
	clklock_half_period <= (NOW - clklock_last_rising_edge)/clockboost; 	
	clklock_last_falling_edge <= NOW;
     END IF;
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc THEN
        if(clockboost >1.0) then
	   FOR i IN 1 TO integer(2.0*clockboost) LOOP 	       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

    intrecclk <= SS_CLKIN_ipd;


    CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not after clklock_half_period when clock_count > 0 else
                     CLK_OUT_sig_d_not;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_sig_2d <= CLK_OUT_sig_d after clklock_half_period; 
    CLK_OUT_sig_3d <= CLK_OUT_sig_2d after clklock_half_period + tpd;

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    inthsrecclk <= CLK_OUT_plus_delay;

    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ;

    RECCLK  <= intrecclk_d1;
    CSLOCK  <= CSLOCK_sig;


process(inthsrecclk,SS_CLKIN)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d <= SS_CLKIn;
    end if;
end process;

process(inthsrecclk,intrecclk_d1)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d1 <= intrecclk_d;
    end if;
end process;

process(inthsrecclk,intrecclk_d1)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
        intrecclk_d2 <= intrecclk_d1;
    end if;
end process;

process(inthsrecclk)
begin
    if(inthsrecclk'event and inthsrecclk='1') then
       shift_buffer(7)  <= SIN_ipd;
       shift_buffer(6)  <= shift_buffer(7);
       shift_buffer(5)  <= shift_buffer(6);
       shift_buffer(4)  <= shift_buffer(5);
       shift_buffer(3)  <= shift_buffer(4);
       shift_buffer(2)  <= shift_buffer(3);
       shift_buffer(1)  <= shift_buffer(2);
       shift_buffer(0)  <= shift_buffer(1);
    end if;
end process;

process(intrecclk_d1)
begin
    if(intrecclk_d1'event and intrecclk_d1='1') then
         store_buffer <= shift_buffer; 
    end if;
end process;

RXD0 <= store_buffer(0);
RXD1 <= store_buffer(1);
RXD2 <= store_buffer(2);
RXD3 <= store_buffer(3);
RXD4 <= store_buffer(4);
RXD5 <= store_buffer(5);
RXD6 <= store_buffer(6);
RXD7 <= store_buffer(7);

end VITAL;

configuration CFG_RX_SS_8_VITAL of RX_SS_8 is 
        for VITAL
        end for; 
end CFG_RX_SS_8_VITAL;

----- VITAL model for cell TX_10B12B -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library lava1;
use lava1.components.all;

-- entity declaration --
entity TX_10B12B is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "12";
      DIV      : string  := "1";
      PLL_DLY  : string  := "0.0";
      LOCK_CYC : integer := 2;
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tsetup_TXD0_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD0_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD1_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD1_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD2_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD2_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD3_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD3_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD4_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD4_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD5_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD5_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD6_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD6_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD7_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD7_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD8_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD8_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD9_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD9_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tipd_REFCLK    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD0      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD1      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD2      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD3      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD4      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD5      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD6      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD7      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD8      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD9      :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      REFCLK            : in    STD_ULOGIC;
      TXD0              : in    STD_ULOGIC;
      TXD1              : in    STD_ULOGIC;
      TXD2              : in    STD_ULOGIC;
      TXD3              : in    STD_ULOGIC;
      TXD4              : in    STD_ULOGIC;
      TXD5              : in    STD_ULOGIC;
      TXD6              : in    STD_ULOGIC;
      TXD7              : in    STD_ULOGIC;
      TXD8              : in    STD_ULOGIC;
      TXD9              : in    STD_ULOGIC;
      SOUT              : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of TX_10B12B : entity is FALSE;
end TX_10B12B;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library lava1;
architecture VITAL of TX_10B12B is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL REFCLK_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD0_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD1_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD2_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD3_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD4_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD5_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD6_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD7_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD8_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD9_ipd	 : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL clklock_half_period1 : TIME :=100 ns;
  SIGNAL clklock_half_period0 : TIME :=100 ns;
  SIGNAL refclk_half_period : TIME :=100 ns;
  SIGNAL refclk_half_period1 : TIME :=100 ns;
  SIGNAL refclk_half_period0 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly1 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly0 : TIME :=100 ns;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_falling_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;

  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;

  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  SIGNAL inthsrecclk    : std_logic := '0';
  SIGNAL intrecclk      : std_logic := '0';
  SIGNAL intrecclk_d    : std_logic := '0';
  SIGNAL intrecclk_d1   : std_logic := '0';
  SIGNAL intrecclk_d2   : std_logic := '0';

  SIGNAL data_out       : std_logic_vector(11 downto 0) := (others => '0');
  SIGNAL shift_buffer   : std_logic_vector(11 downto 0) := (others => '0');
  SIGNAL cnt            : std_logic_vector(3 downto 0) := (others => '0');

  CONSTANT clockboost: integer := str2int(mult) / str2int(div);
  CONSTANT tpd: time := 1.0 ns * str2real(pll_dly);

  SIGNAL SOUT_int       : std_logic := '0';

BEGIN

   WireDelay : block
   begin
   VitalWireDelay (REFCLK_ipd, REFCLK, tipd_REFCLK);
   VitalWireDelay (TXD0_ipd, TXD0, tipd_TXD0);
   VitalWireDelay (TXD1_ipd, TXD1, tipd_TXD1);
   VitalWireDelay (TXD2_ipd, TXD2, tipd_TXD2);
   VitalWireDelay (TXD3_ipd, TXD3, tipd_TXD3);
   VitalWireDelay (TXD4_ipd, TXD4, tipd_TXD4);
   VitalWireDelay (TXD5_ipd, TXD5, tipd_TXD5);
   VitalWireDelay (TXD6_ipd, TXD6, tipd_TXD6);
   VitalWireDelay (TXD7_ipd, TXD7, tipd_TXD7);
   VitalWireDelay (TXD8_ipd, TXD8, tipd_TXD8);
   VitalWireDelay (TXD9_ipd, TXD9, tipd_TXD9);
   end block;

   VITALBehavior : process

        variable Tviol_TXD0_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD1_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD2_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD3_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD4_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD5_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD6_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD7_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD8_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD9_REFCLK_posedge     : std_ulogic  := '0';
        variable Tmkr_TXD0_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD1_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD2_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD3_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD4_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD5_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD6_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD7_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD8_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD9_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Violation                    : std_ulogic := '0';

   begin

        if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD0_REFCLK_posedge,
          TimingData              => Tmkr_TXD0_REFCLK_posedge,
          TestSignal              => TXD0_ipd,
          TestSignalName          => "TXD0",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD0_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD0_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD0_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD0_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_10B12B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD1_REFCLK_posedge,
          TimingData              => Tmkr_TXD1_REFCLK_posedge,
          TestSignal              => TXD1_ipd,
          TestSignalName          => "TXD1",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD1_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD1_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD1_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD1_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_10B12B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD2_REFCLK_posedge,
          TimingData              => Tmkr_TXD2_REFCLK_posedge,
          TestSignal              => TXD2_ipd,
          TestSignalName          => "TXD2",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD2_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD2_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD2_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD2_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_10B12B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD3_REFCLK_posedge,
          TimingData              => Tmkr_TXD3_REFCLK_posedge,
          TestSignal              => TXD3_ipd,
          TestSignalName          => "TXD3",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD3_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD3_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD3_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD3_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_10B12B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD4_REFCLK_posedge,
          TimingData              => Tmkr_TXD4_REFCLK_posedge,
          TestSignal              => TXD4_ipd,
          TestSignalName          => "TXD4",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD4_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD4_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD4_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD4_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_10B12B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD5_REFCLK_posedge,
          TimingData              => Tmkr_TXD5_REFCLK_posedge,
          TestSignal              => TXD5_ipd,
          TestSignalName          => "TXD5",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD5_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD5_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD5_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD5_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_10B12B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD6_REFCLK_posedge,
          TimingData              => Tmkr_TXD6_REFCLK_posedge,
          TestSignal              => TXD6_ipd,
          TestSignalName          => "TXD6",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD6_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD6_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD6_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD6_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_10B12B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD7_REFCLK_posedge,
          TimingData              => Tmkr_TXD7_REFCLK_posedge,
          TestSignal              => TXD7_ipd,
          TestSignalName          => "TXD7",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD7_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD7_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD7_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD7_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_10B12B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD8_REFCLK_posedge,
          TimingData              => Tmkr_TXD8_REFCLK_posedge,
          TestSignal              => TXD8_ipd,
          TestSignalName          => "TXD8",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD8_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD8_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD8_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD8_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_10B12B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD9_REFCLK_posedge,
          TimingData              => Tmkr_TXD9_REFCLK_posedge,
          TestSignal              => TXD9_ipd,
          TestSignalName          => "TXD9",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD9_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD9_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD9_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD9_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_10B12B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

    Violation := Tviol_TXD0_REFCLK_posedge or Tviol_TXD1_REFCLK_posedge or 
                 Tviol_TXD2_REFCLK_posedge or Tviol_TXD3_REFCLK_posedge or 
                 Tviol_TXD4_REFCLK_posedge or Tviol_TXD5_REFCLK_posedge or 
                 Tviol_TXD6_REFCLK_posedge or Tviol_TXD7_REFCLK_posedge or 
                 Tviol_TXD8_REFCLK_posedge or Tviol_TXD9_REFCLK_posedge ;

    wait on REFCLK_ipd, TXD0_ipd, TXD1_ipd, TXD2_ipd, TXD3_ipd, TXD4_ipd, TXD5_ipd, TXD6_ipd, TXD7_ipd, TXD8_ipd, TXD9_ipd;
  end process VITALBehavior;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

       clklock_half_period <= (clklock_half_period0 + clklock_half_period1)/2;
       refclk_half_period <= (refclk_half_period0 + refclk_half_period1)/2;

  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     IF clklock_rising_edge_count = 0 THEN
        clklock_last_rising_edge <= NOW;	
	start_inclk <= REFCLK_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
       refclk_half_period0 <= (NOW - clklock_last_falling_edge);
       clklock_half_period0 <= (NOW - clklock_last_falling_edge)* str2int(div)/str2int(mult);
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     elsif clklock_rising_edge_count = 2 THEN
       clklock_half_period_minus_dly0 <= (NOW - clklock_last_falling_edge) + tpd;
       --clklock_half_period <= (clklock_half_period0 + clklock_half_period1)/2;
     END IF;
     END IF;
 
  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='0');
     clklock_falling_edge_count <= clklock_falling_edge_count +1;	  	
     IF clklock_falling_edge_count = 0 THEN	
	clklock_last_falling_edge <= NOW;
	refclk_half_period1 <= (NOW - clklock_last_rising_edge); 
	clklock_half_period1 <= (NOW - clklock_last_rising_edge)* str2int(div)/str2int(mult); 
     ELSIF clklock_falling_edge_count = 1 THEN
        clklock_half_period_minus_dly1 <= (NOW - clklock_last_rising_edge) + tpd;
     END IF;
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc + 1 THEN
         if(clockboost >1) then
	   FOR i IN 1 TO (2*clockboost) LOOP      
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

process
begin
    wait until CLK_OUT_sig_d_start = '1'; LOOP
     wait for clklock_half_period1;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not;
     wait for clklock_half_period0;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not ;
   END LOOP;
end process;

process
begin
   wait until (clklock_falling_edge_count >= lock_cyc + 1);
    wait for clklock_half_period_minus_dly0;
   CLK_OUT_start <= '1';
end process;

process
begin
   wait until  CLK_OUT_start = '1'; LOOP
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d;
     wait for clklock_half_period1;
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d ;
     wait for clklock_half_period0;
     END LOOP;
end process;


    intrecclk <= REFCLK_ipd;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    inthsrecclk <= CLK_OUT_plus_delay;

    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ;

    CSLOCK  <= CSLOCK_sig;

process (inthsrecclk)
begin
        if(inthsrecclk'event and inthsrecclk = '1') then
           if cnt = "1100" then
              cnt <= "0001";
            else
              cnt <= cnt + "0001";
           end if; 
        end if;
end process;


data_out(0)  <= '1' when cnt = "1100" else shift_buffer(1) ;
data_out(1)  <= TXD0_ipd when cnt = "1100" else shift_buffer(2) ;
data_out(2)  <= TXD1_ipd when cnt = "1100" else shift_buffer(3) ;
data_out(3)  <= TXD2_ipd when cnt = "1100" else shift_buffer(4) ;
data_out(4)  <= TXD3_ipd when cnt = "1100" else shift_buffer(5) ;
data_out(5)  <= TXD4_ipd when cnt = "1100" else shift_buffer(6) ;
data_out(6)  <= TXD5_ipd when cnt = "1100" else shift_buffer(7) ;
data_out(7)  <= TXD6_ipd when cnt = "1100" else shift_buffer(8) ;
data_out(8)  <= TXD7_ipd when cnt = "1100" else shift_buffer(9) ;
data_out(9)  <= TXD8_ipd when cnt = "1100" else shift_buffer(10);
data_out(10)  <= TXD9_ipd when cnt = "1100" else shift_buffer(11);
data_out(11)  <= '0' when cnt = "1100" else shift_buffer(0);

process (inthsrecclk,data_out)
begin
        if(inthsrecclk'event and inthsrecclk='1') then
          SOUT_int         <= data_out(0);
          shift_buffer(1)  <= data_out(1);
          shift_buffer(2)  <= data_out(2);
          shift_buffer(3)  <= data_out(3);
          shift_buffer(4)  <= data_out(4);
          shift_buffer(5)  <= data_out(5);
          shift_buffer(6)  <= data_out(6);
          shift_buffer(7)  <= data_out(7);
          shift_buffer(8)  <= data_out(8);
          shift_buffer(9)  <= data_out(9);
          shift_buffer(10)  <= data_out(10);
          shift_buffer(11)  <= data_out(11);
        end if;
end process;

SOUT <= SOUT_int after refclk_half_period*2*str2int(div)/str2int(mult);

end VITAL;

configuration CFG_TX_10B12B_VITAL of TX_10B12B is 
        for VITAL
        end for; 
end CFG_TX_10B12B_VITAL;

----- VITAL model for cell TX_8B10B -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library lava1;
use lava1.components.all;

-- entity declaration --
entity TX_8B10B is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "10";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PLL_DLY  : string  := "0.0";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tsetup_TXD0_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD0_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD1_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD1_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD2_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD2_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD3_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD3_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD4_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD4_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD5_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD5_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD6_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD6_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD7_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD7_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD8_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD8_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD9_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD9_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tipd_REFCLK    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD0      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD1      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD2      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD3      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD4      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD5      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD6      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD7      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD8      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD9      :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      REFCLK            : in    STD_ULOGIC;
      TXD0              : in    STD_ULOGIC;
      TXD1              : in    STD_ULOGIC;
      TXD2              : in    STD_ULOGIC;
      TXD3              : in    STD_ULOGIC;
      TXD4              : in    STD_ULOGIC;
      TXD5              : in    STD_ULOGIC;
      TXD6              : in    STD_ULOGIC;
      TXD7              : in    STD_ULOGIC;
      TXD8              : in    STD_ULOGIC;
      TXD9              : in    STD_ULOGIC;
      SOUT              : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of TX_8B10B : entity is FALSE;
end TX_8B10B;


architecture VITAL of TX_8B10B is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL REFCLK_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD0_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD1_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD2_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD3_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD4_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD5_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD6_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD7_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD8_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD9_ipd	 : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL clklock_half_period1 : TIME :=100 ns;
  SIGNAL clklock_half_period0 : TIME :=100 ns;
  SIGNAL refclk_half_period : TIME :=100 ns;
  SIGNAL refclk_half_period1 : TIME :=100 ns;
  SIGNAL refclk_half_period0 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly1 : TIME :=100 ns;
  SIGNAL clklock_half_period_minus_dly0 : TIME :=100 ns;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_falling_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;

  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;

  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';


  SIGNAL inthsrecclk    : std_logic := '0';
  SIGNAL intrecclk      : std_logic := '0';
  SIGNAL intrecclk_d    : std_logic := '0';
  SIGNAL intrecclk_d1   : std_logic := '0';
  SIGNAL intrecclk_d2   : std_logic := '0';

  SIGNAL data_out       : std_logic_vector(9 downto 0) := (others => '0');
  SIGNAL shift_buffer   : std_logic_vector(9 downto 0) := (others => '0');
  SIGNAL cnt            : std_logic_vector(3 downto 0) := (others => '0');

  CONSTANT clockboost: integer := str2int(mult) / str2int(div);
  CONSTANT tpd: time := 1.0 ns * str2real(pll_dly);

  SIGNAL SOUT_int, SOUT_int1       : std_logic := '0';

BEGIN

   WireDelay : block
   begin
     VitalWireDelay (REFCLK_ipd, REFCLK, tipd_REFCLK);
     VitalWireDelay (TXD0_ipd, TXD0, tipd_TXD0);
     VitalWireDelay (TXD1_ipd, TXD1, tipd_TXD1);
     VitalWireDelay (TXD2_ipd, TXD2, tipd_TXD2);
     VitalWireDelay (TXD3_ipd, TXD3, tipd_TXD3);
     VitalWireDelay (TXD4_ipd, TXD4, tipd_TXD4);
     VitalWireDelay (TXD5_ipd, TXD5, tipd_TXD5);
     VitalWireDelay (TXD6_ipd, TXD6, tipd_TXD6);
     VitalWireDelay (TXD7_ipd, TXD7, tipd_TXD7);
     VitalWireDelay (TXD8_ipd, TXD8, tipd_TXD8);
     VitalWireDelay (TXD9_ipd, TXD9, tipd_TXD9);
   end block;

  VITALBehavior : process

        variable Tviol_TXD0_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD1_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD2_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD3_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD4_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD5_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD6_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD7_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD8_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD9_REFCLK_posedge     : std_ulogic  := '0';
        variable Tmkr_TXD0_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD1_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD2_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD3_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD4_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD5_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD6_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD7_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD8_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD9_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Violation                    : std_ulogic  := '0';
     begin
       if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD0_REFCLK_posedge,
          TimingData              => Tmkr_TXD0_REFCLK_posedge,
          TestSignal              => TXD0_ipd,
          TestSignalName          => "TXD0",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD0_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD0_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD0_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD0_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_8B10B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD1_REFCLK_posedge,
          TimingData              => Tmkr_TXD1_REFCLK_posedge,
          TestSignal              => TXD1_ipd,
          TestSignalName          => "TXD1",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD1_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD1_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD1_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD1_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_8B10B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD2_REFCLK_posedge,
          TimingData              => Tmkr_TXD2_REFCLK_posedge,
          TestSignal              => TXD2_ipd,
          TestSignalName          => "TXD2",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD2_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD2_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD2_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD2_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_8B10B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD3_REFCLK_posedge,
          TimingData              => Tmkr_TXD3_REFCLK_posedge,
          TestSignal              => TXD3_ipd,
          TestSignalName          => "TXD3",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD3_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD3_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD3_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD3_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_8B10B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD4_REFCLK_posedge,
          TimingData              => Tmkr_TXD4_REFCLK_posedge,
          TestSignal              => TXD4_ipd,
          TestSignalName          => "TXD4",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD4_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD4_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD4_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD4_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_8B10B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD5_REFCLK_posedge,
          TimingData              => Tmkr_TXD5_REFCLK_posedge,
          TestSignal              => TXD5_ipd,
          TestSignalName          => "TXD5",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD5_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD5_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD5_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD5_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_8B10B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD6_REFCLK_posedge,
          TimingData              => Tmkr_TXD6_REFCLK_posedge,
          TestSignal              => TXD6_ipd,
          TestSignalName          => "TXD6",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD6_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD6_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD6_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD6_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_8B10B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD7_REFCLK_posedge,
          TimingData              => Tmkr_TXD7_REFCLK_posedge,
          TestSignal              => TXD7_ipd,
          TestSignalName          => "TXD7",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD7_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD7_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD7_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD7_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_8B10B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD8_REFCLK_posedge,
          TimingData              => Tmkr_TXD8_REFCLK_posedge,
          TestSignal              => TXD8_ipd,
          TestSignalName          => "TXD8",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD8_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD8_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD8_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD8_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_8B10B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD9_REFCLK_posedge,
          TimingData              => Tmkr_TXD9_REFCLK_posedge,
          TestSignal              => TXD9_ipd,
          TestSignalName          => "TXD9",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD9_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD9_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD9_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD9_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_8B10B",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
       end if;

    Violation := Tviol_TXD0_REFCLK_posedge or Tviol_TXD1_REFCLK_posedge or 
                 Tviol_TXD2_REFCLK_posedge or Tviol_TXD3_REFCLK_posedge or 
                 Tviol_TXD4_REFCLK_posedge or Tviol_TXD5_REFCLK_posedge or 
                 Tviol_TXD6_REFCLK_posedge or Tviol_TXD7_REFCLK_posedge or 
                 Tviol_TXD8_REFCLK_posedge or Tviol_TXD9_REFCLK_posedge ;

    wait on REFCLK_ipd, TXD0_ipd, TXD1_ipd, TXD2_ipd, TXD3_ipd, TXD4_ipd, TXD5_ipd, TXD6_ipd, TXD7_ipd, TXD8_ipd, TXD9_ipd;
  end process VITALBehavior;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

       clklock_half_period <= (clklock_half_period0 + clklock_half_period1)/2;
       refclk_half_period <= (refclk_half_period0 + refclk_half_period1)/2;

  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     IF clklock_rising_edge_count = 0 THEN
        clklock_last_rising_edge <= NOW;	
	start_inclk <= REFCLK_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
       refclk_half_period0 <= (NOW - clklock_last_falling_edge);
       clklock_half_period0 <= (NOW - clklock_last_falling_edge)* str2int(div)/str2int(mult);
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     elsif clklock_rising_edge_count = 2 THEN
       clklock_half_period_minus_dly0 <= (NOW - clklock_last_falling_edge) + tpd;
       --clklock_half_period <= (clklock_half_period0 + clklock_half_period1)/2;
     END IF;
     END IF;
 
  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='0');
     clklock_falling_edge_count <= clklock_falling_edge_count +1;	  	
     IF clklock_falling_edge_count = 0 THEN	
	clklock_last_falling_edge <= NOW;
	refclk_half_period1 <= (NOW - clklock_last_rising_edge); 
	clklock_half_period1 <= (NOW - clklock_last_rising_edge)* str2int(div)/str2int(mult);
     ELSIF clklock_falling_edge_count = 1 THEN
        clklock_half_period_minus_dly1 <= (NOW - clklock_last_rising_edge) + tpd;
     END IF;
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc + 1 THEN
         if(clockboost >1) then
	   FOR i IN 1 TO (2*clockboost) LOOP       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

process
begin
    wait until CLK_OUT_sig_d_start = '1'; LOOP
     wait for clklock_half_period1;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not;
     wait for clklock_half_period0;
   CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not ;
   END LOOP;
end process;

process
begin
   wait until (clklock_falling_edge_count >= lock_cyc + 1);
    wait for clklock_half_period_minus_dly0;
   CLK_OUT_start <= '1';
end process;

process
begin
   wait until  CLK_OUT_start = '1'; LOOP
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d;
     wait for clklock_half_period1;
      CLK_OUT_sig_3d <= not CLK_OUT_sig_3d ;
     wait for clklock_half_period0;
     END LOOP;
end process;

    intrecclk <= REFCLK_ipd;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    inthsrecclk <= CLK_OUT_plus_delay;

    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ;

    CSLOCK  <= CSLOCK_sig;

process (inthsrecclk)
begin
        if(inthsrecclk'event and inthsrecclk = '1') then
           if cnt = "1010" then
              cnt <= "0001";
            else
              cnt <= cnt + "0001";
           end if; 
        end if;
end process;


data_out(0)  <= TXD0_ipd when cnt = "1010" else shift_buffer(1);
data_out(1)  <= TXD1_ipd when cnt = "1010" else shift_buffer(2);
data_out(2)  <= TXD2_ipd when cnt = "1010" else shift_buffer(3);
data_out(3)  <= TXD3_ipd when cnt = "1010" else shift_buffer(4);
data_out(4)  <= TXD4_ipd when cnt = "1010" else shift_buffer(5);
data_out(5)  <= TXD5_ipd when cnt = "1010" else shift_buffer(6);
data_out(6)  <= TXD6_ipd when cnt = "1010" else shift_buffer(7);
data_out(7)  <= TXD7_ipd when cnt = "1010" else shift_buffer(8);
data_out(8)  <= TXD8_ipd when cnt = "1010" else shift_buffer(9);
data_out(9)  <= TXD9_ipd when cnt = "1010" else shift_buffer(0);

process (inthsrecclk,data_out)
begin
        if(inthsrecclk'event and inthsrecclk='1') then
          SOUT_int         <= data_out(0);
          shift_buffer(1)  <= data_out(1);
          shift_buffer(2)  <= data_out(2);
          shift_buffer(3)  <= data_out(3);
          shift_buffer(4)  <= data_out(4);
          shift_buffer(5)  <= data_out(5);
          shift_buffer(6)  <= data_out(6);
          shift_buffer(7)  <= data_out(7);
          shift_buffer(8)  <= data_out(8);
          shift_buffer(9)  <= data_out(9);
        end if;
end process;

SOUT <= SOUT_int1 after refclk_half_period*2*str2int(div)/str2int(mult);
SOUT_int1 <= SOUT_int after refclk_half_period*2*str2int(div)/str2int(mult);

end VITAL;

configuration CFG_TX_8B10B_VITAL of TX_8B10B is 
        for VITAL
        end for; 
end CFG_TX_8B10B_VITAL;

----- VITAL model for cell TX_SS_4 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library lava1;
use lava1.components.all;

-- entity declaration --
entity TX_SS_4 is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "4";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PLL_DLY  : string  := "0.0";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tsetup_TXD0_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD0_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD1_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD1_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD2_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD2_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD3_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD3_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tipd_REFCLK    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD0      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD1      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD2      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD3      :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      REFCLK            : in    STD_ULOGIC;
      TXD0              : in    STD_ULOGIC;
      TXD1              : in    STD_ULOGIC;
      TXD2              : in    STD_ULOGIC;
      TXD3              : in    STD_ULOGIC;
      SOUT              : out   STD_ULOGIC;
      SS_CLKOUT         : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of TX_SS_4 : entity is FALSE;
end TX_SS_4;


architecture VITAL of TX_SS_4 is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL REFCLK_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD0_ipd        : STD_ULOGIC := 'X';
  SIGNAL TXD1_ipd        : STD_ULOGIC := 'X';
  SIGNAL TXD2_ipd        : STD_ULOGIC := 'X';
  SIGNAL TXD3_ipd        : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;
  SIGNAL clk_in_period : TIME ;
  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_2d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_2d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  SIGNAL inthsrecclk    : std_logic := '0';
  SIGNAL intrecclk      : std_logic := '0';
  SIGNAL intrecclk_d    : std_logic := '0';
  SIGNAL intrecclk_d1   : std_logic := '0';
  SIGNAL intrecclk_d2   : std_logic := '0';

  SIGNAL data_out       : std_logic_vector(3 downto 0) := (others => '0');
  SIGNAL shift_buffer   : std_logic_vector(3 downto 0) := (others => '0');
  SIGNAL cnt            : std_logic_vector(3 downto 0) := (others => '0');

  signal sout1 : std_logic := '0'; --ct102804
   
  CONSTANT clockboost: real := real(str2int(mult)) / real(str2int(div));
  CONSTANT tpd: time := 1.0 ns * str2real(pll_dly);

BEGIN

   WireDelay : block
   begin
   VitalWireDelay (REFCLK_ipd, REFCLK, tipd_REFCLK);
   VitalWireDelay (TXD0_ipd, TXD0, tipd_TXD0);
   VitalWireDelay (TXD1_ipd, TXD1, tipd_TXD1);
   VitalWireDelay (TXD2_ipd, TXD2, tipd_TXD2);
   VitalWireDelay (TXD3_ipd, TXD3, tipd_TXD3);
   end block;

   VITALBehavior  : process
        variable Tviol_TXD0_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD1_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD2_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD3_REFCLK_posedge     : std_ulogic  := '0';
        variable Tmkr_TXD0_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD1_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD2_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD3_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Violation                    : std_logic    := '0'; 
    begin
      if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD0_REFCLK_posedge,
          TimingData              => Tmkr_TXD0_REFCLK_posedge,
          TestSignal              => TXD0_ipd,
          TestSignalName          => "TXD0",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD0_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD0_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD0_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD0_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD1_REFCLK_posedge,
          TimingData              => Tmkr_TXD1_REFCLK_posedge,
          TestSignal              => TXD1_ipd,
          TestSignalName          => "TXD1",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD1_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD1_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD1_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD1_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD2_REFCLK_posedge,
          TimingData              => Tmkr_TXD2_REFCLK_posedge,
          TestSignal              => TXD2_ipd,
          TestSignalName          => "TXD2",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD2_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD2_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD2_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD2_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD3_REFCLK_posedge,
          TimingData              => Tmkr_TXD3_REFCLK_posedge,
          TestSignal              => TXD3_ipd,
          TestSignalName          => "TXD3",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD3_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD3_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD3_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD3_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_4",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
      end if;

     Violation := Tviol_TXD0_REFCLK_posedge or Tviol_TXD1_REFCLK_posedge or 
                 Tviol_TXD2_REFCLK_posedge or Tviol_TXD3_REFCLK_posedge;

    wait on REFCLK_ipd, TXD0_ipd, TXD1_ipd, TXD2_ipd, TXD3_ipd;
  end process VITALBehavior; 

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     clklock_last_rising_edge <= NOW;
     IF clklock_rising_edge_count = 0 THEN	
	start_inclk <= REFCLK_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     END IF;
     END IF;
 

  --ct09010527466 WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='0');	 
  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='1'); 	
     IF clklock_rising_edge_count = 1 THEN	
       clklock_half_period <= (NOW - clklock_last_rising_edge)/(clockboost*2.0);

	--ct09010527466 clklock_half_period <= (NOW - clklock_last_rising_edge)/clockboost; 	
	--ct09010527466 clklock_last_falling_edge <= NOW;
     END IF;

END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc THEN
        if(clockboost >1.0) then
	   FOR i IN 1 TO integer(2.0*clockboost) LOOP 	       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

    intrecclk <= REFCLK_ipd;


    CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not after clklock_half_period when clock_count > 0 else
                     CLK_OUT_sig_d_not;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_sig_2d <= CLK_OUT_sig_d after clklock_half_period; 
    CLK_OUT_sig_3d <= CLK_OUT_sig_2d after clklock_half_period + tpd;

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    inthsrecclk <= CLK_OUT_plus_delay;
    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ; --ct102804
    CSLOCK <= CSLOCK_sig;
    SS_CLKOUT <= intrecclk;

process (inthsrecclk)
begin
        if(inthsrecclk'event and inthsrecclk = '1') then
           if cnt = "0011" then
              cnt <= "0000";
            else
              cnt <= cnt + "0001";
           end if; 
        end if;
end process;


--data_out(0)  <= TXD0_ipd when cnt = "0011" else shift_buffer(1);
--data_out(1)  <= TXD1_ipd when cnt = "0011" else shift_buffer(2);
--data_out(2)  <= TXD2_ipd when cnt = "0011" else shift_buffer(3);
--data_out(3)  <= TXD3_ipd when cnt = "0011" else shift_buffer(0);

--process (inthsrecclk,data_out)
--begin
--        if(inthsrecclk'event and inthsrecclk='1') then
--          SOUT             <= data_out(0);
--          shift_buffer(1)  <= data_out(1);
--          shift_buffer(2)  <= data_out(2);
--          shift_buffer(3)  <= data_out(3);
--        end if;
--end process;

  process (inthsrecclk)
  begin
     if(inthsrecclk'event and inthsrecclk='1') then
        if ( cnt = "0000" ) then
           data_out <= TXD3_ipd & TXD2_ipd & TXD1_ipd & TXD0_ipd;
        			
        else 
           data_out(2 downto 0) <= data_out(3 downto 1);
           data_out(3) <= data_out(0);
        end if;
     end if;
  end process;
  
  process (inthsrecclk)
  begin
     if(inthsrecclk'event and inthsrecclk='1') then
        sout1<= data_out(0);
        SOUT <= sout1;
     end if;
  end process;

end VITAL;

configuration CFG_TX_SS_4_VITAL of TX_SS_4 is 
        for VITAL
        end for; 
end CFG_TX_SS_4_VITAL;

----- VITAL model for cell TX_SS_6 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library lava1;
use lava1.components.all;

-- entity declaration --
entity TX_SS_6 is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "6";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PLL_DLY  : string  := "0.0";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tsetup_TXD0_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD0_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD1_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD1_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD2_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD2_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD3_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD3_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD4_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD4_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD5_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD5_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tipd_REFCLK    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD0      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD1      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD2      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD3      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD4      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD5      :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      REFCLK            : in    STD_ULOGIC;
      TXD0              : in    STD_ULOGIC;
      TXD1              : in    STD_ULOGIC;
      TXD2              : in    STD_ULOGIC;
      TXD3              : in    STD_ULOGIC;
      TXD4              : in    STD_ULOGIC;
      TXD5              : in    STD_ULOGIC;
      SOUT              : out   STD_ULOGIC;
      SS_CLKOUT         : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of TX_SS_6 : entity is FALSE;
end TX_SS_6;


architecture VITAL of TX_SS_6 is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL REFCLK_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD0_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD1_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD2_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD3_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD4_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD5_ipd	 : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;
  SIGNAL clk_in_period : TIME ;
  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_2d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_2d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  SIGNAL inthsrecclk    : std_logic := '0';
  SIGNAL intrecclk      : std_logic := '0';

  SIGNAL data_out       : std_logic_vector(5 downto 0) := (others => '0');
  SIGNAL shift_buffer   : std_logic_vector(5 downto 0) := (others => '0');
  SIGNAL cnt            : std_logic_vector(3 downto 0) := (others => '0');

  signal sout1 : std_logic := '0'; --ct102804
  
  CONSTANT clockboost: real := real(str2int(mult)) / real(str2int(div));
  CONSTANT tpd: time := 1.0 ns * str2real(pll_dly);

BEGIN

   WireDelay : block
   begin
   VitalWireDelay (REFCLK_ipd, REFCLK, tipd_REFCLK);
   VitalWireDelay (TXD0_ipd, TXD0, tipd_TXD0);
   VitalWireDelay (TXD1_ipd, TXD1, tipd_TXD1);
   VitalWireDelay (TXD2_ipd, TXD2, tipd_TXD2);
   VitalWireDelay (TXD3_ipd, TXD3, tipd_TXD3);
   VitalWireDelay (TXD4_ipd, TXD4, tipd_TXD4);
   VitalWireDelay (TXD5_ipd, TXD5, tipd_TXD5);
   end block;

   VITALBehavior : process

        variable Tviol_TXD0_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD1_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD2_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD3_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD4_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD5_REFCLK_posedge     : std_ulogic  := '0';
        variable Tmkr_TXD0_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD1_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD2_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD3_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD4_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD5_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Violation                    : std_ulogic   := '0';
     begin
       if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD0_REFCLK_posedge,
          TimingData              => Tmkr_TXD0_REFCLK_posedge,
          TestSignal              => TXD0_ipd,
          TestSignalName          => "TXD0",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD0_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD0_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD0_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD0_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_6",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD1_REFCLK_posedge,
          TimingData              => Tmkr_TXD1_REFCLK_posedge,
          TestSignal              => TXD1_ipd,
          TestSignalName          => "TXD1",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD1_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD1_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD1_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD1_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_6",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD2_REFCLK_posedge,
          TimingData              => Tmkr_TXD2_REFCLK_posedge,
          TestSignal              => TXD2_ipd,
          TestSignalName          => "TXD2",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD2_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD2_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD2_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD2_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_6",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD3_REFCLK_posedge,
          TimingData              => Tmkr_TXD3_REFCLK_posedge,
          TestSignal              => TXD3_ipd,
          TestSignalName          => "TXD3",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD3_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD3_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD3_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD3_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_6",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD4_REFCLK_posedge,
          TimingData              => Tmkr_TXD4_REFCLK_posedge,
          TestSignal              => TXD4_ipd,
          TestSignalName          => "TXD4",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD4_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD4_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD4_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD4_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_6",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD5_REFCLK_posedge,
          TimingData              => Tmkr_TXD5_REFCLK_posedge,
          TestSignal              => TXD5_ipd,
          TestSignalName          => "TXD5",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD5_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD5_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD5_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD5_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_6",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
        end if;

    Violation := Tviol_TXD0_REFCLK_posedge or Tviol_TXD1_REFCLK_posedge or 
                 Tviol_TXD2_REFCLK_posedge or Tviol_TXD3_REFCLK_posedge or 
                 Tviol_TXD4_REFCLK_posedge or Tviol_TXD5_REFCLK_posedge;
   
    wait on TXD0_ipd, TXD1_ipd, TXD2_ipd, TXD3_ipd, TXD4_ipd, TXD5_ipd, REFCLK_ipd;

   end  process VITALBehavior;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     clklock_last_rising_edge <= NOW;
     IF clklock_rising_edge_count = 0 THEN	
	start_inclk <= REFCLK_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     END IF;
     END IF;
  
  --ct09010527466 WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='0');	 
  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='1'); 	
     IF clklock_rising_edge_count = 1 THEN	
       clklock_half_period <= (NOW - clklock_last_rising_edge)/(clockboost*2.0);

	--ct09010527466 clklock_half_period <= (NOW - clklock_last_rising_edge)/clockboost; 	
	--ct09010527466 clklock_last_falling_edge <= NOW;
     END IF;

  
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc THEN
        if(clockboost >1.0) then
	   FOR i IN 1 TO integer(2.0*clockboost) LOOP 	       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

    intrecclk <= REFCLK_ipd;


    CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not after clklock_half_period when clock_count > 0 else
                     CLK_OUT_sig_d_not;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_sig_2d <= CLK_OUT_sig_d after clklock_half_period; 
    CLK_OUT_sig_3d <= CLK_OUT_sig_2d after clklock_half_period + tpd;

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 
    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ; --ct102804
    CSLOCK <= CSLOCK_sig;
    inthsrecclk <= CLK_OUT_plus_delay;
    SS_CLKOUT <= intrecclk;

process (inthsrecclk)
begin
        if(inthsrecclk'event and inthsrecclk = '1') then
           if cnt = "0101" then
              cnt <= "0000";
            else
              cnt <= cnt + "0001";
           end if; 
        end if;
end process;


--data_out(0)  <= TXD0_ipd when cnt = "0101" else shift_buffer(1);
--data_out(1)  <= TXD1_ipd when cnt = "0101" else shift_buffer(2);
--data_out(2)  <= TXD2_ipd when cnt = "0101" else shift_buffer(3);
--data_out(3)  <= TXD3_ipd when cnt = "0101" else shift_buffer(4);
--data_out(4)  <= TXD4_ipd when cnt = "0101" else shift_buffer(5);
--data_out(5)  <= TXD5_ipd when cnt = "0101" else shift_buffer(0);

--process (inthsrecclk,data_out)
--begin
--        if(inthsrecclk'event and inthsrecclk='1') then
--          SOUT             <= data_out(0);
--          shift_buffer(1)  <= data_out(1);
--          shift_buffer(2)  <= data_out(2);
--          shift_buffer(3)  <= data_out(3);
--          shift_buffer(4)  <= data_out(4);
--          shift_buffer(5)  <= data_out(5);
--        end if;
--end process;

--ct102804
  process (inthsrecclk)
  begin
     if(inthsrecclk'event and inthsrecclk='1') then
        if ( cnt = "0000" ) then
           data_out <= TXD5_ipd & TXD4_ipd &
        			TXD3_ipd & TXD2_ipd & TXD1_ipd & TXD0_ipd;
        else 
           data_out(4 downto 0) <= data_out(5 downto 1);
           data_out(5) <= data_out(0);
        end if;
     end if;
  end process;
  
  process (inthsrecclk)
  begin
     if(inthsrecclk'event and inthsrecclk='1') then
        sout1<= data_out(0);
        SOUT <= sout1;
     end if;
  end process;
end VITAL;

configuration CFG_TX_SS_6_VITAL of TX_SS_6 is 
        for VITAL
        end for; 
end CFG_TX_SS_6_VITAL;

----- VITAL model for cell TX_SS_8 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library lava1;
use lava1.components.all;

-- entity declaration --
entity TX_SS_8 is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "8";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PLL_DLY  :  STRING  := "0.0";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tsetup_TXD0_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD0_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD1_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD1_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD2_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD2_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD3_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD3_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD4_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD4_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD5_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD5_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD6_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD6_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD7_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD7_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tipd_REFCLK    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD0      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD1      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD2      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD3      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD4      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD5      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD6      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD7      :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      REFCLK            : in    STD_ULOGIC;
      TXD0              : in    STD_ULOGIC;
      TXD1              : in    STD_ULOGIC;
      TXD2              : in    STD_ULOGIC;
      TXD3              : in    STD_ULOGIC;
      TXD4              : in    STD_ULOGIC;
      TXD5              : in    STD_ULOGIC;
      TXD6              : in    STD_ULOGIC;
      TXD7              : in    STD_ULOGIC;
      SOUT              : out   STD_ULOGIC;
      SS_CLKOUT         : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of TX_SS_8 : entity is FALSE;
end TX_SS_8;

architecture VITAL of TX_SS_8 is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL REFCLK_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD0_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD1_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD2_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD3_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD4_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD5_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD6_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD7_ipd	 : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;
  SIGNAL clk_in_period : TIME ;
  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_2d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_2d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  SIGNAL inthsrecclk    : std_logic := '0';
  SIGNAL intrecclk      : std_logic := '0';
  SIGNAL intrecclk_d    : std_logic := '0';
  SIGNAL intrecclk_d1   : std_logic := '0';
  SIGNAL intrecclk_d2   : std_logic := '0';

  SIGNAL data_out       : std_logic_vector(7 downto 0) := (others => '0');
  SIGNAL shift_buffer   : std_logic_vector(7 downto 0) := (others => '0');
  SIGNAL cnt            : std_logic_vector(3 downto 0) := (others => '0');

  signal sout1 : std_logic := '0'; --ct102804
  
  CONSTANT clockboost: real := real(str2int(mult)) / real(str2int(div));
  CONSTANT tpd: time := 1.0 ns * str2real(PLL_DLY);
  
BEGIN

   WireDelay : block
   begin
   VitalWireDelay (REFCLK_ipd, REFCLK, tipd_REFCLK);
   VitalWireDelay (TXD0_ipd, TXD0, tipd_TXD0);
   VitalWireDelay (TXD1_ipd, TXD1, tipd_TXD1);
   VitalWireDelay (TXD2_ipd, TXD2, tipd_TXD2);
   VitalWireDelay (TXD3_ipd, TXD3, tipd_TXD3);
   VitalWireDelay (TXD4_ipd, TXD4, tipd_TXD4);
   VitalWireDelay (TXD5_ipd, TXD5, tipd_TXD5);
   VitalWireDelay (TXD6_ipd, TXD6, tipd_TXD6);
   VitalWireDelay (TXD7_ipd, TXD7, tipd_TXD7);
   end block;

   VITALBehavior : process

        variable Tviol_TXD0_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD1_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD2_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD3_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD4_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD5_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD6_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD7_REFCLK_posedge     : std_ulogic  := '0';
        variable Tmkr_TXD0_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD1_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD2_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD3_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD4_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD5_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD6_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD7_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Violation                    : std_logic   := '0';
   begin
       if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD0_REFCLK_posedge,
          TimingData              => Tmkr_TXD0_REFCLK_posedge,
          TestSignal              => TXD0_ipd,
          TestSignalName          => "TXD0",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD0_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD0_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD0_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD0_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD1_REFCLK_posedge,
          TimingData              => Tmkr_TXD1_REFCLK_posedge,
          TestSignal              => TXD1_ipd,
          TestSignalName          => "TXD1",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD1_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD1_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD1_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD1_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD2_REFCLK_posedge,
          TimingData              => Tmkr_TXD2_REFCLK_posedge,
          TestSignal              => TXD2_ipd,
          TestSignalName          => "TXD2",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD2_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD2_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD2_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD2_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD3_REFCLK_posedge,
          TimingData              => Tmkr_TXD3_REFCLK_posedge,
          TestSignal              => TXD3_ipd,
          TestSignalName          => "TXD3",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD3_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD3_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD3_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD3_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD4_REFCLK_posedge,
          TimingData              => Tmkr_TXD4_REFCLK_posedge,
          TestSignal              => TXD4_ipd,
          TestSignalName          => "TXD4",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD4_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD4_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD4_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD4_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD5_REFCLK_posedge,
          TimingData              => Tmkr_TXD5_REFCLK_posedge,
          TestSignal              => TXD5_ipd,
          TestSignalName          => "TXD5",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD5_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD5_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD5_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD5_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD6_REFCLK_posedge,
          TimingData              => Tmkr_TXD6_REFCLK_posedge,
          TestSignal              => TXD6_ipd,
          TestSignalName          => "TXD6",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD6_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD6_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD6_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD6_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD7_REFCLK_posedge,
          TimingData              => Tmkr_TXD7_REFCLK_posedge,
          TestSignal              => TXD7_ipd,
          TestSignalName          => "TXD7",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD7_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD7_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD7_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD7_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_8",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);
       end if;

    Violation := Tviol_TXD0_REFCLK_posedge or Tviol_TXD1_REFCLK_posedge or 
                 Tviol_TXD2_REFCLK_posedge or Tviol_TXD3_REFCLK_posedge or 
                 Tviol_TXD4_REFCLK_posedge or Tviol_TXD5_REFCLK_posedge or 
                 Tviol_TXD6_REFCLK_posedge or Tviol_TXD7_REFCLK_posedge;

    wait on REFCLK_ipd, TXD0_ipd, TXD1_ipd, TXD2_ipd, TXD3_ipd, TXD4_ipd, TXD5_ipd, TXD6_ipd, TXD7_ipd;

   end  process VITALBehavior;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     clklock_last_rising_edge <= NOW;
     IF clklock_rising_edge_count = 0 THEN	
	start_inclk <= REFCLK_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     END IF;
     END IF;

  --ct09010527466 WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='0');	 
  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='1'); 	
     IF clklock_rising_edge_count = 1 THEN	
       clklock_half_period <= (NOW - clklock_last_rising_edge)/(clockboost*2.0);

	--ct09010527466 clklock_half_period <= (NOW - clklock_last_rising_edge)/clockboost; 	
	--ct09010527466 clklock_last_falling_edge <= NOW;
     END IF;
 
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc THEN
        if(clockboost >1.0) then
	   FOR i IN 1 TO integer(2.0*clockboost) LOOP 	       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

    intrecclk <= REFCLK_ipd;


    CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not after clklock_half_period when clock_count > 0 else
                     CLK_OUT_sig_d_not;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_sig_2d <= CLK_OUT_sig_d after clklock_half_period; 
    CLK_OUT_sig_3d <= CLK_OUT_sig_2d after clklock_half_period + tpd;

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    inthsrecclk <= CLK_OUT_plus_delay;
    
    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
                PLL_LOCK_minus ; --ct102804
    CSLOCK <= CSLOCK_sig;
    
    SS_CLKOUT   <= intrecclk;

process (inthsrecclk)
begin
        if(inthsrecclk'event and inthsrecclk = '1') then
           if cnt = "0111" then
              cnt <= "0000";
            else
              cnt <= cnt + "0001";
           end if; 
        end if;
end process;


--data_out(0)  <= TXD0_ipd when cnt = "0111" else shift_buffer(1);
--data_out(1)  <= TXD1_ipd when cnt = "0111" else shift_buffer(2);
--data_out(2)  <= TXD2_ipd when cnt = "0111" else shift_buffer(3);
--data_out(3)  <= TXD3_ipd when cnt = "0111" else shift_buffer(4);
--data_out(4)  <= TXD4_ipd when cnt = "0111" else shift_buffer(5);
--data_out(5)  <= TXD5_ipd when cnt = "0111" else shift_buffer(6);
--data_out(6)  <= TXD6_ipd when cnt = "0111" else shift_buffer(7);
--data_out(7)  <= TXD7_ipd when cnt = "0111" else shift_buffer(0);

--process (inthsrecclk,data_out)
--begin
--        if(inthsrecclk'event and inthsrecclk='1') then
--          SOUT             <= data_out(0);
--          shift_buffer(1)  <= data_out(1);
--          shift_buffer(2)  <= data_out(2);
--          shift_buffer(3)  <= data_out(3);
--          shift_buffer(4)  <= data_out(4);
--          shift_buffer(5)  <= data_out(5);
--          shift_buffer(6)  <= data_out(6);
--          shift_buffer(7)  <= data_out(7);
--        end if;
--end process;

--ct102804
  process (inthsrecclk)
  begin
     if(inthsrecclk'event and inthsrecclk='1') then
        if ( cnt = "0000" ) then
           data_out <= TXD7_ipd & TXD6_ipd & TXD5_ipd & TXD4_ipd &
        			TXD3_ipd & TXD2_ipd & TXD1_ipd & TXD0_ipd;
        else 
           data_out(6 downto 0) <= data_out(7 downto 1);
           data_out(7) <= data_out(0);
        end if;
     end if;
  end process;
  
  process (inthsrecclk)
  begin
     if(inthsrecclk'event and inthsrecclk='1') then
        sout1<= data_out(0);
        SOUT <= sout1;
     end if;
  end process;
  
end VITAL;

configuration CFG_TX_SS_8_VITAL of TX_SS_8 is 
        for VITAL
        end for; 
end CFG_TX_SS_8_VITAL;

----- VITAL model for cell TX_SS_10 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
library IEEE;
use IEEE.VITAL_Timing.all;
library lava1;
use lava1.components.all;

-- entity declaration --
entity TX_SS_10 is
   generic(
      IN_FREQ  : string  := "100.0";
      MULT     : string  := "10";
      DIV      : string  := "1";
      LOCK_CYC : integer := 2;
      PLL_DLY  :  STRING  := "0.0";
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tsetup_TXD0_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD0_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD1_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD1_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD2_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD2_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD3_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD3_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD4_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD4_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD5_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD5_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD6_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD6_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD7_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD7_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD8_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD8_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tsetup_TXD9_REFCLK_noedge_posedge      :	VitalDelayType   := 0.1 ns;
      thold_TXD9_REFCLK_noedge_posedge       :	VitalDelayType   := 0.0 ns;
      tipd_REFCLK    :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD0      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD1      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD2      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD3      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD4      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD5      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD6      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD7      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD8      :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_TXD9      :	VitalDelayType01 := (0.000 ns, 0.000 ns));
   port(
      REFCLK            : in    STD_ULOGIC;
      TXD0              : in    STD_ULOGIC;
      TXD1              : in    STD_ULOGIC;
      TXD2              : in    STD_ULOGIC;
      TXD3              : in    STD_ULOGIC;
      TXD4              : in    STD_ULOGIC;
      TXD5              : in    STD_ULOGIC;
      TXD6              : in    STD_ULOGIC;
      TXD7              : in    STD_ULOGIC;
      TXD8              : in    STD_ULOGIC;
      TXD9              : in    STD_ULOGIC;
      SOUT              : out   STD_ULOGIC;
      SS_CLKOUT         : out   STD_ULOGIC;
      CSLOCK            : out   STD_ULOGIC);
attribute VITAL_LEVEL0 of TX_SS_10 : entity is FALSE;
end TX_SS_10;

architecture VITAL of TX_SS_10 is
  attribute VITAL_LEVEL1 of VITAL : architecture is FALSE;

  SIGNAL REFCLK_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD0_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD1_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD2_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD3_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD4_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD5_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD6_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD7_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD8_ipd	 : STD_ULOGIC := 'X';
  SIGNAL TXD9_ipd	 : STD_ULOGIC := 'X';

  CONSTANT input_frequency : REAL := str2real(in_freq);

  SIGNAL clklock_half_period : TIME :=100 ns;
  SIGNAL start_inclk : STD_LOGIC ;
  SIGNAL CSLOCK_sig  : STD_LOGIC ;
  SIGNAL clklock_rising_edge_count : INTEGER := 0 ;
  SIGNAL clklock_last_rising_edge : TIME ;
  SIGNAL clklock_last_falling_edge : TIME ;
  SIGNAL clk_in_period : TIME ;
  SIGNAL clock_count  : INTEGER := -1 ;
  SIGNAL clklock_lock : BOOLEAN := TRUE;
  SIGNAL CLK_OUT_sig_d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_not  : std_logic := '0';
  SIGNAL CLK_OUT_sig_2d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_3d  : std_logic := '0';
  SIGNAL CLK_OUT_sig_d_start  : std_logic := '0';
  SIGNAL CLK_OUT_plus_delay : std_logic := '0';
  SIGNAL SEC_OUT_sig_d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_not  : std_logic := '0';
  SIGNAL SEC_OUT_sig_2d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_3d  : std_logic := '0';
  SIGNAL SEC_OUT_sig_d_start  : std_logic := '0';
  SIGNAL SEC_OUT_plus_delay : std_logic := '0';
  SIGNAL CLK_OUT_sig1 : std_logic := '0';
  SIGNAL PLL_LOCK_plus : std_logic := '0';
  SIGNAL PLL_LOCK_minus : std_logic := '0';

  SIGNAL inthsrecclk    : std_logic := '0';
  SIGNAL intrecclk      : std_logic := '0';
  SIGNAL intrecclk_d    : std_logic := '0';
  SIGNAL intrecclk_d1   : std_logic := '0';
  SIGNAL intrecclk_d2   : std_logic := '0';

  SIGNAL data_out       : std_logic_vector(9 downto 0) := (others => '0');
  SIGNAL shift_buffer   : std_logic_vector(9 downto 0) := (others => '0');
  SIGNAL cnt            : std_logic_vector(3 downto 0) := (others => '0');
  signal sout1 : std_logic := '0'; --ct102804
  CONSTANT clockboost: real := real(str2int(mult)) / real(str2int(div));
  CONSTANT tpd: time := 1.0 ns * str2real(PLL_DLY);

BEGIN

   WireDelay : block
   begin
   VitalWireDelay (REFCLK_ipd, REFCLK, tipd_REFCLK);
   VitalWireDelay (TXD0_ipd, TXD0, tipd_TXD0);
   VitalWireDelay (TXD1_ipd, TXD1, tipd_TXD1);
   VitalWireDelay (TXD2_ipd, TXD2, tipd_TXD2);
   VitalWireDelay (TXD3_ipd, TXD3, tipd_TXD3);
   VitalWireDelay (TXD4_ipd, TXD4, tipd_TXD4);
   VitalWireDelay (TXD5_ipd, TXD5, tipd_TXD5);
   VitalWireDelay (TXD6_ipd, TXD6, tipd_TXD6);
   VitalWireDelay (TXD7_ipd, TXD7, tipd_TXD7);
   VitalWireDelay (TXD8_ipd, TXD8, tipd_TXD8);
   VitalWireDelay (TXD9_ipd, TXD9, tipd_TXD9);
   end block;

   VITALBehavior : process

        variable Tviol_TXD0_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD1_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD2_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD3_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD4_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD5_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD6_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD7_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD8_REFCLK_posedge     : std_ulogic  := '0';
        variable Tviol_TXD9_REFCLK_posedge     : std_ulogic  := '0';
        variable Tmkr_TXD0_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD1_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD2_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD3_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD4_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD5_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD6_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD7_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD8_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Tmkr_TXD9_REFCLK_posedge     : VitalTimingDataType := VitalTimingDataInit; 
        variable Violation                    : std_logic   := '0';
   begin
       if (TimingChecksOn) then

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD0_REFCLK_posedge,
          TimingData              => Tmkr_TXD0_REFCLK_posedge,
          TestSignal              => TXD0_ipd,
          TestSignalName          => "TXD0",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD0_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD0_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD0_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD0_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_10",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD1_REFCLK_posedge,
          TimingData              => Tmkr_TXD1_REFCLK_posedge,
          TestSignal              => TXD1_ipd,
          TestSignalName          => "TXD1",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD1_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD1_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD1_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD1_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_10",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD2_REFCLK_posedge,
          TimingData              => Tmkr_TXD2_REFCLK_posedge,
          TestSignal              => TXD2_ipd,
          TestSignalName          => "TXD2",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD2_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD2_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD2_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD2_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_10",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD3_REFCLK_posedge,
          TimingData              => Tmkr_TXD3_REFCLK_posedge,
          TestSignal              => TXD3_ipd,
          TestSignalName          => "TXD3",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD3_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD3_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD3_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD3_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_10",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD4_REFCLK_posedge,
          TimingData              => Tmkr_TXD4_REFCLK_posedge,
          TestSignal              => TXD4_ipd,
          TestSignalName          => "TXD4",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD4_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD4_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD4_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD4_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_10",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD5_REFCLK_posedge,
          TimingData              => Tmkr_TXD5_REFCLK_posedge,
          TestSignal              => TXD5_ipd,
          TestSignalName          => "TXD5",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD5_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD5_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD5_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD5_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_10",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD6_REFCLK_posedge,
          TimingData              => Tmkr_TXD6_REFCLK_posedge,
          TestSignal              => TXD6_ipd,
          TestSignalName          => "TXD6",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD6_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD6_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD6_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD6_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_10",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD7_REFCLK_posedge,
          TimingData              => Tmkr_TXD7_REFCLK_posedge,
          TestSignal              => TXD7_ipd,
          TestSignalName          => "TXD7",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD7_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD7_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD7_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD7_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_10",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD8_REFCLK_posedge,
          TimingData              => Tmkr_TXD8_REFCLK_posedge,
          TestSignal              => TXD8_ipd,
          TestSignalName          => "TXD8",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD8_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD8_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD8_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD8_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_10",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

         VitalSetupHoldCheck (
          Violation               => Tviol_TXD9_REFCLK_posedge,
          TimingData              => Tmkr_TXD9_REFCLK_posedge,
          TestSignal              => TXD9_ipd,
          TestSignalName          => "TXD9",
          TestDelay               => 0 ns,
          RefSignal               => REFCLK_ipd,
          RefSignalName           => "REFCLK",
          RefDelay                => 0 ns,
          SetupHigh               => tsetup_TXD9_REFCLK_noedge_posedge,
          SetupLow                => tsetup_TXD9_REFCLK_noedge_posedge,
          HoldLow                 => thold_TXD9_REFCLK_noedge_posedge,
          HoldHigh                => thold_TXD9_REFCLK_noedge_posedge,
          CheckEnabled            => TRUE, 
          RefTransition           => 'R',
          HeaderMsg               => InstancePath & "/TX_SS_10",
          Xon                     => Xon,
          MsgOn                   => MsgOn,
          MsgSeverity             => WARNING);

       end if;

    Violation := Tviol_TXD0_REFCLK_posedge or Tviol_TXD1_REFCLK_posedge or 
                 Tviol_TXD2_REFCLK_posedge or Tviol_TXD3_REFCLK_posedge or 
                 Tviol_TXD4_REFCLK_posedge or Tviol_TXD5_REFCLK_posedge or 
                 Tviol_TXD6_REFCLK_posedge or Tviol_TXD7_REFCLK_posedge or
                 Tviol_TXD8_REFCLK_posedge or Tviol_TXD9_REFCLK_posedge;

    wait on REFCLK_ipd, TXD0_ipd, TXD1_ipd, TXD2_ipd, TXD3_ipd, TXD4_ipd, TXD5_ipd, TXD6_ipd, TXD7_ipd, TXD8_ipd, TXD9_ipd;

   end  process VITALBehavior;

edge_count: PROCESS
     VARIABLE input_cycle : REAL;
     VARIABLE real_cycle : REAL;
BEGIN

  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='1');	   
     clklock_rising_edge_count <= clklock_rising_edge_count +1;
     clklock_last_rising_edge <= NOW;
     IF clklock_rising_edge_count = 0 THEN	
	start_inclk <= REFCLK_ipd;
     ELSE
     IF clklock_rising_edge_count = 1 THEN
	input_cycle := 1000.0 / input_frequency;
	real_cycle := REAL( (NOW - clklock_last_rising_edge) / 1 ns);
	IF ( real_cycle < 0.9 * input_cycle OR
	     real_cycle > 1.1 * input_cycle ) THEN
  	      	ASSERT TRUE 
  		REPORT " Input_Frequency Violation "
  		SEVERITY WARNING;
  		clklock_lock <= FALSE;
        END IF;
     END IF;
     END IF;
  
  --ct09010527466 WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='0');	 
  WAIT UNTIL (REFCLK_ipd'EVENT AND REFCLK_ipd='1'); 	
     IF clklock_rising_edge_count = 1 THEN	
       clklock_half_period <= (NOW - clklock_last_rising_edge)/(clockboost*2.0);

	--ct09010527466 clklock_half_period <= (NOW - clklock_last_rising_edge)/clockboost; 	
	--ct09010527466 clklock_last_falling_edge <= NOW;
     END IF;
 
END PROCESS edge_count;

toggle: PROCESS
BEGIN

     WAIT ON clklock_rising_edge_count;
     IF clklock_rising_edge_count > lock_cyc THEN
        if(clockboost >1.0) then
	   FOR i IN 1 TO integer(2.0*clockboost) LOOP 	       
		clock_count <= clock_count + 1;
		WAIT FOR clklock_half_period;
	   END LOOP;
        else  
		clock_count <= clock_count + 1;
		WAIT FOR (clklock_half_period);
        end if;
     ELSE
	clock_count <= 0;
     END IF;
END PROCESS toggle;


gen_pll_lock_plus:process
begin
     wait until (clock_count=1);
          PLL_LOCK_plus <= '1';
end process;

gen_pll_lock_minus:process
begin
     wait until (clock_count=3);
          PLL_LOCK_minus <= '1';
end process;

process
begin 
    wait until clock_count = 1;
    CLK_OUT_sig_d_start <='1';
    SEC_OUT_sig_d_start <='1';
end process;

    intrecclk <= REFCLK_ipd;


    CLK_OUT_sig_d_not <= not CLK_OUT_sig_d_not after clklock_half_period when clock_count > 0 else
                     CLK_OUT_sig_d_not;

    CLK_OUT_sig_d <= CLK_OUT_sig_d_start and not CLK_OUT_sig_d_not; 

    CLK_OUT_sig_2d <= CLK_OUT_sig_d after clklock_half_period; 
    CLK_OUT_sig_3d <= CLK_OUT_sig_2d after clklock_half_period + tpd;

    CLK_OUT_plus_delay <= CLK_OUT_sig_d after tpd when tpd >= 0 ns else
                          CLK_OUT_sig_3d; 

    inthsrecclk <= CLK_OUT_plus_delay;
    CSLOCK_sig <= PLL_LOCK_plus when tpd >= 0 ns else
             PLL_LOCK_minus ; --ct102804
    CSLOCK <= CSLOCK_sig;

    SS_CLKOUT   <= intrecclk;

process (inthsrecclk)
begin
        if(inthsrecclk'event and inthsrecclk = '1') then
           if cnt = "1001" then
              cnt <= "0000";
            else
              cnt <= cnt + "0001";
           end if; 
        end if;
end process;


--data_out(0)  <= TXD0_ipd when cnt = "1001" else shift_buffer(1);
--data_out(1)  <= TXD1_ipd when cnt = "1001" else shift_buffer(2);
--data_out(2)  <= TXD2_ipd when cnt = "1001" else shift_buffer(3);
--data_out(3)  <= TXD3_ipd when cnt = "1001" else shift_buffer(4);
--data_out(4)  <= TXD4_ipd when cnt = "1001" else shift_buffer(5);
--data_out(5)  <= TXD5_ipd when cnt = "1001" else shift_buffer(6);
--data_out(6)  <= TXD6_ipd when cnt = "1001" else shift_buffer(7);
--data_out(7)  <= TXD7_ipd when cnt = "1001" else shift_buffer(8);
--data_out(8)  <= TXD8_ipd when cnt = "1001" else shift_buffer(9);
--data_out(9)  <= TXD9_ipd when cnt = "1001" else shift_buffer(0);

--process (inthsrecclk,data_out)
--begin
--        if(inthsrecclk'event and inthsrecclk='1') then
--          SOUT             <= data_out(0);
--          shift_buffer(1)  <= data_out(1);
--          shift_buffer(2)  <= data_out(2);
--          shift_buffer(3)  <= data_out(3);
--          shift_buffer(4)  <= data_out(4);
--          shift_buffer(5)  <= data_out(5);
--          shift_buffer(6)  <= data_out(6);
--          shift_buffer(7)  <= data_out(7);
--          shift_buffer(8)  <= data_out(8);
--          shift_buffer(9)  <= data_out(9);
--        end if;
--end process;

  --ct102804
  process (inthsrecclk)
  begin
     if(inthsrecclk'event and inthsrecclk='1') then
        if ( cnt = "0000" ) then
           data_out <= TXD9_ipd & TXD8_ipd & TXD7_ipd & TXD6_ipd & TXD5_ipd &
        			TXD4_ipd & TXD3_ipd & TXD2_ipd & TXD1_ipd & TXD0_ipd;
        else 
           data_out(8 downto 0) <= data_out(9 downto 1);
           data_out(9) <= data_out(0);
        end if;
     end if;
  end process;
  
  process (inthsrecclk)
  begin
     if(inthsrecclk'event and inthsrecclk='1') then
        sout1<= data_out(0);
        SOUT <= sout1;
     end if;
  end process;

end VITAL;

configuration CFG_TX_SS_10_VITAL of TX_SS_10 is 
        for VITAL
        end for; 
end CFG_TX_SS_10_VITAL;


-- ************************************************************************
--
--  Block Memory: Behavioral Model
--  The kernel of other RAM applications  
-- ************************************************************************
--
--  Filename:  SC_BLOCK_RAM.vhd
--  Description: 16K X 1  BRAM behavioral model. 
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************

library std;
use std.textio.all;

library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;


-- ************************************************************************
-- Entity definition  
-- "generic" members 
-- ************************************************************************

entity SC_BRAM_16K is

  generic (

	 DEVICE_FAMILY : string  := "LAVA1";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;       
	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := ""

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 

end SC_BRAM_16K;

-- ************************************************************************
-- Architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_BRAM_16K is

procedure READ_MEM_INIT_FILE(
                              f_name : IN    STRING;
                              v_MEM  : OUT   STD_LOGIC_VECTOR
                             ) IS

    file     f_INIT_FILE   : TEXT is MEM_INIT_FILE;
    variable v_WORD        : line;
    variable v_GOODFLAG    : boolean;
    variable v_WORD_BIT    : string (WDATA_WIDTH_A downto 1) ;
    variable v_CHAR        : character;
    variable v_OFFSET      : integer := 0;
    variable v_LINE        : integer := 0;

    begin      
      
      while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop

      readline(f_INIT_FILE, v_WORD);
      read(v_WORD, v_WORD_BIT, v_GOODFLAG);

      for k in 0 to WDATA_WIDTH_A - 1 loop
        v_CHAR := v_WORD_BIT (k + 1);
        if (v_CHAR = '1') then
          v_MEM(v_OFFSET + k) := '1';

	elsif (v_CHAR = '0') then
          v_MEM(v_OFFSET + k) := '0';

--	else 
--          v_MEM(v_OFFSET + k) := 'X';

	end if;
      end loop;

      v_LINE := v_LINE + 1;
      v_OFFSET := v_OFFSET + WDATA_WIDTH_A;

    end loop;

  end READ_MEM_INIT_FILE;

--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Address (
    IN_ADDR : in std_logic_vector
 ) return boolean is

    variable v_Valid_Flag : boolean := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Address;

--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------

--------- Local signals used to propagate input wire delay ---------------

signal WADA_node   : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node    : std_logic := 'X';
signal WDA_node    : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node   : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node    : std_logic := 'X';
signal RDA_node    : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');

signal WADB_node   : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node    : std_logic := 'X';
signal WDB_node    : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node   : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node    : std_logic := 'X';
signal RDB_node    : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');

-- architecture
begin 

 WADA_node <= WADA;
 WEA_node  <= WEA;
 WDA_node  <= WDA;
 RADA_node <= RADA;
 REA_node  <= REA;
 RDA       <= RDA_node;
 
 WADB_node <= WADB;
 WEB_node  <= WEB;
 WDB_node  <= WDB;
 RADB_node <= RADB;
 REB_node  <= REB;
 RDB       <= RDB_node;

-----------------------------------------
--------- Behavior process  -------------
-----------------------------------------


  KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)


--TSPEC: A note about sram initial values and rom mode: 
--       If the user does not provide any values, ... default 0 
--       for all ram locations in JECED
    variable v_MEM         : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '1' ); 
    variable v_INI_DONE    : boolean := FALSE;
    variable v_WADDR_A     : integer;
    variable v_RADDR_A     : integer;
    variable v_WADDR_B     : integer;
    variable v_RADDR_B     : integer;

    variable v_WADDRA_Valid_Flag : boolean := TRUE;
    variable v_WADDRB_Valid_Flag : boolean := TRUE;
    variable v_RADDRA_Valid_Flag : boolean := TRUE;
    variable v_RADDRB_Valid_Flag : boolean := TRUE;

  begin -- Process
   
    if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
	READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
	v_INI_DONE := TRUE;
    end if;

  -- Address Check    
    v_WADDRA_Valid_Flag := Valid_Address(WADA_node);	
    v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
    v_RADDRA_Valid_Flag := Valid_Address(RADA_node);	
    v_RADDRB_Valid_Flag := Valid_Address(RADB_node);

    if ( v_WADDRA_Valid_Flag = TRUE ) then
 	v_WADDR_A := CONV_INTEGER(WADA_node);
--    else	
--      assert (Now = 0 ps) 
--        report "Write AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_WADDRB_Valid_Flag = TRUE ) then
      v_WADDR_B := CONV_INTEGER(WADB_node);
    else
--      assert (Now = 0 ps)
--        report "Write AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRA_Valid_Flag = TRUE ) then
      v_RADDR_A := CONV_INTEGER(RADA_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRB_Valid_Flag = TRUE ) then
      v_RADDR_B := CONV_INTEGER(RADB_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

  -- CHECK Operation
    if (WEA = '1' and WEB = '1' and 
         not( 
          (v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B) 
                         or
          (v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
         )
        ) then
      assert false
        report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
        severity warning;
    end if;  

  -- MEM Operation	
    if (WEA_node = '1') then
        v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
    end if;

    if (WEB_node = '1') then
        v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
    end if;

    if (REA_node = '1') then
       RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
--    else
--       RDA_node <= ( others => 'X');
    end if;
    
    if (REB_node = '1') then
       RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
--    else
--       RDB_node <= ( others => 'X');
    end if;
    
  end process KERNEL_BEHAV;
    
end LATTICE_BEHAV;

library std;
use std.textio.all;

library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;


-- ************************************************************************
-- Entity definition  
-- "generic" members 
-- ************************************************************************

entity SC_BRAM_PDP_16K_L is

  generic (

	 DEVICE_FAMILY : string  := "LAVA1";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 262144;       
	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := ""

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 

end SC_BRAM_PDP_16K_L;

-- ************************************************************************
-- Architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_BRAM_PDP_16K_L is

procedure READ_MEM_INIT_FILE(
                              f_name : IN    STRING;
                              v_MEM  : OUT   STD_LOGIC_VECTOR
                             ) IS

    file     f_INIT_FILE   : TEXT is MEM_INIT_FILE;
    variable v_WORD        : line;
    variable v_GOODFLAG    : boolean;
    variable v_WORD_BIT    : string (WDATA_WIDTH_A downto 1) ;
    variable v_CHAR        : character;
    variable v_OFFSET      : integer := 0;
    variable v_LINE        : integer := 0;

    begin      
      
      while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop

      readline(f_INIT_FILE, v_WORD);
      read(v_WORD, v_WORD_BIT, v_GOODFLAG);

      for k in 0 to WDATA_WIDTH_A - 1 loop
        v_CHAR := v_WORD_BIT (k + 1);
        if (v_CHAR = '1') then
          v_MEM(v_OFFSET + k) := '1';

	elsif (v_CHAR = '0') then
          v_MEM(v_OFFSET + k) := '0';

--	else 
--          v_MEM(v_OFFSET + k) := 'X';

	end if;
      end loop;

      v_LINE := v_LINE + 1;
      v_OFFSET := v_OFFSET + WDATA_WIDTH_A;

    end loop;

  end READ_MEM_INIT_FILE;


--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Address (
    IN_ADDR : in std_logic_vector
 ) return boolean is

    variable v_Valid_Flag : boolean := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Address;

--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------

--------- Local signals used to propagate input wire delay ---------------

signal WADA_node   : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node    : std_logic := 'X';
signal WDA_node    : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node   : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node    : std_logic := 'X';
signal RDA_node    : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');

signal WADB_node   : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node    : std_logic := 'X';
signal WDB_node    : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node   : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node    : std_logic := 'X';
signal RDB_node    : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');

-- architecture
begin 

 WADA_node <= WADA;
 WEA_node  <= WEA;
 WDA_node  <= WDA;
 RADA_node <= RADA;
 REA_node  <= REA;
 RDA       <= RDA_node;
 
 WADB_node <= WADB;
 WEB_node  <= WEB;
 WDB_node  <= WDB;
 RADB_node <= RADB;
 REB_node  <= REB;
 RDB       <= RDB_node;

-----------------------------------------
--------- Behavior process  -------------
-----------------------------------------

  KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)


    variable v_MEM         : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '0' );  

    variable v_INI_DONE    : boolean := FALSE;
    variable v_WADDR_A     : integer;
    variable v_RADDR_A     : integer;
    variable v_WADDR_B     : integer;
    variable v_RADDR_B     : integer;

    variable v_WADDRA_Valid_Flag : boolean := TRUE;
    variable v_WADDRB_Valid_Flag : boolean := TRUE;
    variable v_RADDRA_Valid_Flag : boolean := TRUE;
    variable v_RADDRB_Valid_Flag : boolean := TRUE;

  begin -- Process
   
    if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
	READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
	v_INI_DONE := TRUE;
    end if;

  -- Address Check    
    v_WADDRA_Valid_Flag := Valid_Address(WADA_node);	
    v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
    v_RADDRA_Valid_Flag := Valid_Address(RADA_node);	
    v_RADDRB_Valid_Flag := Valid_Address(RADB_node);

    if ( v_WADDRA_Valid_Flag = TRUE ) then
 	v_WADDR_A := CONV_INTEGER(WADA_node);
--    else	
--      assert (Now = 0 ps) 
--        report "Write AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_WADDRB_Valid_Flag = TRUE ) then
      v_WADDR_B := CONV_INTEGER(WADB_node);
--    else
--      assert (Now = 0 ps)
--        report "Write AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRA_Valid_Flag = TRUE ) then
      v_RADDR_A := CONV_INTEGER(RADA_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRB_Valid_Flag = TRUE ) then
      v_RADDR_B := CONV_INTEGER(RADB_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

  -- CHECK Operation
    if (WEA = '1' and WEB = '1' and 
         not( 
          (v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B) 
                         or
          (v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
         )
        ) then
      assert false
        report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
        severity warning;
    end if;  

  -- MEM Operation	
    if (WEA_node = '1') then
        v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
    end if;

    if (WEB_node = '1') then
        v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
    end if;

    if (REA_node = '1') then
       RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
--    else
--       RDA_node <= ( others => 'X');
    end if;
    
    if (REB_node = '1') then
       RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
--    else
--       RDB_node <= ( others => 'X');
    end if;
    
  end process KERNEL_BEHAV;
    
end LATTICE_BEHAV;




-- ************************************************************************
--
--  Block Memory: Behavioral Model
--  The kernel of other RAM applications  
-- ************************************************************************
--
--  Filename:  SC_BLOCK_RAM.vhd
--  Description: 16K X 1  BRAM behavioral model. 
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************
library std;
use std.textio.all;

library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;


-- ************************************************************************
-- Entity definition  
-- "generic" members 
-- ************************************************************************

entity SC_BRAM_16K_L is

  generic (

	 DEVICE_FAMILY : string  := "LAVA1";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 262144;       
	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := ""

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 

end SC_BRAM_16K_L;

-- ************************************************************************
-- Architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_BRAM_16K_L is

procedure READ_MEM_INIT_FILE(
                              f_name : IN    STRING;
                              v_MEM  : OUT   STD_LOGIC_VECTOR
                             ) IS

    file     f_INIT_FILE   : TEXT is MEM_INIT_FILE;
    variable v_WORD        : line;
    variable v_GOODFLAG    : boolean;
    variable v_WORD_BIT    : string (WDATA_WIDTH_A downto 1) ;
    variable v_CHAR        : character;
    variable v_OFFSET      : integer := 0;
    variable v_LINE        : integer := 0;

    begin      
      
      while ( not(endfile(f_INIT_FILE)) and (v_LINE < 2**WADDR_WIDTH_A)) loop

      readline(f_INIT_FILE, v_WORD);
      read(v_WORD, v_WORD_BIT, v_GOODFLAG);

      for k in 0 to WDATA_WIDTH_A - 1 loop
        v_CHAR := v_WORD_BIT (k + 1);
        if (v_CHAR = '1') then
          v_MEM(v_OFFSET + k) := '1';

	elsif (v_CHAR = '0') then
          v_MEM(v_OFFSET + k) := '0';

--	else 
--          v_MEM(v_OFFSET + k) := 'X';

	end if;
      end loop;

      v_LINE := v_LINE + 1;
      v_OFFSET := v_OFFSET + WDATA_WIDTH_A;

    end loop;

  end READ_MEM_INIT_FILE;

--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Address (
    IN_ADDR : in std_logic_vector
 ) return boolean is

    variable v_Valid_Flag : boolean := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Address;

--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------

--------- Local signals used to propagate input wire delay ---------------

signal WADA_node   : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node    : std_logic := 'X';
signal WDA_node    : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node   : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node    : std_logic := 'X';
signal RDA_node    : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');

signal WADB_node   : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node    : std_logic := 'X';
signal WDB_node    : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node   : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node    : std_logic := 'X';
signal RDB_node    : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');

-- architecture
begin 

 WADA_node <= WADA;
 WEA_node  <= WEA;
 WDA_node  <= WDA;
 RADA_node <= RADA;
 REA_node  <= REA;
 RDA       <= RDA_node;
 
 WADB_node <= WADB;
 WEB_node  <= WEB;
 WDB_node  <= WDB;
 RADB_node <= RADB;
 REB_node  <= REB;
 RDB       <= RDB_node;

-----------------------------------------
--------- Behavior process  -------------
-----------------------------------------

  KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)

    variable v_MEM         : std_logic_vector(ARRAY_SIZE - 1 downto 0) := ( others => '1' ); 
    variable v_INI_DONE    : boolean := FALSE;
    variable v_WADDR_A     : integer;
    variable v_RADDR_A     : integer;
    variable v_WADDR_B     : integer;
    variable v_RADDR_B     : integer;

    variable v_WADDRA_Valid_Flag : boolean := TRUE;
    variable v_WADDRB_Valid_Flag : boolean := TRUE;
    variable v_RADDRA_Valid_Flag : boolean := TRUE;
    variable v_RADDRB_Valid_Flag : boolean := TRUE;

  begin -- Process
   
    if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
	READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
	v_INI_DONE := TRUE;
    end if;

  -- Address Check    
    v_WADDRA_Valid_Flag := Valid_Address(WADA_node);	
    v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
    v_RADDRA_Valid_Flag := Valid_Address(RADA_node);	
    v_RADDRB_Valid_Flag := Valid_Address(RADB_node);

    if ( v_WADDRA_Valid_Flag = TRUE ) then
 	v_WADDR_A := CONV_INTEGER(WADA_node);
--    else	
--      assert (Now = 0 ps) 
--        report "Write AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_WADDRB_Valid_Flag = TRUE ) then
      v_WADDR_B := CONV_INTEGER(WADB_node);
--    else
--      assert (Now = 0 ps)
--        report "Write AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRA_Valid_Flag = TRUE ) then
      v_RADDR_A := CONV_INTEGER(RADA_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRB_Valid_Flag = TRUE ) then
      v_RADDR_B := CONV_INTEGER(RADB_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

  -- CHECK Operation
    if (WEA = '1' and WEB = '1' and 
         not( 
          (v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B) 
                         or
          (v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
         )
        ) then
      assert false
        report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
        severity warning;
    end if;  

  -- MEM Operation	
    if (WEA_node = '1') then
        v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
    end if;

    if (WEB_node = '1') then
        v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
    end if;

    if (REA_node = '1') then
       RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
--    else
--       RDA_node <= ( others => 'X');
    end if;
    
    if (REB_node = '1') then
       RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
--    else
--       RDB_node <= ( others => 'X');
    end if;
    
  end process KERNEL_BEHAV;
    
end LATTICE_BEHAV;


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

library lava1;
use lava1.components.all;

-- ************************************************************************
--  Entity definition  
--  Draft "generic" members 
-- ************************************************************************

entity SC_DPRAM_16K_L is

  generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        ADDR_WIDTH_A     : integer := 13;
        DATA_WIDTH_A     : integer := 2;
        ADDR_WIDTH_B     : integer := 14;
        DATA_WIDTH_B     : integer := 1;
        MEM_INIT_FLAG  : integer := 1;  
        ARRAY_SIZE       : integer := 16384;
	MEM_INIT_FILE  : string  := "mem_init_file"

         );

  port (
        CENA : in  STD_LOGIC ;
        CLKA : in  STD_LOGIC ;
        WRA  : in  STD_LOGIC ;
        CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
        RSTA : in  STD_LOGIC ;
        DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
        ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
        DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

        CENB : in  STD_LOGIC ;
        CLKB : in  STD_LOGIC ;
        WRB  : in  STD_LOGIC ;
        CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
        RSTB : in  STD_LOGIC ;
        DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
        ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
        DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)

        ); 

end SC_DPRAM_16K_L ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_DPRAM_16K_L is

 component SC_BRAM_16K_L

  generic (
 	     DEVICE_FAMILY : string  := "LAVA1";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
    	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 -- Signal Declaration
 
 signal CENA_node :  STD_LOGIC := 'X';
 signal CLKA_node :  STD_LOGIC := 'X';
 signal WRA_node  :  STD_LOGIC := 'X';
 signal CSA_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RSTA_node :  STD_LOGIC := 'X';
 signal DIA_node  :  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
 signal ADA_node  :  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => '0');
 signal DOA_node  :  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');

 signal DIA_reg   :  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0) := (others => 'X');
 signal ADA_reg   :  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0) := (others => '0');
 signal ENA_reg   :  STD_LOGIC := 'X';
 signal RENA_reg  :  STD_LOGIC := '1';

 signal CENB_node :  STD_LOGIC := 'X';
 signal CLKB_node :  STD_LOGIC := 'X';
 signal WRB_node  :  STD_LOGIC := 'X';
 signal CSB_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RSTB_node :  STD_LOGIC := 'X';
 signal DIB_node  :  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
 signal ADB_node  :  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => '0');
 signal DOB_node  :  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');

 signal DIB_reg   :  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0) := (others => 'X');
 signal ADB_reg   :  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0) := (others => '0');
 signal ENB_reg   :  STD_LOGIC := 'X';
 signal RENB_reg  :  STD_LOGIC := '1';
 signal v_MEM     :  STD_LOGIC_VECTOR(ARRAY_SIZE - 1 downto 0) := ( others => '1' ); 
 signal v_ADA     :  INTEGER;
 signal v_ADB     :  INTEGER;
 signal AD_EQ     :  STD_LOGIC := '0';

-- architecture

 begin

  CENA_node <= CENA;
  CLKA_node <= CLKA;
  WRA_node  <= WRA;
  CSA_node  <= CSA;
  RSTA_node <= RSTA;
  DIA_node  <= DIA;
  ADA_node  <= ADA;
--  DOA       <= DOA_node; 

  CENB_node <= CENB;
  CLKB_node <= CLKB;
  WRB_node  <= WRB;
  CSB_node  <= CSB;
  RSTB_node <= RSTB;
  DIB_node  <= DIB;
  ADB_node  <= ADB;
--  DOB       <= DOB_node;
               
process(ADA_node, ADB_node)
begin
  if (Valid_Address(ADA_node) = TRUE) then
  v_ADA <= CONV_INTEGER(ADA_node);
  end if;

  if (Valid_Address(ADB_node) = TRUE) then
  v_ADB <= CONV_INTEGER(ADB_node);
  end if;
end process;

  -- Register Port A DI/ AD / Enable inputs


  register_A_inputs: process (CLKA_node, RSTA_node)
  begin
    if (RSTA_node = '1') then
        DIA_reg <= (others => '0');
        ADA_reg <= (others => '0');
        ENA_reg <= '0';
        RENA_reg <= '1'; 
    elsif (CLKA_node'event and CLKA_node = '1') then
      if (CENA_node = '1') then
        DIA_reg <= DIA_node;
        ADA_reg <= ADA_node;
        ENA_reg <= WRA_node  and CSA_node(0) and CSA_node(1);
        RENA_reg <= '1'; 
      end if;
    end if;
  end process register_A_inputs;   

-- Register Port B DI/ AD / Enable inputs
  register_B_inputs: process (CLKB_node, RSTB_node)
  begin
    if (RSTB_node = '1') then
        DIB_reg <= (others => '0');
        ADB_reg <= (others => '0');
        ENB_reg <= '0';
        RENB_reg <= '1'; 
    elsif (CLKB_node'event and CLKB_node = '1') then
      if (CENB_node = '1') then
        DIB_reg <= DIB_node;
        ADB_reg <= ADB_node;
        ENB_reg <= WRB_node  and CSB_node(0) and CSB_node(1);
        RENB_reg <= '1'; 
      end if;
    end if;
  end process register_B_inputs; 

  write_MEM_A: process(DOA_node, DOB_node)
   begin
     if(ENA_reg = '1') then
       for i in 0 to DATA_WIDTH_A - 1 loop
         v_MEM(v_ADA*DATA_WIDTH_A+i) <= DOA_node(i);
       end loop;
     elsif(ENB_reg = '1') then
       for i in 0 to DATA_WIDTH_B - 1 loop
         v_MEM(v_ADB*DATA_WIDTH_B+i) <= DOB_node(i);
       end loop;
     end if;
   end process;

  compare_address: process(ADA, ADB)
    begin
      if (ADA = ADB) then
        AD_EQ <= '1';
      else
        AD_EQ <= '0';
      end if;
  end process;

  read_A_port: process(RSTA_node, RENA_reg, ENA_reg, ENB_reg, DOA_node, CLKA_node)
  begin
     if (RSTA_node = '1') then
        DOA <= (others => '0');
     elsif (CLKA_node = '1') then
          if (RENA_reg = '1' and ENA_reg = '1' and ENB_reg = '0') then
             DOA <= DOA_node;
          elsif (RENA_reg = '1' and ENA_reg = '0' and ENB_reg = '1' and AD_EQ = '0') then
             DOA <= DOA_node;
          elsif (RENA_reg = '1' and ENA_reg = '0' and ENB_reg = '1' and AD_EQ = '1') then
             for i in 0 to DATA_WIDTH_A - 1 loop
                 DOA(i) <= v_MEM(v_ADA*DATA_WIDTH_A+i);
             end loop;
          else
             DOA <= DOA_node;
          end if;
     end if;
  end process; 

  read_B_port: process(RSTB_node, RENB_reg, ENB_reg, ENA_reg, DOB_node, CLKB_node)
  begin
     if (RSTB_node = '1') then
        DOB <= (others => '0');
     elsif (CLKB_node = '1') then
          if (RENB_reg = '1' and ENB_reg = '1' and ENA_reg = '0') then
              DOB <= DOB_node;
          elsif (RENB_reg = '1' and ENB_reg = '0' and ENA_reg = '1' and AD_EQ = '0') then
              DOB <= DOB_node;
          elsif (RENB_reg = '1' and ENB_reg = '0' and ENA_reg = '1' and AD_EQ = '1') then
             for i in 0 to DATA_WIDTH_B - 1 loop
                DOB(i) <= v_MEM(v_ADB*DATA_WIDTH_B+i);
             end loop;
          else
             DOB <= DOB_node;
          end if;
     end if;
  end process; 

  -- BRAM instance for SPRAM 
  DPRAM_INST: SC_BRAM_16K_L

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => ADDR_WIDTH_A,
         RADDR_WIDTH_A  => ADDR_WIDTH_A,
         WADDR_WIDTH_B  => ADDR_WIDTH_B,
         RADDR_WIDTH_B  => ADDR_WIDTH_B,
         WDATA_WIDTH_A  => DATA_WIDTH_A,
         RDATA_WIDTH_A  => DATA_WIDTH_A,
         WDATA_WIDTH_B  => DATA_WIDTH_B,
         RDATA_WIDTH_B  => DATA_WIDTH_B,
         ARRAY_SIZE     => ARRAY_SIZE,
  	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
         WADA => ADA_reg,
         WEA  => ENA_reg,
         WDA  => DIA_reg,
         RADA => ADA_reg,
         REA  => RENA_reg,
         RDA  => DOA_node,
         
         WADB => ADB_reg,
         WEB  => ENB_reg,
         WDB  => DIB_reg,
         RADB => ADB_reg,
         REB  => RENB_reg,
         RDB  => DOB_node
      );

end LATTICE_BEHAV;

-- ************************************************************************
--
--  PseudoDPRAM: Behavioral Model
-- ************************************************************************
--
--  Filename:  SC_PDP_RAM.vhd
--  Description: Pseudo Dual Port BRAM behavioral model. 
--  History:
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

library lava1;
use lava1.components.all;

-- ************************************************************************
--  Entity definition  
--  Draft "generic" members 
-- ************************************************************************

entity SC_PDPRAM_16K_L is

  generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        WADDR_WIDTH    : integer := 13;
        WDATA_WIDTH    : integer := 2;
        RADDR_WIDTH    : integer := 13;
        RDATA_WIDTH    : integer := 2;
        MEM_INIT_FLAG  : integer := 1;  
        ARRAY_SIZE     : integer := 16384;
	MEM_INIT_FILE  : string  := "mem_init_file"

        );

  port (
        WCEN : in  STD_LOGIC ;
        WCLK : in  STD_LOGIC ;
        WE   : in  STD_LOGIC ;
        WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
        RCLK : in  STD_LOGIC;
        RCEN : in  STD_LOGIC;
        RST  : in  STD_LOGIC ;

        WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
        RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);  
        RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
       ); 

end SC_PDPRAM_16K_L ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_PDPRAM_16K_L is

 component SC_BRAM_16K_L

  generic (
 	     DEVICE_FAMILY : string  := "LAVA1";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
   	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 -- Signal Declaration
 
 signal WCEN_node :  STD_LOGIC := 'X';
 signal WCLK_node :  STD_LOGIC := 'X';
 signal WE_node   :  STD_LOGIC := 'X';
 signal WE_reg    :  STD_LOGIC := 'X';
 signal WCS_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RCEN_node :  STD_LOGIC := 'X';
 signal RCLK_node :  STD_LOGIC := 'X';
 signal RST_node  :  STD_LOGIC := 'X';
 signal WD_node   :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
 signal WAD_node  :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
 signal RD_node   :  STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
 signal RD_reg    :  STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
 signal RAD_node  :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X'); 
 

 signal WD_reg    :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
 signal WAD_reg   :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X');
 signal RAD_reg   :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X');
 signal EN_reg    :  STD_LOGIC := 'X';
 signal REN_reg    :  STD_LOGIC := 'X';
 signal GND_sig   :  STD_LOGIC;
 signal VCC_sig   :  STD_LOGIC;

 signal v_RAD      : integer;
 signal v_WAD      : integer;
 signal v_MEM     :  STD_LOGIC_VECTOR(ARRAY_SIZE - 1 downto 0) := ( others => '1' ); 
 -- architecture

 begin
  GND_sig <= '0';
  VCC_sig <= '1';
  WCEN_node <= WCEN;
  WCLK_node <= WCLK;
  WE_node   <= WE;
  WCS_node  <= WCS;
  RCEN_node <= RCEN;
  RCLK_node <= RCLK;
  RST_node  <= RST;
  WD_node   <= WD;
  WAD_node  <= WAD;
  RAD_node  <= RAD;
  RD        <= RD_reg;

process(RAD_node, WAD_node)
begin
  if (Valid_Address(RAD_node) = TRUE) then
  v_RAD <= CONV_INTEGER(RAD_node);
  end if;

  if (Valid_Address(RAD_node) = TRUE) then
  v_WAD <= CONV_INTEGER(RAD_node);
  end if;
end process;

  -- Register WD/WAD/ Enable inputs
  register_write_inputs: process (WCLK_node, RST_node)
  begin
    if (RST_node = '1') then
      WD_reg <= (others =>'0');
      WAD_reg <= (others =>'0');
      WE_reg <= '0';
--      EN_reg <= '0';
--     REN_reg <= '1';
    elsif (WCLK_node'event and WCLK_node = '1') then
      if (WCEN_node = '1') then
        WD_reg  <= WD_node;
        WAD_reg <= WAD_node;
        WE_reg <= WE_node;
--        EN_reg  <= WE_node  and WCS_node(0) and WCS_node(1);
--        REN_reg  <= '1'; 
      end if;
    end if;
  end process register_write_inputs;   

-- Register RAD inputs
  register_read_inputs: process (RCLK_node, RST_node)
  begin
    if (RST_node = '1') then
--      RAD_reg <= (others =>'0');
      RD_reg <= (others =>'0');
    elsif (RCLK_node'event and RCLK_node = '1') then
      if (RCEN_node = '1') then
--        RAD_reg <= RAD_node;
        RD_reg <= RD_node;
      end if;
    end if;
  end process register_read_inputs; 

--  v_MEM_process: process (EN_reg, WD_node)
--  begin
--      if (EN_reg = '1') then
--           for i in 0 to WDATA_WIDTH - 1 loop
         --      v_MEM(v_WAD*WDATA_WIDTH+i) <= RD_node(i) after 1 ps;
--               v_MEM(v_WAD*WDATA_WIDTH+i) <= WD_node(i) after 1 ps;
--           end loop;
--      end if;
--  end process;

--  output_process: process (RST_node, EN_reg, RD_node, RCLK_node)
--  begin
--      if (RST_node = '1') then
--           RD <= (others => '0');
--      elsif (RCLK_node = '1') then
--        if (EN_reg = '1') then
--           for i in 0 to RDATA_WIDTH - 1 loop
--               RD(i) <= v_MEM(v_RAD*RDATA_WIDTH+i);
--           end loop;
--        else
--           RD <= RD_node;
--        end if;
--      end if;
--  end process;
  

-- BRAM instance for SPRAM 
  PDPRAM_INST: SC_BRAM_16K_L

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => WADDR_WIDTH,
         RADDR_WIDTH_A  => RADDR_WIDTH,
         WADDR_WIDTH_B  => WADDR_WIDTH,
         RADDR_WIDTH_B  => RADDR_WIDTH,
         WDATA_WIDTH_A  => WDATA_WIDTH,
         RDATA_WIDTH_A  => RDATA_WIDTH,
         WDATA_WIDTH_B  => WDATA_WIDTH,
         RDATA_WIDTH_B  => RDATA_WIDTH,
         ARRAY_SIZE     => ARRAY_SIZE,
 	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE
       )
    port map (
         WADA => WAD_reg,
         WEA  => WE_reg,
         WDA  => WD_reg,
         RADA => RAD_node,
         REA  => VCC_sig,
         RDA  => RD_node,
         
         WADB => WAD_reg,
         WEB  => GND_sig,
         WDB  => WD_reg,
         RADB => RAD_node,
         REB  => GND_sig,
         RDB  => open
      );

end LATTICE_BEHAV;
 

-- ************************************************************************
--
--  PseudoDPRAM: Behavioral Model
-- ************************************************************************
--
--  Filename:  SC_PDP_RAMA.vhd
--  Description: Asynchronous Read Pseudo Dual Port BRAM behavioral model. 
--
--  Compared with synchronous model 
--  Remove RCLK and RCEN ports   
--  
--  History:
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

-- ************************************************************************
--  Entity definition  
--  Draft "generic" members 
-- ************************************************************************

entity SC_PDPRAMA_16K_L is

  generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        WADDR_WIDTH    : integer := 13;
        WDATA_WIDTH    : integer := 2;
        RADDR_WIDTH    : integer := 13;
        RDATA_WIDTH    : integer := 2;
        ARRAY_SIZE     : integer := 16384;
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "mem_init_file"

        );

  port (
        WCEN : in  STD_LOGIC ;
        WCLK : in  STD_LOGIC ;
        WE   : in  STD_LOGIC ;
        WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
        RST  : in  STD_LOGIC ;

        WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
        RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);  
        RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
       ); 

end SC_PDPRAMA_16K_L ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_PDPRAMA_16K_L is

 component SC_BRAM_PDP_16K_L

  generic (
 	     DEVICE_FAMILY : string  := "LAVA1";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
    	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 -- Signal Declaration
 
 signal WCEN_node :  STD_LOGIC := 'X';
 signal WCLK_node :  STD_LOGIC := 'X';
 signal WE_node   :  STD_LOGIC := 'X';
 signal WCS_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RST_node  :  STD_LOGIC := 'X';
 signal WD_node   :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
 signal WAD_node  :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
 signal RD_node   :  STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');
 signal RAD_node  :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0'); 
 

 signal WD_reg    :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
 signal WAD_reg   :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0');
 signal RAD_reg   :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => '0');
 signal EN_reg    :  STD_LOGIC := 'X';
 signal REN_reg   :  STD_LOGIC := '1';
 signal GND_sig   :  STD_LOGIC;
 signal VCC_sig   :  STD_LOGIC;

 -- architecture

 begin
  GND_sig <= '0';
  VCC_sig <= '1';
  WCEN_node <= WCEN;
  WCLK_node <= WCLK;
  WE_node   <= WE;
  WCS_node  <= WCS;
  RST_node  <= RST;
  WD_node   <= WD;
  WAD_node  <= WAD;
  RAD_node  <= RAD;
  RD        <= RD_node;

  -- Register WD/WAD/ Enable inputs
  register_write_inputs: process (WCLK_node, RST_node)
  begin
    if (RST_node = '1') then
      WD_reg <= (others =>'0');
      WAD_reg <= (others =>'0');
      EN_reg <= '0';
      REN_reg <= '1';
    elsif (WCLK_node'event and WCLK_node = '1') then
       if (WCEN_node = '1') then
        WD_reg  <= WD_node;
        WAD_reg <= WAD_node;
        EN_reg  <= WE_node  and WCS_node(0) and WCS_node(1);
       end if;
    end if;
  end process register_write_inputs;   

-- BRAM instance for SPRAM 
  PDPRAM_INST: SC_BRAM_PDP_16K_L

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => WADDR_WIDTH,
         RADDR_WIDTH_A  => RADDR_WIDTH,
         WADDR_WIDTH_B  => WADDR_WIDTH,
         RADDR_WIDTH_B  => RADDR_WIDTH,
         WDATA_WIDTH_A  => WDATA_WIDTH,
         RDATA_WIDTH_A  => RDATA_WIDTH,
         WDATA_WIDTH_B  => WDATA_WIDTH,
         RDATA_WIDTH_B  => RDATA_WIDTH,
         ARRAY_SIZE     => ARRAY_SIZE,
  	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
         WADA => WAD_reg,
         WEA  => EN_reg,
         WDA  => WD_reg,
         RADA => RAD_node,   
         REA  => REN_reg,
         RDA  => RD_node,
         
         WADB => WAD_reg,
         WEB  => GND_sig,
         WDB  => WD_reg,
         RADB => RAD_node,   
         REB  => GND_sig,
         RDB  => open
      );

end LATTICE_BEHAV;
 



 
-- ************************************************************************
--
--  SPRAM: Behavioral Model
--  
-- ************************************************************************
--
--  Filename:  SC_SP_RAM.vhd
--  Description: Single Port BRAM behavioral model. 
--  History:
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

library lava1;
use lava1.components.all;

-- ************************************************************************
--  Entity definition  
--  Draft "generic" members 
-- ************************************************************************

entity SC_SPRAM_16K_L is

  generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        MEM_INIT_FLAG  : integer := 1;  
        ARRAY_SIZE     : integer := 16384;
	MEM_INIT_FILE  : string  := "qq.dat"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end SC_SPRAM_16K_L ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_SPRAM_16K_L is

 component SC_BRAM_16K_L

  generic (
 	     DEVICE_FAMILY : string  := "LAVA1";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
 	 MEM_INIT_FLAG : integer := 1;  
	 MEM_INIT_FILE : string  := "mem_init_file"

	  );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 -- Signal Declaration
 
 signal CEN_node :  STD_LOGIC := 'X';
 signal CLK_node :  STD_LOGIC := 'X';
 signal WR_node  :  STD_LOGIC := 'X';
 signal CS_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RST_node :  STD_LOGIC := 'X';
 signal DI_node  :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
 signal AD_node  :  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
 signal DO_node  :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');

 signal DI_reg   :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
 signal AD_reg   :  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
 signal EN_reg   :  STD_LOGIC := 'X';
 signal REN_reg   :  STD_LOGIC := 'X';

 signal GND_sig   :  STD_LOGIC;
 signal VCC_sig   :  STD_LOGIC;
 signal v_AD      : integer;
 signal v_MEM     :  STD_LOGIC_VECTOR(ARRAY_SIZE - 1 downto 0) := ( others => '1' ); 

 -- architecture

 begin
  GND_sig <= '0';
  VCC_sig <= '1';

  CEN_node <= CEN;
  CLK_node <= CLK;
  WR_node  <= WR;
  CS_node  <= CS;
  RST_node <= RST;
  DI_node  <= DI;
  AD_node  <= AD;
--  DO       <= DO_node;

process(AD_node)
begin
  if (Valid_Address(AD_node) = TRUE) then
     v_AD <= CONV_INTEGER(AD_node);
  end if;

end process;

  -- Register DI/ AD / Enable inputs
  register_inputs: process (CLK_node, RST_node)
  begin
    if (RST_node = '1') then
      DI_reg <= (others =>'0');
      AD_reg <= (others =>'0');
      EN_reg <= '0';
      REN_reg <= '1';
    elsif (CLK_node'event and CLK_node = '1') then
      if (CEN_node = '1') then
        DI_reg <= DI_node;
        AD_reg <= AD_node;
        EN_reg <= WR_node  and CS_node(0) and CS_node(1);
        REN_reg <= '1'; 
      end if;
    end if;
  end process register_inputs;  

  v_MEM_process: process (EN_reg, DO_node, AD_node)
  begin
      if (EN_reg = '1') then
           for i in 0 to DATA_WIDTH - 1 loop
               v_MEM(v_AD*DATA_WIDTH+i) <= DO_node(i) after 1 ps;
           end loop;
      end if;
  end process;

  output_process: process (RST_node, EN_reg, DO_node, CLK_node)
  begin
     if (RST_node = '1') then
         DO <= (others => '0'); 
     elsif (CLK_node = '1') then
         if (EN_reg = '1') then
           for j in 0 to DATA_WIDTH - 1 loop
               DO(j) <= v_MEM(v_AD*DATA_WIDTH+j);
           end loop;
         else
           DO <= DO_node;
         end if;
     end if;
  end process;


  -- BRAM instance for SPRAM 
  SPRAM_INST: SC_BRAM_16K_L

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => ADDR_WIDTH,
         RADDR_WIDTH_A  => ADDR_WIDTH,
         WADDR_WIDTH_B  => ADDR_WIDTH,
         RADDR_WIDTH_B  => ADDR_WIDTH,
         WDATA_WIDTH_A  => DATA_WIDTH,
         RDATA_WIDTH_A  => DATA_WIDTH,
         WDATA_WIDTH_B  => DATA_WIDTH,
         RDATA_WIDTH_B  => DATA_WIDTH,
         --ct092705 ARRAY_SIZE     => open,
         ARRAY_SIZE     => (2**ADDR_WIDTH) * DATA_WIDTH,

	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE
       )
    port map (
         WADA => AD_reg,
         WEA  => EN_reg,
         WDA  => DI_reg,
         RADA => AD_reg,
         REA  => REN_reg,
         RDA  => DO_node,

         WADB => AD_reg,
         WEB  => GND_sig,
         WDB  => DI_reg,
         RADB => AD_reg,
         REB  => GND_sig,
         RDB  => open
      );

end LATTICE_BEHAV;

-- ************************************************************************
--
--  SPRAM: Behavioral Model
-- ************************************************************************
--
--  Filename:  SC_SP_RAMA.vhd
--  Description: Asynchronous Read Single Port BRAM behavioral model. 
--  Compared with synchronous model, 
--  no ports modification, just logic change 
--  History:
--  May. 30, 2002 Read memory initialization file feature
-- ************************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

-- ************************************************************************
--  Entity definition  
--  Draft "generic" members 
-- ************************************************************************

entity SC_SPRAMA_16K_L is

  generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        ARRAY_SIZE     : integer := 16384;
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "mem_init_file"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end SC_SPRAMA_16K_L ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_SPRAMA_16K_L is

 component SC_BRAM_16K_L

  generic (
 	     DEVICE_FAMILY : string  := "LAVA1";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
  	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 -- Signal Declaration
 
 signal CEN_node :  STD_LOGIC := 'X';
 signal CLK_node :  STD_LOGIC := 'X';
 signal WR_node  :  STD_LOGIC := 'X';
 signal CS_node  :  STD_LOGIC_VECTOR (1 downto 0) := (others => 'X');
 signal RST_node :  STD_LOGIC := 'X';
 signal DI_node  :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
 signal AD_node  :  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
 signal DO_node  :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');

 signal DI_reg   :  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) := (others => 'X');
 signal AD_reg   :  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0) := (others => 'X');
 signal EN_reg   :  STD_LOGIC := 'X';
 signal REN_reg   :  STD_LOGIC := '1';
 signal GND_sig   :  STD_LOGIC;
 signal VCC_sig   :  STD_LOGIC;

 -- architecture

 begin
  GND_sig <= '0';
  VCC_sig <= '1';

  CEN_node <= CEN;
  CLK_node <= CLK;
  WR_node  <= WR;
  CS_node  <= CS;
  RST_node <= RST;
  DI_node  <= DI;
  AD_node  <= AD;

  DO       <= DO_node;


  -- Register DI/ AD / Enable inputs
  register_inputs: process (CLK_node, RST_node)
  begin
    if (RST_node = '1') then
      DI_reg <= (others =>'0');
      AD_reg <= (others =>'0');
      EN_reg <= '0';
      REN_reg <= '1';
    elsif (CLK_node'event and CLK_node = '1') then
      if (CEN_node = '1') then
        DI_reg <= DI_node;
        AD_reg <= AD_node;
        EN_reg <= WR_node  and CS_node(0) and CS_node(1);
       -- REN_reg <= '1'; 
      end if;
    end if;
  end process register_inputs;   

  -- BRAM instance for SPRAM 
  SPRAM_INST: SC_BRAM_16K_L

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => ADDR_WIDTH,
         RADDR_WIDTH_A  => ADDR_WIDTH,
         WADDR_WIDTH_B  => ADDR_WIDTH,
         RADDR_WIDTH_B  => ADDR_WIDTH,
         WDATA_WIDTH_A  => DATA_WIDTH,
         RDATA_WIDTH_A  => DATA_WIDTH,
         WDATA_WIDTH_B  => DATA_WIDTH,
         RDATA_WIDTH_B  => DATA_WIDTH,
         ARRAY_SIZE     => ARRAY_SIZE,
 	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
--       WADA => AD_reg,
         WADA => AD_reg,
         WEA  => EN_reg,
         WDA  => DI_reg,
--       RADA => AD_reg,  -- Synchronous
         RADA => AD_node, -- Asynchronous
	 REA  => REN_reg,
         RDA  => DO_node,
         
--       WADB => AD_reg,
         WADB => AD_reg,
         WEB  => GND_sig,
         WDB  => DI_reg,
         RADB => AD_reg,
         REB  => GND_sig,
         RDB  => open
      );

end LATTICE_BEHAV;
 

library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.ALL;
use IEEE.std_logic_signed.all;

Library lava1;
USE lava1.components.all;

ENTITY L_ABS is
    GENERIC (LPM_WIDTH: positive;
             LPM_TYPE: string;
             LPM_HINT: string);
    PORT (DATA: IN std_logic_vector(LPM_WIDTH-1 downto 0);
          OVERFLOW: OUT std_logic;
          RESULT: OUT std_logic_vector(LPM_WIDTH-1 downto 0));
    FUNCTION str_to_int(s: string) return integer IS
      VARIABLE len: integer:=s'length;
      VARIABLE ivalue: integer:=0;
      VARIABLE digit:integer;
      BEGIN
        for i in 1 to len loop
          case s(i) is
            when '0' =>
              digit := 0;
            when '1' =>
              digit := 1;
            when '2' =>
              digit := 2;
            when '3' =>
              digit := 3;
            when '4' =>
              digit := 4;
            when '5' =>
              digit := 5;
            when '6' =>
              digit := 6;
            when '7' =>
              digit := 7;
            when '8' =>
              digit := 8;
            when '9' =>
              digit := 9;
            when others =>
              ASSERT FALSE
              REPORT "Illegal Character " & s(i) & "in string parameter! "
              SEVERITY ERROR;
          end case;
          ivalue := ivalue*10 + digit;
        end loop;
        return ivalue;
      end;
END L_ABS;

ARCHITECTURE LPM_SYN of L_ABS is
    BEGIN
      PROCESS(DATA)
        BEGIN
             if(DATA = conv_std_logic_vector(-(2 ** (LPM_WIDTH-1)), LPM_WIDTH)) then
                OVERFLOW <= '1';
                RESULT <= (OTHERS => 'X');
             elsif DATA < conv_std_logic_vector(0, LPM_WIDTH) then
                RESULT <= conv_std_logic_vector(0, LPM_WIDTH)-DATA;
                OVERFLOW <= '0';
             else
                RESULT <= DATA;
                OVERFLOW <= '0';
             end if;
    END PROCESS;
end LPM_SYN;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;

Library lava1;
USE lava1.components.all;

entity L_ADD_SUB_SIGNED is
        generic (LPM_WIDTH : positive;
                 LPM_DIRECTION : string;
                 LPM_PIPELINE : integer := 0;
                 LPM_TYPE : string;
                 LPM_HINT : string);
        port (DATAA : in std_logic_vector(LPM_WIDTH downto 1);
              DATAB : in std_logic_vector(LPM_WIDTH downto 1);
              ACLR : in std_logic;
              CLOCK : in std_logic;
              CIN : in std_logic;
              ADD_SUB : in std_logic;
              RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
              COUT : out std_logic;
              OVERFLOW : out std_logic);
end L_ADD_SUB_SIGNED;

architecture LPM_SYN of L_ADD_SUB_SIGNED is

signal A, B : std_logic_vector(LPM_WIDTH downto 0);
signal INIT : std_logic := '0';
type t_resulttmp IS ARRAY (0 to LPM_PIPELINE) of std_logic_vector(LPM_WIDTH downto 0);

begin
        A <= (DATAA(LPM_WIDTH) & DATAA);
        B <= (DATAB(LPM_WIDTH) & DATAB);

        process(ACLR, CLOCK, A, B, CIN, ADD_SUB)
        variable resulttmp : t_resulttmp;
        variable couttmp : std_logic_vector(0 to LPM_PIPELINE);
        variable overflowtmp : std_logic_vector(0 to LPM_PIPELINE);
        variable ovflow : std_logic_vector (LPM_WIDTH-1 downto 0);
        variable ovflow1 : std_logic_vector (LPM_WIDTH-1 downto 0);
        begin

           if INIT = '0' then
                FOR i IN (LPM_WIDTH-1) downto 0 LOOP
                    if i = (LPM_WIDTH-1) then
                        ovflow(i) := '1';
                        ovflow1(i) := '0';
                    else
                        ovflow(i) := '0';
                        ovflow1(i) := '1';
                    end if;
                END LOOP;
            end if;
                if LPM_PIPELINE >= 0 then
                        if LPM_DIRECTION = "ADD" or
                           (LPM_DIRECTION /= "SUB" and ADD_SUB = '1') then
                                resulttmp(LPM_PIPELINE) := A + B + CIN;
                                couttmp(LPM_PIPELINE) := resulttmp(LPM_PIPELINE)(LPM_WIDTH)
                                                         xor DATAA(LPM_WIDTH)
                                                         xor DATAB(LPM_WIDTH);
                        else
                                resulttmp(LPM_PIPELINE) := A - B + CIN - 1;
                                couttmp(LPM_PIPELINE) := not resulttmp(LPM_PIPELINE)(LPM_WIDTH)
                                                         xor DATAA(LPM_WIDTH)
                                                         xor DATAB(LPM_WIDTH);
                        end if;
                        if (resulttmp(LPM_PIPELINE) > ovflow1) or
                           (resulttmp(LPM_PIPELINE) < ovflow) then
                                overflowtmp(LPM_PIPELINE) := '1';
                        else
                                overflowtmp(LPM_PIPELINE) := '0';
                        end if;
                        if LPM_PIPELINE > 0 then
                                if ACLR = '1' then
                                   overflowtmp := (OTHERS => '0');
                                   couttmp := (OTHERS => '0');
                                   for i in 0 to LPM_PIPELINE loop
                                           resulttmp(i) := (OTHERS => '0');
                                   end loop;
                                elsif CLOCK'event and CLOCK = '1' then
                                   overflowtmp(0 to LPM_PIPELINE - 1) := overflowtmp(1 to LPM_PIPELINE);
                                   couttmp(0 to LPM_PIPELINE - 1) := couttmp(1 to LPM_PIPELINE);
                                   resulttmp(0 to LPM_PIPELINE - 1) := resulttmp(1 to LPM_PIPELINE);
                                end if;
                        end if;

                        COUT <= couttmp(0);
                        OVERFLOW <= overflowtmp(0);
                        RESULT <= resulttmp(0)(LPM_WIDTH-1 downto 0);
                end if;
        end process;

end LPM_SYN;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

Library lava1;
USE lava1.components.all;

entity L_ADD_SUB_UNSIGNED is
        generic (LPM_WIDTH : positive;
                 LPM_DIRECTION : string;
                 LPM_PIPELINE : integer;
                 LPM_TYPE : string;
                 LPM_HINT : string);
        port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
              DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
              ACLR : in std_logic;
              CLOCK : in std_logic;
              CIN : in std_logic;
              ADD_SUB : in std_logic;
              RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
              COUT : out std_logic;
              OVERFLOW : out std_logic);
end L_ADD_SUB_UNSIGNED;

architecture LPM_SYN of L_ADD_SUB_UNSIGNED is
signal A, B : std_logic_vector(LPM_WIDTH downto 0);
type t_resulttmp IS ARRAY (0 to LPM_PIPELINE) of std_logic_vector(LPM_WIDTH downto 0);

begin

        A <= ('0' & DATAA);
        B <= ('0' & DATAB);

        process(ACLR, CLOCK, A, B, CIN, ADD_SUB)
        variable resulttmp : t_resulttmp;
        variable couttmp : std_logic_vector(0 to LPM_PIPELINE);
        variable overflowtmp : std_logic_vector(0 to LPM_PIPELINE);
        begin

                if LPM_PIPELINE >= 0 then
                        if LPM_DIRECTION = "ADD" or
                           (LPM_DIRECTION /= "SUB" and ADD_SUB = '1') then

                                resulttmp(LPM_PIPELINE) := A + B + CIN;
                                couttmp(LPM_PIPELINE) := resulttmp(LPM_PIPELINE)(LPM_WIDTH);
                        else
                                resulttmp(LPM_PIPELINE) := A - B + CIN-1;
                                couttmp(LPM_PIPELINE) := not resulttmp(LPM_PIPELINE)(LPM_WIDTH);
                        end if;

                        overflowtmp(LPM_PIPELINE) := resulttmp(LPM_PIPELINE)(LPM_WIDTH);

                        if LPM_PIPELINE > 0 then
                                if ACLR = '1' then
                                   overflowtmp := (OTHERS => '0');
                                   couttmp := (OTHERS => '0');
                                   for i in 0 to LPM_PIPELINE loop
                                       resulttmp(i) := (OTHERS => '0');
                                   end loop;
                                elsif CLOCK'event and CLOCK = '1' then
                                   overflowtmp(0 to LPM_PIPELINE - 1) := overflowtmp(1 to LPM_PIPELINE);
                                   couttmp(0 to LPM_PIPELINE - 1) := couttmp(1 to LPM_PIPELINE);
                                   resulttmp(0 to LPM_PIPELINE - 1) := resulttmp(1 to LPM_PIPELINE);
                                end if;
                        end if;

                        COUT <= couttmp(0);
                        OVERFLOW <= overflowtmp(0);
                        RESULT <= resulttmp(0)(LPM_WIDTH-1 downto 0);
                end if;
        end process;

end LPM_SYN;

library IEEE;
USE IEEE.std_logic_1164.ALL;

Library lava1;
USE lava1.components.all;

ENTITY L_ADD_SUB IS

    GENERIC (LPM_WIDTH: positive;
             LPM_DIRECTION : string;
             LPM_REPRESENTATION: string;
             LPM_PIPELINE : integer;
             LPM_TYPE : string;
             LPM_HINT : string);
       port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
             DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
             ACLR : in std_logic;
             CLOCK : in std_logic;
             CIN : in std_logic;
             ADD_SUB : in std_logic;
             RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
             COUT : out std_logic;
             OVERFLOW : out std_logic);
END L_ADD_SUB;

architecture LPM_SYN of L_ADD_SUB is

        component L_ADD_SUB_SIGNED
                        generic (LPM_WIDTH : positive;
                                 LPM_DIRECTION : string;
                                 LPM_PIPELINE : integer;
                                 LPM_TYPE : string;
                                 LPM_HINT : string);
                        port (DATAA : in std_logic_vector(LPM_WIDTH downto 1);
                              DATAB : in std_logic_vector(LPM_WIDTH downto 1);
                              ACLR : in std_logic;
                              CLOCK : in std_logic;
                              CIN : in std_logic;
                              ADD_SUB : in std_logic;
                              RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
                              COUT : out std_logic;
                              OVERFLOW : out std_logic);
        end component;

        component L_ADD_SUB_UNSIGNED
                        generic (LPM_WIDTH : positive;
                                         LPM_DIRECTION : string;
                                         LPM_PIPELINE : integer;
                                         LPM_TYPE : string;
                                         LPM_HINT : string);
                        port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
                              DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
                              ACLR : in std_logic;
                              CLOCK : in std_logic;
                              CIN : in std_logic;
                              ADD_SUB : in std_logic;
                              RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
                              COUT : out std_logic;
                              OVERFLOW : out std_logic);
        end component;

begin

L1: if LPM_REPRESENTATION = "UNSIGNED" generate

U:  L_ADD_SUB_UNSIGNED
        generic map (LPM_WIDTH => LPM_WIDTH, LPM_DIRECTION => LPM_DIRECTION,
                     LPM_PIPELINE => LPM_PIPELINE, LPM_TYPE => LPM_TYPE,
                     LPM_HINT => LPM_HINT)
        port map (DATAA => DATAA, DATAB => DATAB, ACLR => ACLR, CLOCK => CLOCK,
                  CIN => CIN, ADD_SUB => ADD_SUB, RESULT => RESULT, COUT => COUT,
                  OVERFLOW => OVERFLOW);
        end generate;

L2: if LPM_REPRESENTATION = "SIGNED" generate

V:  L_ADD_SUB_SIGNED
        generic map (LPM_WIDTH => LPM_WIDTH, LPM_DIRECTION => LPM_DIRECTION,
                     LPM_PIPELINE => LPM_PIPELINE, LPM_TYPE => LPM_TYPE,
                     LPM_HINT => LPM_HINT)
        port map (DATAA => DATAA, DATAB => DATAB, ACLR => ACLR, CLOCK => CLOCK,
                  CIN => CIN, ADD_SUB => ADD_SUB, RESULT => RESULT, COUT => COUT,
                  OVERFLOW => OVERFLOW);
        end generate;

end LPM_SYN;
library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.ALL;
use IEEE.std_logic_unsigned.all;

Library lava1;
USE lava1.components.all;

entity L_CLSHIFT is
        generic (LPM_WIDTH : positive;
                 LPM_WIDTHDIST : positive;
                 LPM_SHIFTTYPE : string;
                 LPM_TYPE : string;
                 LPM_HINT : string);
        port (DATA : in STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0);
                  DISTANCE : in STD_LOGIC_VECTOR(LPM_WIDTHDIST-1 downto 0);
                  DIRECTION : in STD_LOGIC;
                  RESULT : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0);
                  UNDERFLOW : out STD_LOGIC;
                  OVERFLOW : out STD_LOGIC);
end L_CLSHIFT;

architecture LPM_SYN of L_CLSHIFT is
signal IRESULT : std_logic_vector(LPM_WIDTH-1 downto 0);
begin
        process(DATA, DISTANCE, DIRECTION)
        begin
           if LPM_SHIFTTYPE = "ARITHMETIC" then
                if DIRECTION = '0' then
                   IRESULT(LPM_WIDTH-1 downto conv_integer(DISTANCE)) <= DATA(LPM_WIDTH-1-conv_integer(DISTANCE) downto 0);
                   IRESULT(conv_integer(DISTANCE)-1 downto 0) <= (OTHERS => '0');
                else
                   if DATA(LPM_WIDTH-1) = '0' then
                        IRESULT(LPM_WIDTH-1 downto LPM_WIDTH-conv_integer(DISTANCE)) <= (OTHERS => '0');
                        IRESULT(LPM_WIDTH-1-conv_integer(DISTANCE) downto 0) <= DATA(LPM_WIDTH-1 downto conv_integer(DISTANCE));
                   else
                        IRESULT(LPM_WIDTH-1-conv_integer(DISTANCE) downto 0) <= DATA(LPM_WIDTH-1 downto conv_integer(DISTANCE));
                        IRESULT(LPM_WIDTH-1 downto LPM_WIDTH-conv_integer(DISTANCE)) <= (OTHERS => '1');
                   end if;
                end if;
           elsif LPM_SHIFTTYPE = "ROTATE" then
                if DIRECTION = '0' then
                   IRESULT <= (DATA(LPM_WIDTH-conv_integer(DISTANCE)-1 downto 0) &
                        DATA(LPM_WIDTH-1 downto LPM_WIDTH-conv_integer(DISTANCE)));
                else
                   IRESULT <= (DATA(conv_integer(DISTANCE)-1 downto 0) &
                        DATA(LPM_WIDTH-1 downto conv_integer(DISTANCE)));
                end if;
           else
              if DISTANCE = 0 then
                IRESULT(LPM_WIDTH-1 downto 0) <= DATA(LPM_WIDTH-1 downto 0);
              elsif DISTANCE > 0 then
                if DIRECTION =  '1' then
                   IRESULT(LPM_WIDTH-1 downto LPM_WIDTH-conv_integer(DISTANCE)) <= (OTHERS => '0');
                   IRESULT(LPM_WIDTH-1-conv_integer(DISTANCE) downto 0) <= DATA(LPM_WIDTH-1 downto conv_integer(DISTANCE));
                else
                   IRESULT(LPM_WIDTH-1 downto conv_integer(DISTANCE)) <= DATA(LPM_WIDTH-1-conv_integer(DISTANCE) downto 0);
                   IRESULT(conv_integer(DISTANCE)-1 downto 0) <= (OTHERS => '0');
                end if;
              end if;
           end if;
        end process;
        process(IRESULT)
        begin
           if LPM_SHIFTTYPE = "LOGICAL" or LPM_SHIFTTYPE = "ROTATE" then
                if IRESULT > 2 ** (LPM_WIDTH) then
                   OVERFLOW <= '1';
                else
                   OVERFLOW <= '0';
                end if;
                if IRESULT = 0 then
                   UNDERFLOW <= '1';
                else
                   UNDERFLOW <= '0';
                end if;
           else
                OVERFLOW <= '0';
                UNDERFLOW <= '0';
           end if;
        end process;
        RESULT <= IRESULT;
end LPM_SYN;
library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.ALL;
use IEEE.std_logic_signed.all;

Library lava1;
USE lava1.components.all;
entity L_COMPARE_SIGNED is
        generic (LPM_WIDTH : positive;
                LPM_PIPELINE : integer;
                LPM_TYPE: string;
                LPM_HINT : string);
        port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
                DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
                ACLR : in std_logic;
                CLOCK : in std_logic;
                AGB : out std_logic;
                AGEB : out std_logic;
                AEB : out std_logic;
                ANEB : out std_logic;
                ALB : out std_logic;
                ALEB : out std_logic);
end L_COMPARE_SIGNED;

architecture LPM_SYN of L_COMPARE_SIGNED is
begin

        process(ACLR, CLOCK, DATAA, DATAB)
           variable agbtmp : std_logic_vector (0 to LPM_PIPELINE);
           variable agebtmp : std_logic_vector (0 to LPM_PIPELINE);
           variable aebtmp : std_logic_vector (0 to LPM_PIPELINE);
           variable anebtmp : std_logic_vector (0 to LPM_PIPELINE);
           variable albtmp : std_logic_vector (0 to LPM_PIPELINE);
           variable alebtmp : std_logic_vector (0 to LPM_PIPELINE);
           variable dataaa : std_logic_vector (LPM_WIDTH-1 downto 0);
           variable databb : std_logic_vector (LPM_WIDTH-1 downto 0);

        begin

           if LPM_PIPELINE >= 0 then
              if DATAA(LPM_WIDTH-1) = '1' and DATAB(LPM_WIDTH-1) = '0' then
                 agbtmp(LPM_PIPELINE) := '0';
                 agebtmp(LPM_PIPELINE) := '0';
                 anebtmp(LPM_PIPELINE) := '1';
                 aebtmp(LPM_PIPELINE) := '0';
                 albtmp(LPM_PIPELINE) := '1';
                 alebtmp(LPM_PIPELINE) := '1';
              elsif DATAA(LPM_WIDTH-1) = '0'  and DATAB(LPM_WIDTH-1) = '1'      then
                 agbtmp(LPM_PIPELINE) := '1';
                 agebtmp(LPM_PIPELINE) := '1';
                 anebtmp(LPM_PIPELINE) := '1';
                 aebtmp(LPM_PIPELINE) := '0';
                 albtmp(LPM_PIPELINE) := '0';
                 alebtmp(LPM_PIPELINE) := '0';
              elsif DATAA(LPM_WIDTH-1) = '0'  and  DATAB(LPM_WIDTH-1) = '0' then
                 agbtmp(LPM_PIPELINE) := '0';
                 agebtmp(LPM_PIPELINE) := '1';
                 anebtmp(LPM_PIPELINE) := '0';
                 aebtmp(LPM_PIPELINE) := '1';
                 albtmp(LPM_PIPELINE) := '0';
                 alebtmp(LPM_PIPELINE) := '1';
                 FOR i IN (LPM_WIDTH-2) downto 0 LOOP
                    if(DATAA(i) > DATAB(i)) then
                        agbtmp(LPM_PIPELINE) := '1';
                        agebtmp(LPM_PIPELINE) := '1';
                        anebtmp(LPM_PIPELINE) := '1';
                        aebtmp(LPM_PIPELINE) := '0';
                        albtmp(LPM_PIPELINE) := '0';
                        alebtmp(LPM_PIPELINE) := '0';
                        EXIT;
                    elsif(DATAA(i) < DATAB(i)) then
                        agbtmp(LPM_PIPELINE) := '0';
                        agebtmp(LPM_PIPELINE) := '0';
                        anebtmp(LPM_PIPELINE) := '1';
                        aebtmp(LPM_PIPELINE) := '0';
                        albtmp(LPM_PIPELINE) := '1';
                        alebtmp(LPM_PIPELINE) := '1';
                        EXIT;
                    end if;
                 END LOOP;
              elsif DATAA(LPM_WIDTH-1) = '1' and DATAB(LPM_WIDTH-1) = '1' then
                 agbtmp(LPM_PIPELINE) := '0';
                 agebtmp(LPM_PIPELINE) := '1';
                 anebtmp(LPM_PIPELINE) := '0';
                 aebtmp(LPM_PIPELINE) := '1';
                 albtmp(LPM_PIPELINE) := '0';
                 alebtmp(LPM_PIPELINE) := '1';
                 dataaa := DATAA;
                 databb := DATAB;
                 FOR i IN (LPM_WIDTH-1) downto 0 LOOP
                    dataaa(i) := dataaa(i) xor '1';
                    databb(i) := databb(i) xor '1';
                 END LOOP;
                 dataaa := dataaa +1;
                 databb := databb +1;
                 FOR i IN (LPM_WIDTH-1) downto 0 LOOP
                    if(dataaa(i) > databb(i)) then
                        agbtmp(LPM_PIPELINE) := '0';
                        agebtmp(LPM_PIPELINE) := '0';
                        anebtmp(LPM_PIPELINE) := '1';
                        aebtmp(LPM_PIPELINE) := '0';
                        albtmp(LPM_PIPELINE) := '1';
                        alebtmp(LPM_PIPELINE) := '1';
                        EXIT;
                    elsif(dataaa(i) < databb(i)) then
                        agbtmp(LPM_PIPELINE) := '1';
                        agebtmp(LPM_PIPELINE) := '1';
                        anebtmp(LPM_PIPELINE) := '1';
                        aebtmp(LPM_PIPELINE) := '0';
                        albtmp(LPM_PIPELINE) := '0';
                        alebtmp(LPM_PIPELINE) := '0';
                        EXIT;
                    end if;
                 END LOOP;
              end if;
              if LPM_PIPELINE > 0 then
                 if ACLR = '1' then
                    for i in 0 to LPM_PIPELINE loop
                       agbtmp(i) := '0';
                       agebtmp(i) := '0';
                       anebtmp(i) := '0';
                       aebtmp(i) := '0';
                       albtmp(i) := '0';
                       alebtmp(i) := '0';
                    end loop;
                 elsif CLOCK'event and CLOCK = '1' then
                    agbtmp(0 to LPM_PIPELINE-1) :=  agbtmp(1 to LPM_PIPELINE);
                    agebtmp(0 to LPM_PIPELINE-1) := agebtmp(1 to LPM_PIPELINE) ;
                    anebtmp(0 to LPM_PIPELINE-1) := anebtmp(1 to LPM_PIPELINE);
                    aebtmp(0 to LPM_PIPELINE-1) := aebtmp(1 to LPM_PIPELINE);
                    albtmp(0 to LPM_PIPELINE-1) := albtmp(1 to LPM_PIPELINE);
                    alebtmp(0 to LPM_PIPELINE-1) := alebtmp(1 to LPM_PIPELINE);
                 end if;
              end if;
           end if;

           AGB <= agbtmp(0);
           AGEB <= agebtmp(0);
           ANEB <= anebtmp(0);
           AEB <= aebtmp(0);
           ALB <= albtmp(0);
           ALEB <= alebtmp(0);
        end process;

  end LPM_SYN;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

Library lava1;
USE lava1.components.all;

entity L_COMPARE_UNSIGNED is
        generic (LPM_WIDTH : positive;
                 LPM_PIPELINE : integer;
                 LPM_TYPE: string;
                 LPM_HINT : string);
        port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
              DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
              ACLR : in std_logic;
              CLOCK : in std_logic;
              AGB : out std_logic;
              AGEB : out std_logic;
              AEB : out std_logic;
              ANEB : out std_logic;
              ALB : out std_logic;
              ALEB : out std_logic);
  end L_COMPARE_UNSIGNED;

  architecture LPM_SYN of L_COMPARE_UNSIGNED is
  begin

        process(ACLR, CLOCK, DATAA, DATAB)
           variable agbtmp : std_logic_vector (0 to LPM_PIPELINE);
           variable agebtmp : std_logic_vector (0 to LPM_PIPELINE);
           variable aebtmp : std_logic_vector (0 to LPM_PIPELINE);
           variable anebtmp : std_logic_vector (0 to LPM_PIPELINE);
           variable albtmp : std_logic_vector (0 to LPM_PIPELINE);
           variable alebtmp : std_logic_vector (0 to LPM_PIPELINE);

        begin
           if LPM_PIPELINE >= 0 then
              agbtmp(LPM_PIPELINE) := '0';
              agebtmp(LPM_PIPELINE) := '1';
              anebtmp(LPM_PIPELINE) := '0';
              aebtmp(LPM_PIPELINE) := '1';
              albtmp(LPM_PIPELINE) := '0';
              alebtmp(LPM_PIPELINE) := '1';
              FOR i IN (LPM_WIDTH-1) downto 0 LOOP
                   if(DATAA(i) > DATAB(i)) then
                        agbtmp(LPM_PIPELINE) := '1';
                        agebtmp(LPM_PIPELINE) := '1';
                        anebtmp(LPM_PIPELINE) := '1';
                        aebtmp(LPM_PIPELINE) := '0';
                        albtmp(LPM_PIPELINE) := '0';
                        alebtmp(LPM_PIPELINE) := '0';
                        EXIT;
                   elsif(DATAA(i) < DATAB(i)) then
                        agbtmp(LPM_PIPELINE) := '0';
                        agebtmp(LPM_PIPELINE) := '0';
                        anebtmp(LPM_PIPELINE) := '1';
                        aebtmp(LPM_PIPELINE) := '0';
                        albtmp(LPM_PIPELINE) := '1';
                        alebtmp(LPM_PIPELINE) := '1';
                        EXIT;
                   end if;
              END LOOP;
              if LPM_PIPELINE > 0 then
                 if ACLR = '1' then
                    for i in 0 to LPM_PIPELINE loop
                       agbtmp(i) := '0';
                       agebtmp(i) := '0';
                       anebtmp(i) := '0';
                       aebtmp(i) := '0';
                       albtmp(i) := '0';
                       alebtmp(i) := '0';
                    end loop;
                 elsif CLOCK'event and CLOCK = '1' then
                    agbtmp(0 to LPM_PIPELINE-1) :=  agbtmp(1 to LPM_PIPELINE);
                    agebtmp(0 to LPM_PIPELINE-1) := agebtmp(1 to LPM_PIPELINE) ;
                    anebtmp(0 to LPM_PIPELINE-1) := anebtmp(1 to LPM_PIPELINE);
                    aebtmp(0 to LPM_PIPELINE-1) := aebtmp(1 to LPM_PIPELINE);
                    albtmp(0 to LPM_PIPELINE-1) := albtmp(1 to LPM_PIPELINE);
                    alebtmp(0 to LPM_PIPELINE-1) := alebtmp(1 to LPM_PIPELINE);
                 end if;
              end if;
           end if;

           AGB <= agbtmp(0);
           AGEB <= agebtmp(0);
           ANEB <= anebtmp(0);
           AEB <= aebtmp(0);
           ALB <= albtmp(0);
           ALEB <= alebtmp(0);
        end process;

  end LPM_SYN;


library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.ALL;

Library lava1;
USE lava1.components.all;

ENTITY L_COMPARE is
    GENERIC (LPM_WIDTH: positive;
             LPM_REPRESENTATION : string;
             LPM_PIPELINE : integer;
             LPM_TYPE: string;
             LPM_HINT : string);
    PORT (DATAA: IN std_logic_vector(LPM_WIDTH-1 downto 0);
          DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
          ACLR : in std_logic;
          CLOCK : in std_logic;
          AGB : out std_logic;
          AGEB : out std_logic;
          AEB : out std_logic;
          ANEB : out std_logic;
          ALB : out std_logic;
          ALEB : out std_logic);
END L_COMPARE;

ARCHITECTURE LPM_SYN of L_COMPARE is
      component L_COMPARE_SIGNED
                 generic (LPM_WIDTH : positive;
                          LPM_PIPELINE : integer;
                          LPM_TYPE: string;
                          LPM_HINT : string);
                 port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
                       DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
                       ACLR : in std_logic;
                       CLOCK : in std_logic;
                       AGB : out std_logic;
                       AGEB : out std_logic;
                       AEB : out std_logic;
                       ANEB : out std_logic;
                       ALB : out std_logic;
                       ALEB : out std_logic);
        end component;

        component L_COMPARE_UNSIGNED
                generic (LPM_WIDTH : positive;
                         LPM_PIPELINE : integer;
                         LPM_TYPE: string;
                         LPM_HINT : string);
                port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
                      DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
                      ACLR : in std_logic;
                      CLOCK : in std_logic;
                      AGB : out std_logic;
                      AGEB : out std_logic;
                      AEB : out std_logic;
                      ANEB : out std_logic;
                      ALB : out std_logic;
                      ALEB : out std_logic);
        end component;
   begin

     L1: if LPM_REPRESENTATION = "UNSIGNED" generate

        U1: L_COMPARE_UNSIGNED
         generic map (LPM_WIDTH => LPM_WIDTH, LPM_PIPELINE => LPM_PIPELINE,
                                 LPM_TYPE => LPM_TYPE, LPM_HINT => LPM_HINT)
         port map (DATAA => DATAA, DATAB => DATAB, ACLR => ACLR,
                          CLOCK => CLOCK, AGB => AGB, AGEB => AGEB,
                          AEB => AEB, ANEB => ANEB, ALB => ALB, ALEB => ALEB);
     end generate;

     L2: if LPM_REPRESENTATION = "SIGNED" generate

        U2: L_COMPARE_SIGNED
         generic map (LPM_WIDTH => LPM_WIDTH, LPM_PIPELINE => LPM_PIPELINE,
                                 LPM_TYPE => LPM_TYPE, LPM_HINT => LPM_HINT)
         port map (DATAA => DATAA, DATAB => DATAB, ACLR => ACLR,
                          CLOCK => CLOCK, AGB => AGB, AGEB => AGEB,
                          AEB => AEB, ANEB => ANEB, ALB => ALB, ALEB => ALEB);
     end generate;

end LPM_SYN;
library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.ALL;
use IEEE.std_logic_unsigned.all;

Library lava1;
USE lava1.components.all;

ENTITY L_COUNTER is
    GENERIC (LPM_WIDTH: positive;
             LPM_MODULUS: natural;
                 LPM_DIRECTION : string;
                 LPM_AVALUE : string;
                 LPM_SVALUE : string;
                 LPM_PVALUE : string;
                 LPM_TYPE: string;
                 LPM_HINT : string);
        port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
                 CLOCK : in std_logic;
                 CLK_EN : in std_logic;
                 CNT_EN : in std_logic;
                 UPDOWN : in std_logic;
                 SLOAD : in std_logic;
                 SSET : in std_logic;
                 SCLR : in std_logic;
                 ALOAD : in std_logic;
                 ASET : in std_logic;
                 ACLR : in std_logic;
                 CIN : in std_logic;
                 COUT : out std_logic;
                 Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
END L_COUNTER;

ARCHITECTURE LPM_SYN of L_COUNTER is
signal COUNT : std_logic_vector(LPM_WIDTH downto 0);
signal INIT : std_logic := '0';

begin

        Counter: process (CLOCK, ACLR, ASET, ALOAD, DATA, INIT)
        variable IAVALUE, ISVALUE : integer;
        variable IMODULUS : integer;
        variable dir_tmp : integer;
        variable vmodulus : std_logic_vector (LPM_WIDTH downto 0);

        begin
           -- INITIALIZE TO PVALUE & SETUP VARIABLES --
           if INIT = '0' then
              if LPM_PVALUE /= "UNUSED" then
                 COUNT <= conv_std_logic_vector(Str2int(LPM_PVALUE), LPM_WIDTH+1);
              end if;
              FOR i IN (LPM_WIDTH) downto 0 LOOP
                 if i = LPM_WIDTH then
                    vmodulus(i) := '1';
                 else
                    vmodulus(i) := '0';
                 end if;
              END LOOP;
              INIT <= '1';
           else
              if ACLR =  '1' then
                 COUNT <= (OTHERS => '0');
              elsif ASET = '1' then
                 if LPM_AVALUE = "UNUSED" then
                    COUNT <= (OTHERS => '1');
                 else
                    IAVALUE := Str2int(LPM_AVALUE);
                    COUNT <= conv_std_logic_vector(IAVALUE, LPM_WIDTH+1);
                 end if;
              elsif ALOAD = '1' then
                 COUNT(LPM_WIDTH-1 downto 0) <= DATA;
              elsif CLOCK'event and CLOCK = '1' then
                 if CLK_EN = '1' then
                    if SCLR = '1' then
                       COUNT <= (OTHERS => '0');
                    elsif SSET = '1' then
                       if LPM_SVALUE = "UNUSED" then
                          COUNT <= (OTHERS => '1');
                       else
                          ISVALUE := Str2int(LPM_SVALUE);
                          COUNT <= conv_std_logic_vector(ISVALUE, LPM_WIDTH+1);
                       end if;
                    elsif SLOAD = '1' then
                       COUNT(LPM_WIDTH-1 downto 0) <= DATA;
                    elsif CNT_EN = '1' then
                       if LPM_DIRECTION = "UNUSED" then
                          if UPDOWN = '0' then
                             dir_tmp := 0;   -- decrement
                          else
                             dir_tmp := 1;   -- increment
                          end if;
                       elsif LPM_DIRECTION = "UP" then
                          dir_tmp := 1;       -- increment
                       elsif LPM_DIRECTION = "DOWN" then
                          dir_tmp := 0;       -- decrement
                       else
                          dir_tmp := 1;       -- illegal param value; increment
                       end if;

                       if vmodulus = 1 then
                          COUNT <= (OTHERS => '0');
                       elsif dir_tmp = 1 then
                          -- INCREMENT --
                          if COUNT >= vmodulus - 1 then
                             COUNT <= conv_std_logic_vector(CIN, LPM_WIDTH+1);
                          elsif COUNT >= vmodulus - 2 then
                             if CIN = '1' then
                                COUNT <= conv_std_logic_vector(0, LPM_WIDTH+1);
                             else
                                COUNT <= vmodulus-1;
                             end if;
                          else
                             COUNT <= COUNT + 1 + CIN;
                          end if;
                       else
                          -- DECREMENT --
                          if COUNT = 0 then
                             if CIN = '1' then
                                COUNT <= vmodulus-2;
                             else
                                COUNT <= vmodulus-1;
                             end if;
                          elsif COUNT = 1 then
                             if CIN = '1' then
                                COUNT <= vmodulus-1;
                             else
                                COUNT <= conv_std_logic_vector(0, LPM_WIDTH+1);
                             end if;
                          else
                             COUNT <= COUNT - 1 - CIN;
                          end if;
                       end if;
                    else
                    end if;
                 else
                 end if;
              else
              end if;
           end if;
           COUNT(LPM_WIDTH) <= '0';
        end process Counter;

        CarryOut: process (COUNT, CIN, INIT)
        variable IMODULUS : integer;
        variable dir_tmp : integer;
        variable vmodulus : std_logic_vector (LPM_WIDTH downto 0);

        begin
           if INIT = '1' then
              FOR i IN (LPM_WIDTH) downto 0 LOOP
                 if i = LPM_WIDTH then
                    vmodulus(i) := '1';
                 else
                    vmodulus(i) := '0';
                 end if;
              END LOOP;
              if LPM_DIRECTION = "UNUSED" then
                 if UPDOWN = '0' then
                    dir_tmp := 0;   -- decrement
                 else
                    dir_tmp := 1;   -- increment
                 end if;
              elsif LPM_DIRECTION = "UP" then
                 dir_tmp := 1;       -- increment
              elsif LPM_DIRECTION = "DOWN" then
                 dir_tmp := 0;       -- decrement
              else
                 dir_tmp := 1;       -- illegal param value; increment
              end if;

              COUT <= '0';
              if vmodulus = 1 then
                 COUT <= '1';
              elsif CIN = '1' then
                 if (dir_tmp = 1 and COUNT >= vmodulus - 2)
                    or (dir_tmp = 0 and COUNT <= 1) then
                       COUT <= '1';
                 else
                 end if;
              else
                 if (dir_tmp = 1 and COUNT >= vmodulus - 1)
                    or (dir_tmp = 0 and COUNT = 0) then
                       COUT <= '1';
                 else
                 end if;
              end if;
           else
           end if;
        end process CarryOut;

        Q <= COUNT(LPM_WIDTH-1 downto 0);

end LPM_SYN;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

Library lava1;
USE lava1.components.all;

ENTITY L_DECODE IS

    GENERIC (LPM_WIDTH: positive;
             L_DECODES: positive;
             LPM_PIPELINE: integer;
             LPM_TYPE: string);
    PORT (DATA: IN std_logic_vector(LPM_WIDTH-1 downto 0);
          ACLR : IN std_logic;
          CLOCK: IN std_logic;
          ENABLE: IN std_logic;
          EQ   : OUT std_logic_vector(L_DECODES-1 downto 0));
END L_DECODE;

ARCHITECTURE LPM_SYN OF L_DECODE IS
type t_eqtmp IS ARRAY(0 to LPM_PIPELINE) of std_logic_vector(L_DECODES-1 downto 0);
    BEGIN
      PROCESS(ACLR, CLOCK, DATA, ENABLE)
      VARIABLE eqtmp: t_eqtmp;
        BEGIN
           if LPM_PIPELINE >= 0 then
              for i in 0 to L_DECODES-1 loop
                 if conv_integer(DATA) = i then
                    if ENABLE = '1' then
                      eqtmp(LPM_PIPELINE)(i) := '1';
                    else
                      eqtmp(LPM_PIPELINE)(i) := '0';
                    end if;
                 else
                    eqtmp(LPM_PIPELINE)(i) := '0';
                 end if;
              end loop;
              if LPM_PIPELINE > 0 then
                 if ACLR = '1' then
                    for i in 0 to LPM_PIPELINE loop
                       eqtmp(i) := (OTHERS => '0');
                    end loop;
                 elsif CLOCK'event and CLOCK = '1' then
                    eqtmp(0 to LPM_PIPELINE-1) := eqtmp(1 to LPM_PIPELINE);
                 end if;
              end if;
           end if;
           EQ <= eqtmp(0);
    END PROCESS;
END LPM_SYN;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

Library lava1;
USE lava1.components.all;

entity L_FIFO is
        generic (LPM_WIDTH : positive;
                 LPM_WIDTHU : natural;
                 LPM_PARITY_WIDTH : positive;
                 LPM_NUMWORDS : positive;
                 LPM_SHOWAHEAD : string;
                 LPM_TYPE : string;
                 LPM_HINT : string);
        port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
                  CLOCK : in std_logic;
                  WRREQ : in std_logic;
                  RDREQ : in std_logic;
                  ACLR : in std_logic;
                  SCLR : in std_logic;
                  Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
                  USEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);
                  FULL : out std_logic;
                  EMPTY : out std_logic);
end L_FIFO;

architecture LPM_SYN of L_FIFO is

type lpm_memory is array (lpm_numwords-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);

signal tmp_q : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => 'X');
signal read_id, write_id, count_id : integer := 0;
signal empty_flag : std_logic := '1';
signal full_flag : std_logic := '0';
constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => 'X');

begin

        process (clock, aclr)
        variable mem_data : lpm_memory := (OTHERS => ZEROS);

        begin
           if (aclr = '1') then
                tmp_q <= ZEROS;
                full_flag <= '0';
                empty_flag <= '1';
                read_id <= 0;
                write_id <= 0;
                count_id <= 0;
                if (lpm_showahead = "ON") then
                   tmp_q <= mem_data(0);
                end if;
           elsif (clock'event and clock = '1') then
                if (sclr = '1') then
                   tmp_q <= mem_data(read_id);
                   full_flag <= '0';
                   empty_flag <= '1';
                   read_id <= 0;
                   write_id <= 0;
                   count_id <= 0;
                   if (lpm_showahead = "ON") then
                        tmp_q <= mem_data(0);
                   end if;
                else
                   ----- IF BOTH READ AND WRITE -----
                   if (wrreq = '1' and full_flag = '0') and
                                (rdreq = '1' and empty_flag = '0') then
                        mem_data(write_id) := data;
                        if (write_id >= lpm_numwords-1) then
                           write_id <= 0;
                        else
                           write_id <= write_id + 1;
                        end if;

                        tmp_q <= mem_data(read_id);
                        if (read_id >= lpm_numwords-1) then
                           read_id <= 0;
                           if (lpm_showahead = "ON") then
                                tmp_q <= mem_data(0);
                           end if;
                        else
                           read_id <= read_id + 1;
                           if (lpm_showahead = "ON") then
                                tmp_q <= mem_data(read_id+1);
                           end if;
                        end if;

                   ----- IF WRITE (ONLY) -----
                   elsif (wrreq = '1' and full_flag = '0') then
                        mem_data(write_id) := data;
                        if (lpm_showahead = "ON") then
                           tmp_q <= mem_data(read_id);
                        end if;
                        count_id <= count_id + 1;
                        empty_flag <= '0';
                        if (count_id >= lpm_numwords-1) then
                           full_flag <= '1';
                           count_id <= lpm_numwords;
                        end if;
                        if (write_id >= lpm_numwords-1) then
                           write_id <= 0;
                        else
                           write_id <= write_id + 1;
                        end if;

                   ----- IF READ (ONLY) -----
                   elsif (rdreq = '1' and empty_flag = '0') then
                        tmp_q <= mem_data(read_id);
                        count_id <= count_id - 1;
                        full_flag <= '0';
                        if (count_id <= 1) then
                           empty_flag <= '1';
                           count_id <= 0;
                        end if;
                        if (read_id >= lpm_numwords-1) then
                           read_id <= 0;
                           if (lpm_showahead = "ON") then
                                tmp_q <= mem_data(0);
                           end if;
                        else
                           read_id <= read_id + 1;
                           if (lpm_showahead = "ON") then
                                tmp_q <= mem_data(read_id+1);
                           end if;
                        end if;
                   end if;  -- if WRITE and/or READ
                end if;  -- if sclr = '1'
           end if;  -- if aclr = '1'
        end process;

        q <= tmp_q;
        full <= full_flag;
        empty <= empty_flag;
        usedw <= conv_std_logic_vector(count_id, lpm_widthu);

end LPM_SYN;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;

Library lava1;
USE lava1.components.all;

entity L_MULT_SIGNED is
        generic (LPM_WIDTHA : positive;
                LPM_WIDTHB : positive;
                --LPM_WIDTHS : positive;
                LPM_WIDTHS : natural;
                LPM_WIDTHP : positive;
                LPM_PIPELINE : integer;
                LPM_TYPE: string;
                LPM_HINT : string);
        port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
                DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
                ACLR : in std_logic;
                CLOCK : in std_logic;
                --CLKEN : in std_logic;
                SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0);
                RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end L_MULT_SIGNED;

architecture LPM_SYN of L_MULT_SIGNED is

signal FP : std_logic_vector(LPM_WIDTHS-1 downto 0);
type t_resulttmp IS ARRAY (0 to LPM_PIPELINE) of std_logic_vector(LPM_WIDTHP-1 downto 0);

begin

        process (CLOCK, ACLR, DATAA, DATAB, SUM)
        variable resulttmp : t_resulttmp;
        begin
           if LPM_PIPELINE >= 0 then
                if LPM_WIDTHP >= LPM_WIDTHS then
                   if LPM_WIDTHS > 0 then
                        resulttmp(LPM_PIPELINE) := (DATAA * DATAB) + SUM;
                   else
                        resulttmp(LPM_PIPELINE) := (DATAA * DATAB);
                   end if;
                else
                   FP <= (DATAA * DATAB) + SUM;
                   resulttmp(LPM_PIPELINE) := FP(LPM_WIDTHS-1 downto LPM_WIDTHS-LPM_WIDTHP);
                end if;

                if LPM_PIPELINE > 0 then
                   if ACLR = '1' then
                        for i in 0 to LPM_PIPELINE loop
                           resulttmp(i) := (OTHERS => '0');
                        end loop;
                   elsif CLOCK'event and CLOCK = '1' then
                        resulttmp(0 to LPM_PIPELINE - 1) := resulttmp(1 to LPM_PIPELINE);
                   end if;
                end if;
           end if;

           RESULT <= resulttmp(0);
        end process;

end LPM_SYN;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

Library lava1;
USE lava1.components.all;

entity L_MULT_UNSIGNED is
        generic (LPM_WIDTHA : positive;
                 LPM_WIDTHB : positive;
                 --LPM_WIDTHS : positive;
                 LPM_WIDTHS : natural;
                 LPM_WIDTHP : positive;
                 LPM_PIPELINE : integer;
                 LPM_TYPE: string;
                 LPM_HINT : string);
        port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
                 DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
                 ACLR : in std_logic;
                 CLOCK : in std_logic;
                 --CLKEN : in std_logic;
                 SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0);
                 RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end L_MULT_UNSIGNED;

architecture LPM_SYN of L_MULT_UNSIGNED is

signal FP : std_logic_vector(LPM_WIDTHS-1 downto 0);
type t_resulttmp IS ARRAY (0 to LPM_PIPELINE) of std_logic_vector(LPM_WIDTHP-1 downto 0);

begin

        process (CLOCK, ACLR, DATAA, DATAB, SUM)
        variable resulttmp : t_resulttmp;
        begin
           if LPM_PIPELINE >= 0 then
                if LPM_WIDTHP >= LPM_WIDTHS then
                   if LPM_WIDTHS > 0 then
                        resulttmp(LPM_PIPELINE) := (DATAA * DATAB) + SUM;
                   else
                        resulttmp(LPM_PIPELINE) := (DATAA * DATAB);
                   end if;
                else
                   FP <= (DATAA * DATAB) + SUM;
                   resulttmp(LPM_PIPELINE) := FP(LPM_WIDTHS-1 downto LPM_WIDTHS-LPM_WIDTHP);
                end if;

                if LPM_PIPELINE > 0 then
                   if ACLR = '1' then
                        for i in 0 to LPM_PIPELINE loop
                           resulttmp(i) := (OTHERS => '0');
                        end loop;
                   elsif CLOCK'event and CLOCK = '1' then
                        resulttmp(0 to LPM_PIPELINE - 1) := resulttmp(1 to LPM_PIPELINE);
                   end if;
                end if;
           end if;

           RESULT <= resulttmp(0);
        end process;

end LPM_SYN;

library IEEE;
use IEEE.std_logic_1164.all;

Library lava1;
USE lava1.components.all;

entity L_MULT is
        generic (LPM_WIDTHA : positive;
                 LPM_WIDTHB : positive;
                 --LPM_WIDTHS : positive;
                 LPM_WIDTHS : natural;
                 LPM_WIDTHP : positive;
                 LPM_REPRESENTATION : string;
                 LPM_PIPELINE : integer;
                 LPM_TYPE: string;
                 LPM_HINT : string);
        port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
                 DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
                 ACLR : in std_logic;
                 CLOCK : in std_logic;
                 --CLKEN : in std_logic;
                 SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0);
                 RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end L_MULT;

architecture LPM_SYN of L_MULT is

        component L_MULT_UNSIGNED
                generic (LPM_WIDTHA : positive;
                         LPM_WIDTHB : positive;
                         --LPM_WIDTHS : positive;
                         LPM_WIDTHS : natural;
                         LPM_WIDTHP : positive;
                         LPM_PIPELINE : integer;
                         LPM_TYPE: string := "LPM_MULT";
                         LPM_HINT : string := "UNUSED");
                port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
                      DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
                      ACLR : in std_logic := '0';
                      CLOCK : in std_logic := '0';
                      --CLKEN : in std_logic := '1';
                      SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0);
                      RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
        end component;

        component L_MULT_SIGNED
                generic (LPM_WIDTHA : positive;
                         LPM_WIDTHB : positive;
                         --LPM_WIDTHS : positive;
                         LPM_WIDTHS : natural;
                         LPM_WIDTHP : positive;
                         LPM_PIPELINE : integer;
                         LPM_TYPE: string;
                         LPM_HINT : string);
                port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
                      DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
                      ACLR : in std_logic;
                      CLOCK : in std_logic;
                      --CLKEN : in std_logic;
                      SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0);
                      RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
        end component;

begin

L1: if LPM_REPRESENTATION = "UNSIGNED" generate

U1: L_MULT_UNSIGNED
        generic map (LPM_WIDTHA => LPM_WIDTHA,
                     LPM_WIDTHB => LPM_WIDTHB, LPM_WIDTHS => LPM_WIDTHS,
                     LPM_WIDTHP => LPM_WIDTHP, LPM_PIPELINE => LPM_PIPELINE,
                     LPM_TYPE => LPM_TYPE, LPM_HINT => LPM_HINT)
        port map (DATAA => DATAA, DATAB => DATAB, ACLR => ACLR,
                  SUM => SUM, CLOCK => CLOCK, RESULT => RESULT);
        end generate;

L2: if LPM_REPRESENTATION = "SIGNED" generate

U1: L_MULT_SIGNED
        generic map (LPM_WIDTHA => LPM_WIDTHA,
                     LPM_WIDTHB => LPM_WIDTHB, LPM_WIDTHS => LPM_WIDTHS,
                     LPM_WIDTHP => LPM_WIDTHP, LPM_PIPELINE => LPM_PIPELINE,
                     LPM_TYPE => LPM_TYPE, LPM_HINT => LPM_HINT)
        port map (DATAA => DATAA, DATAB => DATAB, ACLR => ACLR,
                  SUM => SUM, CLOCK => CLOCK, RESULT => RESULT);
        end generate;

end LPM_SYN;
Library IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;
Library lava1;
USE lava1.components.all;

ENTITY L_MUX IS

    GENERIC (LPM_WIDTH: positive;
             LPM_SIZE: positive;
             LPM_WIDTHS: positive;
             LPM_PIPELINE: integer;
             LPM_TYPE: string;
             LPM_HINT: string);
    PORT (DATA: IN std_logic_2d(LPM_SIZE-1 downto 0, LPM_WIDTH-1 downto 0);
          ACLR : IN std_logic;
          CLOCK: IN std_logic;
          SEL  : IN std_logic_vector(LPM_WIDTHS-1 downto 0);
          RESULT: OUT std_logic_vector(LPM_WIDTH-1 downto 0));
END L_MUX;

ARCHITECTURE LPM_SYN OF L_MUX IS
type t_resulttmp IS ARRAY(0 to LPM_PIPELINE) of std_logic_vector(LPM_WIDTH-1 downto 0);
    BEGIN
      PROCESS(ACLR, CLOCK, SEL, DATA)
      VARIABLE resulttmp: t_resulttmp;
      VARIABLE ISEL: integer;
        BEGIN
           if LPM_PIPELINE >= 0 then
              ISEL := conv_integer(SEL);
              for i in 0 to LPM_WIDTH-1 loop
                 resulttmp(LPM_PIPELINE)(i) := DATA(ISEL, i);
              end loop;
              if LPM_PIPELINE > 0 then
                 if ACLR = '1' then
                    for i in 0 to LPM_PIPELINE loop
                       resulttmp(i) := (OTHERS => '0');
                    end loop;
                 elsif CLOCK'event and CLOCK = '1' then
                    resulttmp(0 to LPM_PIPELINE-1) := resulttmp(1 to LPM_PIPELINE);
                 end if;
              end if;
              RESULT <= resulttmp(0);
           end if;
    END PROCESS;
END LPM_SYN;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lava1;
use lava1.components.all;
    
entity l_ram_dp is
  generic(
	   module_type             : string := "LPM_RAM_DP";
	   module_widthw           : integer := 1;
	   module_widthr           : integer := 1;
	   module_numwordsw        : integer := 1;
	   module_widthadw         : integer := 1;
	   module_widthadr         : integer := 1;
   	   module_numwordsr        : integer := 1;
  	   module_indata           : string := "REGISTERED";
	   module_outdata          : string := "UNREGISTERED";
    	   module_addressw_control : string := "REGISTERED";
	   module_addressr_control : string := "REGISTERED";
	   module_hint             : string := "UNUSED";
           module_init_file        : string := "");


  port(
           Data        : in  std_logic_vector (module_widthw-1 downto 0);
           WrAddress   : in  std_logic_vector (module_widthadw-1 downto 0);
           RdAddress   : in  std_logic_vector (module_widthadr-1 downto 0);
           WrClock     : in std_logic;
           WrClockEn   : in std_logic;
           RdClock     : in std_logic;
           RdClockEn   : in std_logic;
           WE          : in std_logic;
           Reset       : in std_logic;
           Q           : out std_logic_vector (module_widthr-1 downto 0));

end l_ram_dp;

architecture fun_simulation of l_ram_dp is

component SC_PDPRAM_16K_L

  generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        WADDR_WIDTH    : integer := 13;
        WDATA_WIDTH    : integer := 2;
        RADDR_WIDTH    : integer := 13;
        RDATA_WIDTH    : integer := 2;
        ARRAY_SIZE     : integer := 511; 
        MEM_INIT_FLAG  : integer := 0;  
	MEM_INIT_FILE  : string  := "mem_init_file"

        );

  port (
        WCEN : in  STD_LOGIC ;
        WCLK : in  STD_LOGIC ;
        WE   : in  STD_LOGIC ;
        WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
        RCLK : in  STD_LOGIC;
        RCEN : in  STD_LOGIC;
        RST  : in  STD_LOGIC ;

        WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
        RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);  
        RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
       ); 

end component;

     signal cs        : std_logic_vector ( 1 downto 0);
     signal Q_K       : std_logic_vector (module_widthr-1 downto 0);
     signal Q_K_reg   : std_logic_vector (module_widthr-1 downto 0);
     CONSTANT  module_init_flag       :  integer := init_flag(module_init_file);

  begin

     cs <= "11";

      OutRegister : process(RdClock, Reset)
       begin
           if (Reset = '1') then 
                Q_K_reg <= (others => '0');
           elsif (RdClock'EVENT and RdClock = '1') then
              if (RdClockEn = '1') then
                Q_K_reg <= Q_K;
              elsif (RdClockEn /= '0') then
                Q_K_reg <= (others => 'X');
              end if;
           end if;
       end process;

      SelectOut  : process (Q_K , Q_K_reg)
        begin
              if(module_outdata = "UNREGISTERED" and module_addressr_control = "REGISTERED") then 
                     Q <= Q_K;
              elsif(module_outdata = "REGISTERED" and module_addressr_control = "REGISTERED") then
                     Q <= Q_K_reg;
              elsif(module_indata = "UNREGISTERED") then
                    assert false report "Error: module_indata should be REGISTERED" severity ERROR;
              elsif(module_addressw_control = "UNREGISTERED") then
                    assert false report "Error: module_addressw_control should be REGISTERED" severity ERROR;
              elsif(module_addressr_control = "UNREGISTERED") then
                    assert false report "Error: module_addressr_control should be REGISTERED" severity ERROR;
              end if;
        end process;


   PDPRAM_inst : SC_PDPRAM_16K_L

  generic map(

        DEVICE_FAMILY  => open,
        WADDR_WIDTH    => module_widthadw,
        WDATA_WIDTH    => module_widthw,
        RADDR_WIDTH    => module_widthadr,
        RDATA_WIDTH    => module_widthr,
        MEM_INIT_FLAG  => module_init_flag,  
        ARRAY_SIZE     => module_numwordsw*module_widthw,
	MEM_INIT_FILE  => module_init_file)

  port map(
        WCEN =>  WrClockEn,
        WCLK =>  WrClock,
        WE   =>  WE,
        WCS  =>  cs,
        RCLK =>  RdClock,
        RCEN =>  RdClockEn,
        RST  =>  Reset,

        WD   =>  Data,
        WAD  =>  WrAddress,
        RAD  =>  RdAddress,
        RD   => Q_K 
       ); 
end;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lava1;
use lava1.components.all;

entity l_ram_dpx is 
generic (
              LPM_TYPE      : string := "LPM_RAM_DPX";
              LPM_WIDTHA    : positive;
              LPM_WIDTHADA  : positive;
              LPM_NUMWORDSA : positive;
              LPM_WIDTHB    : positive;
              LPM_WIDTHADB  : positive;
              LPM_NUMWORDSB : positive;
              LPM_INDATA    : string :="REGISTERED";
              LPM_OUTDATA   : string :="REGISTERED";
              LPM_ADDRESSA_CONTROL   : string :="UNREGISTERED";
              LPM_ADDRESSB_CONTROL   : string :="UNREGISTERED";
              lpm_init_file        : string := "";
              LPM_HINT      : string :="UNUSED");
      port (  
              DataInA       : in std_logic_vector(LPM_WIDTHA-1 downto 0);
              AddressA      : in std_logic_vector(LPM_WIDTHADA-1 downto 0);
              DataInB       : in std_logic_vector(LPM_WIDTHB-1 downto 0);
              AddressB      : in std_logic_vector(LPM_WIDTHADB-1 downto 0);
              ClockA        : in std_logic := '0';
              ClockEnA      : in std_logic := '0';
              ClockB        : in std_logic := '0';
              ClockEnB      : in std_logic := '0';
              WrA           : in std_logic;
              WrB           : in std_logic;
              ResetA        : in std_logic;
              ResetB        : in std_logic;
              QA            : out std_logic_vector(LPM_WIDTHA-1 downto 0);
              QB            : out std_logic_vector(LPM_WIDTHB-1 downto 0));
end l_ram_dpx;

architecture fun_simulation of l_ram_dpx is

component SC_DPRAM_16K_L
  generic (
        DEVICE_FAMILY  : string  := "LAVA1";
        ADDR_WIDTH_A     : integer := 13;
        DATA_WIDTH_A     : integer := 2;
        ADDR_WIDTH_B     : integer := 14;
        DATA_WIDTH_B     : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        ARRAY_SIZE     : integer := 511; 
	MEM_INIT_FILE  : string  := "mem_init_file"
        );
  port (
        CENA : in  STD_LOGIC ;
        CLKA : in  STD_LOGIC ;
        WRA  : in  STD_LOGIC ;
        CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
        RSTA : in  STD_LOGIC ;
        DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
        ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
        DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

        CENB : in  STD_LOGIC ;
        CLKB : in  STD_LOGIC ;
        WRB  : in  STD_LOGIC ;
        CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
        RSTB : in  STD_LOGIC ;
        DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
        ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
        DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
        ); 

end component;

      signal CS : std_logic_vector ( 1 downto 0);
      signal QA_int, QA_int_reg  : std_logic_vector(LPM_WIDTHA-1 downto 0);
      signal QB_int, QB_int_reg  : std_logic_vector(LPM_WIDTHB-1 downto 0);
      CONSTANT  module_init_flag       :  integer := init_flag(lpm_init_file);

begin

      CS <= "11";

      OutRegisterA : process(ClockA, ResetA)
       begin
           if(ResetA = '1') then QA_int_reg <= (others => '0');
           elsif (ClockA'EVENT and ClockA = '1') then
               QA_int_reg <= QA_int;
           end if;
       end process;

      OutRegisterB : process(ClockB, ResetB)
       begin
           if(ResetB = '1') then QB_int_reg <= (others => '0');
           elsif (ClockB'EVENT and ClockB = '1') then
               QB_int_reg <= QB_int;
           end if;
       end process;

      SelectA   : process (QA_int , QA_int_reg)
        begin
              if(ResetA = '1') then
                     QA <= (others => '0');
              elsif(lpm_outdata = "REGISTERED" and lpm_addressa_control = "UNREGISTERED")  then
                     QA <= QA_int;
              elsif(lpm_outdata = "REGISTERED" and lpm_addressa_control = "REGISTERED") then
                     QA <= QA_int_reg;
              end if;
        end process;

      SelectB   : process (QB_int , QB_int_reg)
        begin
              if(ResetB = '1') then
                     QB <= (others => '0');
              elsif(lpm_outdata = "REGISTERED" and lpm_addressb_control = "UNREGISTERED") then
                     QB <= QB_int;
              elsif(lpm_outdata = "REGISTERED" and lpm_addressb_control = "REGISTERED") then
                     QB <= QB_int_reg;
              end if;
       end process;

RAM_DP_INST : SC_DPRAM_16K_L

    generic map(
         DEVICE_FAMILY  => open ,
         ADDR_WIDTH_A  => LPM_WIDTHADA,
         DATA_WIDTH_A  => LPM_WIDTHA,
         ADDR_WIDTH_B  => LPM_WIDTHADB,
         DATA_WIDTH_B  => LPM_WIDTHB,
  	 MEM_INIT_FLAG => module_init_flag,  
         ARRAY_SIZE    => lpm_numwordsa*lpm_widtha,
	 MEM_INIT_FILE  => lpm_init_file
       )
    port map (
         CENA => ClockEnA,
         CLKA => ClockA,
         WRA  => WrA,
         CSA  => CS,
         RSTA => ResetA,
         DIA  => DataInA,
         ADA  => AddressA,
         DOA  => QA_int,

         CENB => ClockEnB,
         CLKB => ClockB,
         WRB  => WrB,
         CSB  => CS,
         RSTB => ResetB,
         DIB  => DataInB,
         ADB  => AddressB,
         DOB  => QB_int
      );
end;



library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lava1;
use lava1.components.all;

entity l_ram_dq  is
  generic(
	   module_type            : string  := "LPM_RAM_DQ";
	   module_width           : integer := 1;
	   module_numwords        : integer := 1;
	   module_widthad         : integer := 1;
  	   module_indata          : string  := "REGISTERED";
	   module_outdata         : string  := "UNREGISTERED";
	   module_address_control : string  := "REGISTERED";
           module_init_file       : string := "";
	   module_hint            : string  := "UNUSED");

  port(

           Data                : in  std_logic_vector (module_width-1 downto 0);
           Address             : in  std_logic_vector (module_widthad-1 downto 0);
           Clock               : in  std_logic;
           ClockEn             : in  std_logic;
           WE                  : in  std_logic;
           Reset               : in  std_logic;
           Q                   : out std_logic_vector (module_width-1 downto 0));
  end l_ram_dq;


architecture fun_simulation of l_ram_dq is


  component SC_SPRAM_16K_L

  generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        MEM_INIT_FLAG  : integer := 1; 
        ARRAY_SIZE     : integer := 511; 
	MEM_INIT_FILE  : string  := "qq.dat"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end component;

    signal cs   : std_logic_vector (1 downto 0);
    signal Q_K       : std_logic_vector (module_width-1 downto 0);
    signal Q_K_reg   : std_logic_vector (module_width-1 downto 0);
    CONSTANT  module_init_flag       :  integer := init_flag(module_init_file);

  begin

      cs <= "11";

      OutRegister : process(Clock, Reset)
       begin
           if (Reset = '1') then 
               Q_K_reg <= (others => '0');
           elsif (Clock'EVENT and Clock = '1') then
              if (ClockEn = '1') then
               Q_K_reg <= Q_K;
              elsif (ClockEn /= '0') then
               Q_K_reg <= (others => 'X');
              end if;
           end if;
       end process;

      SelectOut  : process (Q_K , Q_K_reg)
        begin
              if(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
                     Q <= Q_K;
              elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
                     Q <= Q_K_reg;
              elsif(module_indata = "UNREGISTERED") then
                    assert false report "Error: module_indata should be REGISTERED" severity ERROR;
              elsif(module_address_control = "UNREGISTERED") then
                    assert false report "Error: module_address_control should be REGISTERED" severity ERROR;
              end if;
        end process;

  SPRAM_inst : SC_SPRAM_16K_L

  generic map (

        DEVICE_FAMILY  => open,
        ADDR_WIDTH     => module_widthad,
        DATA_WIDTH     => module_width,
        MEM_INIT_FLAG  => module_init_flag,
        ARRAY_SIZE     => module_numwords * module_width,
	MEM_INIT_FILE  => module_init_file)

  port map (
        CEN  => ClockEn, 
        CLK  => Clock, 
         WR  => WE, 
         CS  => cs,
        RST  => Reset,
         DI  => Data,
         AD  => Address,
         DO  => Q_K
       ); 
end;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lava1;
use lava1.components.all;

entity l_rom is
  generic (
	    module_type               : string  := "LPM_ROM";
	    module_width              : integer := 1;
	    module_numwords           : integer := 1;
	    module_widthad            : integer := 1;
	    module_outdata            : string  := "REGISTERED";
	    module_address_control    : string  := "REGISTERED";
            module_init_file          : string := "init_file";
	    module_hint               : string  := "UNUSED");
  port (
            Address       : in  std_logic_vector (module_widthad-1 downto 0);
            OutClock      : in  std_logic;
            OutClockEn    : in  std_logic;
            Reset         : in  std_logic;
            Q             : out std_logic_vector (module_width-1 downto 0));
end l_rom;

architecture fun_simulation of l_rom is

  component  SC_SPRAM_16K_L

    generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        ARRAY_SIZE     : integer := 511; 
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "qq.dat"

	);

    port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

  end component;

        signal cs : std_logic_vector ( 1 downto 0);
        signal DI_sig : std_logic_vector (module_width-1 downto 0);
        signal WE_sig : std_logic;

        signal Q_K       : std_logic_vector (module_width-1 downto 0);
        signal Q_K_reg   : std_logic_vector (module_width-1 downto 0);

        CONSTANT  module_init_flag       :  integer := init_flag(module_init_file);

  begin

        cs <= "11";
        WE_sig <= '0';

      OutRegister : process(OutClock, Reset)
       begin
           if (Reset = '1') then 
               Q_K_reg <= (others => '0');
           elsif (OutClock'EVENT and OutClock = '1') then
              if(OutClockEn = '1') then
               Q_K_reg <= Q_K;
              elsif(OutClockEn /= '0') then
               Q_K_reg <= (others => 'X' );
              end if;
           end if;
       end process;

      SelectOut  : process (Q_K , Q_K_reg)
        begin
              if(module_outdata = "UNREGISTERED" and module_address_control = "REGISTERED") then
                     Q <= Q_K;
              elsif(module_outdata = "REGISTERED" and module_address_control = "REGISTERED") then
                     Q <= Q_K_reg;
              elsif(module_address_control = "UNREGISTERED") then
                    assert false report "Error: module_address_control should be REGISTERED" severity ERROR;
              end if;
        end process;

    SPRAM_inst :  SC_SPRAM_16K_L

      generic map(

           DEVICE_FAMILY  =>  open,
           ADDR_WIDTH     =>  module_widthad,
           DATA_WIDTH     =>  module_width, 
           MEM_INIT_FLAG  =>  module_init_flag,
           ARRAY_SIZE     =>  module_numwords * module_width,
	   MEM_INIT_FILE  =>  module_init_file)

      port map(
           CEN    =>  OutClockEn,
           CLK    =>  OutClock,
           WR     =>  WE_sig,
           CS     =>  cs,
           RST    =>  Reset,
           DI     =>  DI_sig,
           AD     =>  Address,
           DO     =>  Q_K
       ); 
end;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

Library lava1;
USE lava1.components.all;

entity LPM_SHIFTREG is
        generic (LPM_WIDTH : positive;
           LPM_SHIFT_VALUE : integer;
           LPM_AVALUE : string;
           LPM_SVALUE : string;
           LPM_PVALUE : string;
           LPM_DIRECTION: string;
           LPM_TYPE: string;
           LPM_HINT : string);
        port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
              CLOCK : in std_logic;
              ENABLE : in std_logic;
              SHIFTIN : in std_logic;
              LOAD : in std_logic;
              SCLR : in std_logic;
              SSET : in std_logic;
              ACLR : in std_logic;
              ASET : in std_logic;
              Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
              SHIFTOUT : out std_logic);
end LPM_SHIFTREG;

architecture LPM_SYN of LPM_SHIFTREG is

signal INIT : std_logic := '0';

begin

        process (CLOCK, ACLR, ASET, SCLR)
        variable so_tmp : std_logic_vector(LPM_SHIFT_VALUE downto 0);
        variable IAVALUE, ISVALUE : integer;
        variable IQ : std_logic_vector(LPM_WIDTH-1 downto 0);
        begin
           -- INITIALIZE TO PVALUE --
           if INIT = '0' then
                if LPM_PVALUE /= "UNUSED" then
                   IQ := conv_std_logic_vector(Str2int(LPM_PVALUE), LPM_WIDTH);
                else
                   IQ := (OTHERS => 'X');
                end if;
                so_tmp := (OTHERS => '1');
                INIT <= '1';
           elsif ACLR =  '1' then
                IQ := (OTHERS => '0');
           elsif ASET = '1' then
                if LPM_AVALUE = "UNUSED" then
                   IQ := (OTHERS => '1');
                else
                   IAVALUE := Str2int(LPM_AVALUE);
                   IQ := conv_std_logic_vector(IAVALUE, LPM_WIDTH);
                end if;
           elsif CLOCK'event and CLOCK = '1' then
                if ENABLE = '1' then
                   if SCLR = '1' then
                        IQ := (OTHERS => '0');
                   elsif SSET = '1' then
                        if LPM_SVALUE = "UNUSED" then
                           IQ := (OTHERS => '1');
                        else
                           ISVALUE := Str2int(LPM_SVALUE);
                           IQ := conv_std_logic_vector(ISVALUE, LPM_WIDTH);
                        end if;
                   elsif LOAD = '0' then
                      if LPM_DIRECTION = "LEFT" then
                        IQ := IQ(LPM_WIDTH-2 downto 0) & SHIFTIN;
                      else
                        IQ := SHIFTIN & IQ(LPM_WIDTH-1 downto 1);
                      end if;
                   else
                      IQ :=  DATA;
                   end if;
                   if LPM_SHIFT_VALUE > 0 then
                        so_tmp := SHIFTIN & so_tmp(LPM_SHIFT_VALUE downto 1);
                   end if;
                end if;
           end if;
           Q <= IQ;
           if LPM_SHIFT_VALUE > 0 then
                        SHIFTOUT <= so_tmp(0);
           else
                if LPM_DIRECTION = "LEFT" then
                   SHIFTOUT <= IQ(LPM_WIDTH-1);
                else
                        SHIFTOUT <= IQ(0);
                end if;
           end if;
        end process;

end LPM_SYN;

--------New set of L model-----------------
-- ************************************************************************
--
--  Block Memory: Behavioral Model
--  The kernel of other RAM applications  
-- ************************************************************************
--
--  Filename:  SC_BLOCK_RAM_L.vhd
--  Description: BRAM behavioral model. 
-- ************************************************************************
library std;
use std.textio.all;

library ieee, std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;


-- ************************************************************************
-- Entity definition  
-- "generic" members 
-- ************************************************************************

entity SC_BRAM_16K_L_SYNC is

  generic (

	 DEVICE_FAMILY : string  := "LAVA1";

         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 262144;       
	 MEM_INIT_FLAG : integer := 0;  
	 MEM_INIT_FILE : string  := ""

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
         WCLK : in  STD_LOGIC;
         RCLK : in  STD_LOGIC
	); 

end SC_BRAM_16K_L_SYNC;

-- ************************************************************************
-- Architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_BRAM_16K_L_SYNC is


procedure READ_MEM_INIT_FILE(
                              f_name : IN    STRING;
                              v_MEM  : OUT   STD_LOGIC_VECTOR
                             ) IS

    file     f_INIT_FILE   : TEXT is MEM_INIT_FILE;
    variable v_WORD        : line;
    variable v_GOODFLAG    : boolean;
    variable v_WORD_BIT    : string (WDATA_WIDTH_A downto 1) ;
    variable v_CHAR        : character;
    variable v_OFFSET      : integer := 0;
    variable v_LINE        : integer := 0;

    begin      
      
      while ( not(endfile(f_INIT_FILE)) and (v_LINE < ARRAY_SIZE)) loop

      readline(f_INIT_FILE, v_WORD);
      read(v_WORD, v_WORD_BIT, v_GOODFLAG);

      for k in 0 to WDATA_WIDTH_A - 1 loop
        v_CHAR := v_WORD_BIT (k + 1);
        if (v_CHAR = '1') then
          v_MEM(v_OFFSET + k) := '1';

	elsif (v_CHAR = '0') then
          v_MEM(v_OFFSET + k) := '0';

--	else 
--          v_MEM(v_OFFSET + k) := 'X';

	end if;
      end loop;

      v_LINE := v_LINE + 1;
      v_OFFSET := v_OFFSET + WDATA_WIDTH_A;

    end loop;

  end READ_MEM_INIT_FILE;

--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Address (
    IN_ADDR : in std_logic_vector
 ) return boolean is

    variable v_Valid_Flag : boolean := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Address;

--------------------------------------------------------------------------
-- Signal Declaration
--------------------------------------------------------------------------

--------- Local signals used to propagate input wire delay ---------------

signal WADA_node   : std_logic_vector( WADDR_WIDTH_A -1 downto 0) := (others => '0');
signal WEA_node    : std_logic := 'X';
signal WDA_node    : std_logic_vector( WDATA_WIDTH_A -1 downto 0) := (others => 'X');
signal RADA_node   : std_logic_vector( RADDR_WIDTH_A -1 downto 0) := (others => '0');
signal REA_node    : std_logic := 'X';
signal RDA_node    : std_logic_vector( RDATA_WIDTH_A -1 downto 0) := (others => 'X');

signal WADB_node   : std_logic_vector( WADDR_WIDTH_B -1 downto 0) := (others => '0');
signal WEB_node    : std_logic := 'X';
signal WDB_node    : std_logic_vector( WDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal RADB_node   : std_logic_vector( RADDR_WIDTH_B -1 downto 0) := (others => '0');
signal REB_node    : std_logic := 'X';
signal RDB_node    : std_logic_vector( RDATA_WIDTH_B -1 downto 0) := (others => 'X');
signal WCLK_node   : std_logic := 'X';
signal RCLK_node   : std_logic := 'X';
-- architecture
begin 

 WADA_node <= WADA;
 WEA_node  <= WEA;
 WDA_node  <= WDA;
 RADA_node <= RADA;
 REA_node  <= REA;
 RDA       <= RDA_node;
 
 WADB_node <= WADB;
 WEB_node  <= WEB;
 WDB_node  <= WDB;
 RADB_node <= RADB;
 REB_node  <= REB;
 RDB       <= RDB_node;

 WCLK_node <= WCLK;
 RCLK_node <= RCLK;

-----------------------------------------
--------- Behavior process  -------------
-----------------------------------------


  --KERNEL_BEHAV : process( WADA_node, WEA_node, WDA_node, RADA_node, REA_node, WADB_node, WEB_node, WDB_node, RADB_node, REB_node)
KERNEL_BEHAV : process( WCLK_node, RCLK_node)

--TSPEC: A note about sram initial values and rom mode: 
--       If the user does not provide any values, ... default 0 
--       for all ram locations in JECED
    variable v_MEM         : std_logic_vector(ARRAY_SIZE*WDATA_WIDTH_A - 1 downto 0) := ( others => '0' ); 
    variable v_INI_DONE    : boolean := FALSE;
    variable v_WADDR_A     : integer;
    variable v_RADDR_A     : integer;
    variable v_WADDR_B     : integer;
    variable v_RADDR_B     : integer;

    variable v_WADDRA_Valid_Flag : boolean := TRUE;
    variable v_WADDRB_Valid_Flag : boolean := TRUE;
    variable v_RADDRA_Valid_Flag : boolean := TRUE;
    variable v_RADDRB_Valid_Flag : boolean := TRUE;

  begin -- Process
   
    if( MEM_INIT_FLAG = 1 and v_INI_DONE = FALSE) THEN
	READ_MEM_INIT_FILE(MEM_INIT_FILE, v_MEM);
	v_INI_DONE := TRUE;
    end if;

  -- Address Check    
    v_WADDRA_Valid_Flag := Valid_Address(WADA_node);	
    v_WADDRB_Valid_Flag := Valid_Address(WADB_node);
    v_RADDRA_Valid_Flag := Valid_Address(RADA_node);	
    v_RADDRB_Valid_Flag := Valid_Address(RADB_node);

    if ( v_WADDRA_Valid_Flag = TRUE ) then
 	v_WADDR_A := CONV_INTEGER(WADA_node);
--    else	
--      assert (Now = 0 ps) 
--        report "Write AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_WADDRB_Valid_Flag = TRUE ) then
      v_WADDR_B := CONV_INTEGER(WADB_node);
    else
--      assert (Now = 0 ps)
--        report "Write AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRA_Valid_Flag = TRUE ) then
      v_RADDR_A := CONV_INTEGER(RADA_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressA of Port contains invalid bit!"
--        severity warning;
    end if;	

    if (v_RADDRB_Valid_Flag = TRUE ) then
      v_RADDR_B := CONV_INTEGER(RADB_node);
--    else
--      assert (Now = 0 ps)
--        report "Read AddressB of Port contains invalid bit!"
--        severity warning;
    end if;	

  -- CHECK Operation
    if (WEA = '1' and WEB = '1' and 
         not( 
          (v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) < (v_WADDR_B*WDATA_WIDTH_B) 
                         or
          (v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) < (v_WADDR_A*WDATA_WIDTH_A)
         )
        ) then
      assert false
        report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
        severity warning;
    end if;  

  -- MEM Operation	
    if (WEA_node = '1' and WCLK_node'event and WCLK_node = '1' ) then
        v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
    end if;

    if (WEB_node = '1' and WCLK_node'event and WCLK_node = '1') then
        v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
    end if;

    if (REA_node = '1' and RCLK_node'event and RCLK_node = '1') then
       RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
--    else
--       RDA_node <= ( others => 'X');
    end if;
    
    if (REB_node = '1' and RCLK_node'event and RCLK_node = '1') then
       RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
--    else
--       RDB_node <= ( others => 'X');
    end if;
    
  end process KERNEL_BEHAV;
    
end LATTICE_BEHAV;

-- ************************************************************************
--
--  FIFO: Behavioral Model
-- ************************************************************************
--
--  Filename:  SC_FIFO.vhd
--  Description: FIFO behavioral model. 
--     
-- ************************************************************************
-- FIFO COMPONENTS READ_POINTER_CTRL
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity READ_POINTER_CTRL is
	generic (
              RPOINTER_WIDTH : integer := 9
		);
	port (
                TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
		GLOBAL_RST   : in STD_LOGIC ;
                RESET_RP     : in STD_LOGIC ;
                READ_EN      : in STD_LOGIC ;
                READ_CLK     : in STD_LOGIC ;
	        EMPTY_FLAG   : in STD_LOGIC ;
		READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
	     );
end READ_POINTER_CTRL;

architecture LATTICE_BEHAV of READ_POINTER_CTRL is

  signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');

begin

  READ_POINTER <= s_READ_POINTER; 

process  (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)

	variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');

begin

	if GLOBAL_RST = '1'  or RESET_RP = '1' then 

          s_READ_POINTER <= (others => '0');

	elsif (READ_CLK'EVENT and READ_CLK = '1') then
		if (READ_EN = '1' and EMPTY_FLAG = '1') then
                  v_READ_POINTER := s_READ_POINTER + '1';
                else  
                  v_READ_POINTER := s_READ_POINTER;
		end if;

		if (v_READ_POINTER = TERMINAL_COUNT + 1) then
		   s_READ_POINTER <= (others => '0');
		else
		   s_READ_POINTER <= v_READ_POINTER;
		end if;
	end if;

end process;
end LATTICE_BEHAV;

-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity WRITE_POINTER_CTRL is
        generic (
                WPOINTER_WIDTH : integer := 9;
                WDATA_WIDTH : integer := 32
		);
        port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
		GLOBAL_RST    : in STD_LOGIC ;
                WRITE_EN      : in STD_LOGIC ;
                WRITE_CLK     : in STD_LOGIC ;
                FULL_FLAG     : in STD_LOGIC ;
                WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
            
	     );
end WRITE_POINTER_CTRL;

architecture LATTICE_BEHAV of WRITE_POINTER_CTRL is

 signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');

begin 

  WRITE_POINTER <= s_WRITE_POINTER;

  process  (GLOBAL_RST, WRITE_EN, WRITE_CLK)

    variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');

begin
	if GLOBAL_RST = '1'  then 
		s_WRITE_POINTER <= (others => '0'); 

	elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
		if (WRITE_EN = '1' and FULL_FLAG /= '1') then
		   v_WRITE_POINTER := s_WRITE_POINTER + '1';
                else
		   v_WRITE_POINTER := s_WRITE_POINTER ;
                end if; 

		if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
		   s_WRITE_POINTER <= (others => '0');
		else
		   s_WRITE_POINTER <= v_WRITE_POINTER;
		end if;
	end if;
end process;
end LATTICE_BEHAV;

-- ************************************************************************
-- FIFO COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity FLAG_LOGIC is
 	generic (
                WPOINTER_WIDTH : integer := 9;
                RPOINTER_WIDTH : integer := 9;
                WDATA_WIDTH    : integer := 32; 
                RDATA_WIDTH    : integer := 32; 
                AMFULL_X      : integer := 1;
                AMEMPTY_Y     : integer := 1
		);
	port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0) := (others => '0');--QQ
		R_POINTER  : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
                W_POINTER  : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0');
                GLOBAL_RST : in STD_LOGIC ;
                READ_EN    : in STD_LOGIC ;
                READ_CLK   : in STD_LOGIC ;
                WRITE_EN   : in STD_LOGIC ;
                WRITE_CLK  : in STD_LOGIC ; 
                FULL_D     : out STD_LOGIC ;
                EMPTY_D    : out STD_LOGIC ;
                AMFULL_D   : out STD_LOGIC ;
                AMEMPTY_D  : out STD_LOGIC 
	);
end FLAG_LOGIC;

architecture LATTICE_BEHAV of FLAG_LOGIC is
--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Pointer (
    IN_ADDR : in STD_LOGIC_VECTOR
 ) return BOOLEAN is

    variable v_Valid_Flag : BOOLEAN := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Pointer;

--------------------------------------------------------------------------
-- Function: Calculate_Offset 
-- Description: 
--------------------------------------------------------------------------
function Calculate_Offset (
    IN_TC : in  STD_LOGIC_VECTOR;
    TC_LENGTH: in INTEGER
 ) return STD_LOGIC_VECTOR is

    variable vTC_FULL: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '1');
    variable vTC_TEMP: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
    variable vOFFSET : STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
begin
    vTC_TEMP := IN_TC;
    vOFFSET := vTC_FULL-vTC_TEMP;
    return vOFFSET;
end Calculate_Offset;
   
begin 

--------------------------------------------------------------------------
-- Function: Main Process 
-- Description: 
--------------------------------------------------------------------------
FULL_AMFULL: process  (GLOBAL_RST, WRITE_EN, WRITE_CLK, W_POINTER, R_POINTER)
    variable v_WP_Valid_Flag : boolean := TRUE;
    variable v_RP_Valid_Flag : boolean := TRUE;
    --variable v_WP_Check_FULL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
    variable v_WP_Check_AMFL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
    variable v_WP_Check_AMFL_TMP1 : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
    variable v_WP_Check_FULL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
    variable v_WP_Check_AMFL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ

begin
        v_WP_Valid_Flag := Valid_Pointer(W_POINTER);	
        v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
	if( v_WP_Valid_Flag = TRUE) then
             v_WP_Check_AMFL_TMP := W_POINTER + AMFULL_X + 1;
        end if;

        v_WP_Check_AMFL_TMP1 := v_WP_Check_AMFL_TMP + Calculate_Offset(TERMINAL_COUNT, WPOINTER_WIDTH);

	if ( v_WP_Valid_Flag = TRUE and W_POINTER = TERMINAL_COUNT ) then 
	    v_WP_Check_FULL := (others => '0');
	elsif( v_WP_Valid_Flag = TRUE ) then 
	    v_WP_Check_FULL := W_POINTER + 1; 
	end if;

	if GLOBAL_RST = '1'  then 
	    FULL_D <= '0';
	    AMFULL_D <= '0';

	elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then

	    if R_POINTER = v_WP_Check_FULL then
	     FULL_D <= '1';
            else
	     FULL_D <= '0';	
            end if;

            if (W_POINTER > R_POINTER) then
	      if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
                if v_WP_Check_AMFL_TMP1 >= R_POINTER then
	         AMFULL_D <= '1';
	        else
	         AMFULL_D <= '0'; 	
	        end if; 
              else 
	         AMFULL_D <= '0'; 	
              end if;    
            elsif (W_POINTER < R_POINTER) then
	      if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
	         AMFULL_D <= '1';
	      elsif (v_WP_Check_AMFL_TMP >= R_POINTER) then
	         AMFULL_D <= '1';
	      else 
	         AMFULL_D <= '0'; 	
	      end if; 
            end if;    

        end if;

end process FULL_AMFULL;

EMPTY_AMEMPTY: process  (GLOBAL_RST, READ_EN, READ_CLK, W_POINTER, R_POINTER)
    variable v_WP_Valid_Flag : boolean := TRUE;
    variable v_RP_Valid_Flag : boolean := TRUE;
    variable v_RP_Check_EMPT_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
    variable v_RP_Check_AMET_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
    variable v_RP_Check_AMET_TMP1 : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
    --variable v_RP_Check_EMPT : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
    variable v_RP_Check_AMET : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ

begin
        v_WP_Valid_Flag := Valid_Pointer(W_POINTER);	
        v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
	if( v_RP_Valid_Flag = TRUE and v_WP_Valid_Flag = TRUE) then
	    v_RP_Check_AMET_TMP := R_POINTER + AMEMPTY_Y ; -- Different from TSPEC QQ 07 17,2002
        end if;
        v_RP_Check_AMET_TMP1 := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);

	if GLOBAL_RST = '1'  then 
	  EMPTY_D <= '0';
	  AMEMPTY_D <= '0';
	elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then
            if R_POINTER  = W_POINTER then   -- Different from TSPEC QQ 07 17,2002
                    EMPTY_D <= '0';
            else
                    EMPTY_D <= '1';
            end if;

	    
	    if (W_POINTER < R_POINTER) then
	      if (v_RP_Check_AMET_TMP1 < R_POINTER) then
	          v_RP_Check_AMET := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);
                if v_RP_Check_AMET >= W_POINTER then
	         AMEMPTY_D <= '0';
	        else
	         AMEMPTY_D <= '1'; 	
	        end if; 
              else 
	         AMEMPTY_D <= '1'; 	
              end if;    
            elsif (W_POINTER > R_POINTER) then
	      if (v_RP_Check_AMET_TMP1 < R_POINTER) then
	         AMEMPTY_D <= '0';
	      elsif (v_RP_Check_AMET_TMP >= W_POINTER) then
	         AMEMPTY_D <= '0';
	      else 
	         AMEMPTY_D <= '1'; 	
	      end if; 
            elsif (W_POINTER = R_POINTER) then
              AMEMPTY_D <= '0';
            end if;    
       end if;
end process EMPTY_AMEMPTY;

end LATTICE_BEHAV;

-- ####################################################################
-- ##  SC_FIFO_L 
-- ####################################################################

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;


 entity SC_FIFO_16K_L is 
  generic (

 	DEVICE_FAMILY  : string  := "LAVA1";
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0; 
        TERMINAL_COUNT : integer := 511; 
        MEM_INIT_FILE  : string  := "mem_init_file"


         );

  port (

	CLK    : in STD_LOGIC ;
 	WE      : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);

        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)

        ); 

end SC_FIFO_16K_L; 

-- ************************************************************************
-- ARCHITECTURE
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_16K_L is 
 
   constant ACTIVE_HIGH_EMPTY : boolean := true;

-- ************************************************************************
-- COMPONENT DECLARATIONS
-- ************************************************************************
component SC_BRAM_16K_L_SYNC 

  generic (
 	     
         DEVICE_FAMILY : string  := "LAVA1";
         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
         MEM_INIT_FLAG : integer := 0;  
         MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
	 WCLK : in  STD_LOGIC;
	 RCLK : in  STD_LOGIC
        ); 
 end component;

-- ************************************************************************
-- SIGNAL DECLARATIONS
-- ************************************************************************
signal we_ram : STD_LOGIC := '0';
signal re_ram : STD_LOGIC := '0';
signal full_bit, am_full_bit : STD_LOGIC := '0';
signal empty_bit, am_empty_bit : STD_LOGIC := '1';
signal wptr_wrap_bit : STD_LOGIC := '0';
signal rptr_wrap_bit : STD_LOGIC := '0';
signal wptr : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0) := (others => '0');
signal rptr : STD_LOGIC_VECTOR (RADDR_WIDTH - 1 downto 0) := (others => '0');
signal wptr_wrap_appended : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				:= (others => '0');
signal rptr_wrap_appended : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) 
				:= (others => '0');
signal next_wptr_wrap_appended : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				:= (others => '0');
signal next_rptr_wrap_appended : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) 
				:= (others => '0');

signal next_num_unread_loc : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0); 				
signal next_num_empty_loc : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) ;
				
signal next_wptr : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0) := (others => '0');
signal next_rptr : STD_LOGIC_VECTOR (RADDR_WIDTH - 1 downto 0) := (others => '0');
signal next_wptr_wrap_bit : STD_LOGIC := '0';
signal next_rptr_wrap_bit : STD_LOGIC := '0';

signal TERM_CNT_VEC : STD_LOGIC_VECTOR (WADDR_WIDTH  downto 0);
signal DEPTH : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0);   



 
-- ************************************************************************
-- FUNCTIONS
-- ************************************************************************
function next_ptr (
   ptr_wrap_bit :  STD_LOGIC;
   ptr :  STD_LOGIC_VECTOR;
   TERMINAL_COUNT :  integer; 
   add: STD_LOGIC)

  return STD_LOGIC_VECTOR is

  variable result_ptr : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0); 
  variable tmp_ptr : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0);
  
begin
   if (ptr = TERMINAL_COUNT) then
      tmp_ptr := (others => '1');
   else
      tmp_ptr :=  ptr;
   end if;
   result_ptr := (ptr_wrap_bit & tmp_ptr) + add;
  
   return result_ptr;

end next_ptr;

function INT_TO_VEC ( INPUT_INT : integer; INPUT_LENGTH: integer)
 return std_logic_vector is

   variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
   variable vTRANS: integer := 0;
   variable vQUOTIENT: integer := 0;
 
 begin 
    vQUOTIENT := INPUT_INT;

    for i in 0 to INPUT_LENGTH -1 loop
	vTRANS := 0;
	while vQUOTIENT >1 loop
	    vQUOTIENT := vQUOTIENT - 2;
            vTRANS := vTRANS + 1;
	end loop;
        case vQUOTIENT is
              when 1 =>
                 vDATA_STD_VEC(i) := '1';
              when 0 =>
                 vDATA_STD_VEC(i) := '0';
              when others =>
                 null;
        end case;
        vQUOTIENT := vTRANS; 
    end loop;
  return vDATA_STD_VEC; 	  
 end INT_TO_VEC; 

-- ************************************************************************
-- BODY
-- ************************************************************************

begin 

-- ************************************************************************
-- INSTANTIATIONS
-- ************************************************************************

FIFO_BRAM_INST: SC_BRAM_16K_L_SYNC

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => WADDR_WIDTH, 
         RADDR_WIDTH_A  => RADDR_WIDTH, 
         WADDR_WIDTH_B  => WADDR_WIDTH, 
         RADDR_WIDTH_B  => RADDR_WIDTH, 
         WDATA_WIDTH_A  => WDATA_WIDTH, 
         RDATA_WIDTH_A  => RDATA_WIDTH, 
         WDATA_WIDTH_B  => WDATA_WIDTH, 
         RDATA_WIDTH_B  => RDATA_WIDTH, 
         --ct092805 ARRAY_SIZE     => open,
         ARRAY_SIZE     => (2**WADDR_WIDTH) * WDATA_WIDTH,
    	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
         WADA => wptr,
         WEA  => we_ram,
         WDA  => DI, 
         RADA => rptr,
         REA  => re_ram,
         RDA  => DO, 
         
         WADB => wptr, 
         WEB  => '0', 
         WDB  => DI, 
         RADB => rptr, 
         REB  => '0', 
         RDB  => open,
	 WCLK => CLK,
	 RCLK => CLK
      );


-- ************************************************************************
-- CONCURRENT ASSIGNMENTS
-- ************************************************************************
TERM_CNT_VEC (WADDR_WIDTH downto 0) <= INT_TO_VEC(TERMINAL_COUNT, WADDR_WIDTH + 1);

DEPTH (WADDR_WIDTH downto 0)  <= TERM_CNT_VEC  + 1;


we_ram  <= WE and not(full_bit);
re_ram <= RE and not(empty_bit);

wptr <= wptr_wrap_appended(WADDR_WIDTH - 1 downto 0);
rptr <= rptr_wrap_appended(RADDR_WIDTH - 1 downto 0);

wptr_wrap_bit <= wptr_wrap_appended(WADDR_WIDTH);
rptr_wrap_bit <= rptr_wrap_appended(RADDR_WIDTH);

next_wptr_wrap_appended <= next_ptr(wptr_wrap_bit, wptr, TERMINAL_COUNT, we_ram);
next_rptr_wrap_appended <= next_ptr(rptr_wrap_bit, rptr, TERMINAL_COUNT, re_ram);
next_wptr <= next_wptr_wrap_appended(WADDR_WIDTH - 1 downto 0);
next_rptr <= next_rptr_wrap_appended(RADDR_WIDTH - 1 downto 0);
next_wptr_wrap_bit <= next_wptr_wrap_appended(WADDR_WIDTH);
next_rptr_wrap_bit <= next_rptr_wrap_appended(RADDR_WIDTH);
-- ************************************************************************
-- FLAG LOGIC
-- ************************************************************************
next_num_empty_loc <= -- used for full, 
   ( DEPTH + next_rptr) - next_wptr when (next_rptr_wrap_bit = next_wptr_wrap_bit)
else
   "0" & (next_rptr -  next_wptr);

next_num_unread_loc <= --used for empty, 
   ( DEPTH + next_wptr) - next_rptr when (next_wptr_wrap_bit /= next_rptr_wrap_bit)
else
   "0" & (next_wptr -  next_rptr);

--------------------------------------------------------------------------
process (RST, CLK)
begin
   if (RST = '1')  then
      full_bit <= '0';
   elsif ( CLK'event and CLK = '1') then
      if (next_num_empty_loc = 0) then 
         full_bit <= '1' after 1 ns;
      else
         full_bit <= '0' after 1 ns;
      end if;
   end if ;   
end process;

process (RST, CLK)
begin
   if (RST = '1')  then
      am_full_bit <= '0';
   elsif ( CLK'event and CLK = '1') then
      if (next_num_empty_loc <= ALMOST_FULL_X) then 
         am_full_bit <= '1' after 1 ns;
      else
         am_full_bit <= '0' after 1 ns;
      end if;
   end if ;   
end process; 

process (RST, CLK)
begin
   if (RST = '1')  then
      empty_bit <= '1'; 
   elsif ( CLK'event and CLK = '1') then
      if (next_num_unread_loc = 0) then  
         empty_bit <= '1' after 1 ns;    
      else 
         empty_bit <= '0' after 1 ns;
      end if;
   end if ;   
end process;


process (RST, CLK)
begin
   if (RST = '1')  then
      am_empty_bit <= '1'; 
   elsif ( CLK'event and CLK = '1') then
      if (next_num_unread_loc <= ALMOST_EMPTY_Y) then  
         am_empty_bit <= '1' after 1 ns;    
      else 
         am_empty_bit <= '0' after 1 ns;
      end if;
   end if ;   
end process;

FULL <= full_bit;
AMFULL <= am_full_bit;
EMPTY <= empty_bit when ACTIVE_HIGH_EMPTY else not(empty_bit);
AMEMPTY <= am_empty_bit when ACTIVE_HIGH_EMPTY else not(am_empty_bit);


-- ************************************************************************
-- WRITE READ POINTERS
-- ************************************************************************

process (RST, CLK)
begin

   if (RST = '1')  then
      rptr_wrap_appended <= (others => '0') ;
   elsif ( CLK'event and CLK = '1') then
      if ( (RE and not(empty_bit)) = '1') then
         rptr_wrap_appended <= next_rptr_wrap_appended after 1 ns;
      end if;
   end if ;   
end process;

process (RST, CLK)
begin

   if (RST = '1')  then
      wptr_wrap_appended <= (others => '0');
   elsif ( CLK'event and CLK = '1') then
      if (WE = '1' and full_bit = '0') then
         wptr_wrap_appended <= next_wptr_wrap_appended after 1 ns;
      end if;
   end if;
end process;


-- ************************************************************************
-- END ARCHITECTURE: SC_FIFO_16K_L
-- ************************************************************************
end LATTICE_BEHAV; 


-- ####################################################################
-- ##  SC_FIFO_DC_L 
-- ####################################################################
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;


 entity SC_FIFO_DC_16K_L is 
  generic (
	
	DEVICE_FAMILY  : string  := "LAVA1";
  	TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
	WADDR_WIDTH    : integer :=   9;
        WDATA_WIDTH    : integer :=  32;
        RADDR_WIDTH    : integer :=   9;
        RDATA_WIDTH    : integer :=  32;
        ALMOST_FULL_X  : integer :=   1;
        ALMOST_EMPTY_Y : integer :=   1;
        MEM_INIT_FLAG  : integer :=   0;  
        MEM_INIT_FILE  : string  := "mem_init_file"


         );

  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);

        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)

        ); 

end SC_FIFO_DC_16K_L; 

-- ************************************************************************
-- ARCHITECTURE
-- ************************************************************************
architecture LATTICE_BEHAV of SC_FIFO_DC_16K_L is 
 
   constant NUM_SYNC_STAGES : integer :=2;
   constant ACTIVE_HIGH_EMPTY : boolean := true;

-- ************************************************************************
-- COMPONENT DECLARATIONS
-- ************************************************************************
component SC_BRAM_16K_L_SYNC 

  generic (
 	     
         DEVICE_FAMILY : string  := "LAVA1";
         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
         MEM_INIT_FLAG : integer := 0;  
         MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
	 WCLK : in  STD_LOGIC;
	 RCLK : in  STD_LOGIC
        ); 
 end component;

-- ************************************************************************
-- SIGNAL DECLARATIONS
-- ************************************************************************
signal we_ram : STD_LOGIC := '0';
signal re_ram : STD_LOGIC := '0';
signal full_bit, am_full_bit : STD_LOGIC := '0';
signal empty_bit, am_empty_bit : STD_LOGIC := '1';
signal wptr_wrap_bit : STD_LOGIC := '0';
signal rptr_wrap_bit : STD_LOGIC := '0';
signal wptr : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0) := (others => '0');
signal rptr : STD_LOGIC_VECTOR (RADDR_WIDTH - 1 downto 0) := (others => '0');
signal wptr_wrap_appended : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				:= (others => '0');
signal rptr_wrap_appended : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) 
				:= (others => '0');
signal next_wptr_wrap_appended : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				:= (others => '0');
signal next_rptr_wrap_appended : STD_LOGIC_VECTOR (RADDR_WIDTH downto 0) 
				:= (others => '0');

signal next_num_unread_loc : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0); 				
signal next_num_empty_loc : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) ;
				
signal next_wptr : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0) := (others => '0');
signal next_rptr : STD_LOGIC_VECTOR (RADDR_WIDTH - 1 downto 0) := (others => '0');
signal next_wptr_wrap_bit : STD_LOGIC := '0';
signal next_rptr_wrap_bit : STD_LOGIC := '0';

signal TERM_CNT_VEC : STD_LOGIC_VECTOR (WADDR_WIDTH  downto 0);
signal DEPTH : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0);   

signal wptr_rdomain : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0) := (others => '0');
signal rptr_wdomain : STD_LOGIC_VECTOR (RADDR_WIDTH - 1 downto 0) := (others => '0');

signal wptr_wrap_bit_rdomain : STD_LOGIC := '0';
signal rptr_wrap_bit_wdomain : STD_LOGIC := '0';

signal wptr_wrap_appended_rdomain : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				  := (others => '0');
signal rptr_wrap_appended_wdomain : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) 
				  := (others => '0');
signal wptr_rsync1 : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) := (others => '0');
signal rptr_wsync1 : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0) := (others => '0');


 
-- ************************************************************************
-- FUNCTIONS
-- ************************************************************************
function next_ptr (
   ptr_wrap_bit :  STD_LOGIC;
   ptr :  STD_LOGIC_VECTOR;
   TERMINAL_COUNT :  integer; 
   add: STD_LOGIC)

  return STD_LOGIC_VECTOR is

  variable result_ptr : STD_LOGIC_VECTOR (WADDR_WIDTH downto 0); 
  variable tmp_ptr : STD_LOGIC_VECTOR (WADDR_WIDTH - 1 downto 0);
  
begin
   if (ptr = TERMINAL_COUNT) then
      tmp_ptr := (others => '1');
   else
      tmp_ptr :=  ptr;
   end if;
   result_ptr := (ptr_wrap_bit & tmp_ptr) + add;
  
   return result_ptr;

end next_ptr;

function INT_TO_VEC ( INPUT_INT : integer; INPUT_LENGTH: integer)
 return std_logic_vector is

   variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
   variable vTRANS: integer := 0;
   variable vQUOTIENT: integer := 0;
 
 begin 
    vQUOTIENT := INPUT_INT;

    for i in 0 to INPUT_LENGTH -1 loop
	vTRANS := 0;
	while vQUOTIENT >1 loop
	    vQUOTIENT := vQUOTIENT - 2;
            vTRANS := vTRANS + 1;
	end loop;
        case vQUOTIENT is
              when 1 =>
                 vDATA_STD_VEC(i) := '1';
              when 0 =>
                 vDATA_STD_VEC(i) := '0';
              when others =>
                 null;
        end case;
        vQUOTIENT := vTRANS; 
    end loop;
  return vDATA_STD_VEC; 	  
 end INT_TO_VEC; 

-- ************************************************************************
-- BODY
-- ************************************************************************

begin 

-- ************************************************************************
-- INSTANTIATIONS
-- ************************************************************************

FIFO_BRAM_INST: SC_BRAM_16K_L_SYNC

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => WADDR_WIDTH, 
         RADDR_WIDTH_A  => RADDR_WIDTH, 
         WADDR_WIDTH_B  => WADDR_WIDTH, 
         RADDR_WIDTH_B  => RADDR_WIDTH, 
         WDATA_WIDTH_A  => WDATA_WIDTH, 
         RDATA_WIDTH_A  => RDATA_WIDTH, 
         WDATA_WIDTH_B  => WDATA_WIDTH, 
         RDATA_WIDTH_B  => RDATA_WIDTH, 
         --ct092805 ARRAY_SIZE     => open,
         ARRAY_SIZE     => (2**WADDR_WIDTH) * WDATA_WIDTH,
    	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
         WADA => wptr,
         WEA  => we_ram,
         WDA  => DI, 
         RADA => rptr,
         REA  => re_ram,
         RDA  => DO, 
         
         WADB => wptr, 
         WEB  => '0', 
         WDB  => DI, 
         RADB => rptr, 
         REB  => '0', 
         RDB  => open,
	 WCLK => WCLK,
	 RCLK => RCLK
      );


-- ************************************************************************
-- CONCURRENT ASSIGNMENTS
-- ************************************************************************
TERM_CNT_VEC (WADDR_WIDTH downto 0) <= INT_TO_VEC(TERMINAL_COUNT, WADDR_WIDTH + 1);

DEPTH (WADDR_WIDTH downto 0)  <= TERM_CNT_VEC  + 1;


we_ram  <= WE and not(full_bit);
re_ram <= RE and not(empty_bit);

wptr <= wptr_wrap_appended(WADDR_WIDTH - 1 downto 0);
rptr <= rptr_wrap_appended(RADDR_WIDTH - 1 downto 0);
wptr_rdomain <= wptr_wrap_appended_rdomain(WADDR_WIDTH - 1 downto 0);
rptr_wdomain <= rptr_wrap_appended_wdomain(RADDR_WIDTH - 1 downto 0);

wptr_wrap_bit <= wptr_wrap_appended(WADDR_WIDTH);
rptr_wrap_bit <= rptr_wrap_appended(RADDR_WIDTH);
wptr_wrap_bit_rdomain  <= wptr_wrap_appended_rdomain (WADDR_WIDTH);
rptr_wrap_bit_wdomain  <= rptr_wrap_appended_wdomain (RADDR_WIDTH);

next_wptr_wrap_appended <= next_ptr(wptr_wrap_bit, wptr, TERMINAL_COUNT, we_ram);
next_rptr_wrap_appended <= next_ptr(rptr_wrap_bit, rptr, TERMINAL_COUNT, re_ram);
next_wptr <= next_wptr_wrap_appended(WADDR_WIDTH - 1 downto 0);
next_rptr <= next_rptr_wrap_appended(RADDR_WIDTH - 1 downto 0);
next_wptr_wrap_bit <= next_wptr_wrap_appended(WADDR_WIDTH);
next_rptr_wrap_bit <= next_rptr_wrap_appended(RADDR_WIDTH);
-- ************************************************************************
-- FLAG LOGIC
-- ************************************************************************
next_num_empty_loc <= -- used for full, computed in wdomain
   ( DEPTH + rptr_wdomain) - next_wptr when (rptr_wrap_bit_wdomain = next_wptr_wrap_bit)
else
   "0" & (rptr_wdomain -  next_wptr);

next_num_unread_loc <= --used for empty, computed in rdomain
   ( DEPTH + wptr_rdomain) - next_rptr when (wptr_wrap_bit_rdomain /= next_rptr_wrap_bit)
else
   "0" & (wptr_rdomain -  next_rptr);

--------------------------------------------------------------------------
process (RST, WCLK)
begin
   if (RST = '1')  then
      full_bit <= '0';
   elsif ( WCLK'event and WCLK = '1') then
      if (next_num_empty_loc = 0) then 
         full_bit <= '1' after 1 ns;
      else
         full_bit <= '0' after 1 ns;
      end if;
   end if ;   
end process;

process (RST, WCLK)
begin
   if (RST = '1')  then
      am_full_bit <= '0';
   elsif ( WCLK'event and WCLK = '1') then
      if (next_num_empty_loc <= ALMOST_FULL_X) then 
         am_full_bit <= '1' after 1 ns;
      else
         am_full_bit <= '0' after 1 ns;
      end if;
   end if ;   
end process; 

process (RST, RCLK)
begin
   if (RST = '1')  then
      empty_bit <= '1'; 
   elsif ( RCLK'event and RCLK = '1') then
      if (next_num_unread_loc = 0) then  
         empty_bit <= '1' after 1 ns;    
      else 
         empty_bit <= '0' after 1 ns;
      end if;
   end if ;   
end process;


process (RST, RCLK)
begin
   if (RST = '1')  then
      am_empty_bit <= '1'; 
   elsif ( RCLK'event and RCLK = '1') then
      if (next_num_unread_loc <= ALMOST_EMPTY_Y) then  
         am_empty_bit <= '1' after 1 ns;    
      else 
         am_empty_bit <= '0' after 1 ns;
      end if;
   end if ;   
end process;

FULL <= full_bit;
AMFULL <= am_full_bit;
EMPTY <= empty_bit;-- when ACTIVE_HIGH_EMPTY else not(empty_bit);
AMEMPTY <= am_empty_bit;-- when ACTIVE_HIGH_EMPTY else not(am_empty_bit);


-- ************************************************************************
-- WRITE READ POINTERS
-- ************************************************************************

process (RST, RCLK)
begin

   if (RST = '1')  then
      rptr_wrap_appended <= (others => '0') ;
   elsif ( RCLK'event and RCLK = '1') then
      if ( (RE and not(empty_bit)) = '1') then
         rptr_wrap_appended <= next_rptr_wrap_appended after 1 ns;
      end if;
   end if ;   
end process;

process (RST, WCLK)
begin

   if (RST = '1')  then
      wptr_wrap_appended <= (others => '0');
   elsif ( WCLK'event and WCLK = '1') then
      if (WE = '1' and full_bit = '0') then
         wptr_wrap_appended <= next_wptr_wrap_appended after 1 ns;
      end if;
   end if;
end process;

-- ************************************************************************
-- POINTER SYNCHRONIZATIONS (SIMPLY DONE TO MATCH THE GATE-LEVEL MODEL)
-- ************************************************************************

process (RST, WCLK)
begin
   if (RST = '1')  then
      rptr_wrap_appended_wdomain <= (others => '0');
      rptr_wsync1 <= (others => '0');
   elsif ( WCLK'event and WCLK = '1') then
      rptr_wsync1 <= rptr_wrap_appended;
      if (NUM_SYNC_STAGES = 1) then
         rptr_wrap_appended_wdomain <=  rptr_wrap_appended  after 1 ns;
      else 
         rptr_wrap_appended_wdomain <= rptr_wsync1 after 1 ns;
      end if;
   end if;
end process;

process (RST, RCLK)
begin
   if (RST = '1')  then
      wptr_wrap_appended_rdomain <= (others => '0');
      wptr_rsync1 <= (others => '0');
   elsif ( RCLK'event and RCLK = '1') then
      wptr_rsync1 <= wptr_wrap_appended;
      if (NUM_SYNC_STAGES = 1) then
          wptr_wrap_appended_rdomain <= wptr_wrap_appended  after 1 ns;
      else 
         wptr_wrap_appended_rdomain <= wptr_rsync1 after 1 ns;  
      end if;                            
   end if;
end process;

-- ************************************************************************
-- END ARCHITECTURE: SC_FIFO_DC_16K_L
-- ************************************************************************
end LATTICE_BEHAV; 

-- ************************************************************************
--
--  FIFO V2: Behavioral Model
--  VHDL
-- ************************************************************************
--
--  Filename:  SC_FIFO_V2.vhd
--  Description: FIFO behavioral model. 
--     
-- ************************************************************************

-- ************************************************************************
-- History: 
-- 1. Reset EMPTY & AMEMPTY to '0', '0' means 'Ture';   
-- 2. May. 30, 2002 Read memory initialization file feature
-- 3. Add control signal RE WE to BlockRAM 
-- 4. Add programable TERMINAL_COUNT
-- 5. Fix the Write 1-5, Read 2-6 issue
-- 6. Data bus width conversion
--  
-- ************************************************************************

-- ************************************************************************
-- FIFO COMPONENTS READ_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity READ_POINTER_CTRL_V2 is
	generic (
              RPOINTER_WIDTH : integer := 9
		);
	port (
                TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
		GLOBAL_RST   : in STD_LOGIC ;
                RESET_RP     : in STD_LOGIC ;
                READ_EN      : in STD_LOGIC ;
                READ_CLK     : in STD_LOGIC ;
	        EMPTY_FLAG   : in STD_LOGIC ;
		READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
	     );
end READ_POINTER_CTRL_V2;

architecture LATTICE_BEHAV of READ_POINTER_CTRL_V2 is

  signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');

begin

  READ_POINTER <= s_READ_POINTER; 

process  (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)

	variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');

begin

	if GLOBAL_RST = '1'  or RESET_RP = '1' then 

        s_READ_POINTER <= TERMINAL_COUNT; 

	elsif (READ_CLK'EVENT and READ_CLK = '1') then
		if (READ_EN = '1' and EMPTY_FLAG = '1') then
                  v_READ_POINTER := s_READ_POINTER + '1';
		  
                else  
                  v_READ_POINTER := s_READ_POINTER;
		end if;

		if (v_READ_POINTER = TERMINAL_COUNT + 1) then
		   s_READ_POINTER <= (others => '0');
		else
		   s_READ_POINTER <= v_READ_POINTER;
		end if;
	end if;

end process;
end LATTICE_BEHAV;

-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity WRITE_POINTER_CTRL_V2 is
        generic (
                WPOINTER_WIDTH : integer := 9;
                WDATA_WIDTH : integer := 32
		);
        port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
		GLOBAL_RST    : in STD_LOGIC ;
                WRITE_EN      : in STD_LOGIC ;
                WRITE_CLK     : in STD_LOGIC ;
                FULL_FLAG     : in STD_LOGIC ;
                WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
            
	     );
end WRITE_POINTER_CTRL_V2;

architecture LATTICE_BEHAV of WRITE_POINTER_CTRL_V2 is

 signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');

begin 

  WRITE_POINTER <= s_WRITE_POINTER;

  process  (GLOBAL_RST, WRITE_EN, WRITE_CLK)

    variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');

begin
	if GLOBAL_RST = '1'  then 
		s_WRITE_POINTER <= TERMINAL_COUNT ; 

	elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
		if (WRITE_EN = '1' and FULL_FLAG /= '1') then
		   v_WRITE_POINTER := s_WRITE_POINTER + '1';
                else
		   v_WRITE_POINTER := s_WRITE_POINTER ;
                end if; 

		if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
		   s_WRITE_POINTER <= (others => '0');
		else
		   s_WRITE_POINTER <= v_WRITE_POINTER ;
		end if;
	end if;
end process;
end LATTICE_BEHAV;

-- ************************************************************************
-- FIFO V2 COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;

entity FLAG_LOGIC_V2 is
 	generic (
                WDATA_WIDTH    : integer := 32; 
                RDATA_WIDTH    : integer := 32; 
                AMFULL_X      : integer := 1;
                AMEMPTY_Y     : integer := 1
		);
	port (
                GLOBAL_RST : in STD_LOGIC ;
		FIFO_CAP   : in integer ; 	
                FIFO_PTR   : in integer ;
                FULL_D     : out STD_LOGIC ;
                EMPTY_D    : out STD_LOGIC ;
                AMFULL_D   : out STD_LOGIC ;
                AMEMPTY_D  : out STD_LOGIC 
	);
end FLAG_LOGIC_V2;

architecture LATTICE_BEHAV of FLAG_LOGIC_V2 is

begin 
--------------------------------------------------------------------------
-- Function: Main Process 
-- Description: 
--------------------------------------------------------------------------
FULL_AMFULL_EMPTY_AMEMPTY: process  (GLOBAL_RST, FIFO_CAP, FIFO_PTR)

begin

	if GLOBAL_RST = '1'  then 
	    FULL_D    <= '0';
	    AMFULL_D  <= '0';
	    EMPTY_D   <= '0';
            AMEMPTY_D <= '0';
	else
		if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH) then
		     FULL_D <= '1';
		else
		     FULL_D <= '0';	
	        end if;

		if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH + AMFULL_X * WDATA_WIDTH) then
		     AMFULL_D <= '1';
		else
		     AMFULL_D <= '0';	
	        end if;

		if (FIFO_PTR < RDATA_WIDTH) then
		     EMPTY_D <= '0';
	        else
		     EMPTY_D <= '1';	
	        end if;

		if (FIFO_PTR < RDATA_WIDTH + AMEMPTY_Y * RDATA_WIDTH) then
		     AMEMPTY_D <= '0';
	        else
		     AMEMPTY_D <= '1';	
		end if;
	end if;

end process FULL_AMFULL_EMPTY_AMEMPTY;

end LATTICE_BEHAV;


-- ************************************************************************
-- FIFO V2 Main Body 
-- READ_POINTER_CTRL_V2
-- WRITE_POINTER_CTRL_V2
-- FLAG_LOGIC_V2 
-- SC_BRAM_16K
-- ************************************************************************
-- ************************************************************************
-- Top Design Entity definition  
-- ************************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity SC_FIFO_V2_16K is

  generic (

        DEVICE_FAMILY  : string  := "LAVA1";
  	TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
	WADDR_WIDTH    : integer :=   9;
        WDATA_WIDTH    : integer :=  32;
        RADDR_WIDTH    : integer :=   8;
        RDATA_WIDTH    : integer :=  64;
        ALMOST_FULL_X  : integer :=   2;
        ALMOST_EMPTY_Y : integer :=   2;
        MEM_INIT_FLAG  : integer :=   0;  
        MEM_INIT_FILE  : string  := "mem_init_file"

         );

  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);

        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)

        ); 

end SC_FIFO_V2_16K ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_FIFO_V2_16K is

---------------------------------------------------------
-- Function: TO_STD_VECTOR
---------------------------------------------------------
 function TO_STD_VECTOR ( INPUT_STRING : string; INPUT_LENGTH: integer)
 return std_logic_vector is

   variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
   variable vTRANS: string(INPUT_LENGTH downto 1) := (others => '0');
 
 begin 
    vTRANS := INPUT_STRING;

    for i in INPUT_LENGTH downto 1 loop
      if (vTRANS(i) = '1') then
        vDATA_STD_VEC(i-1) := '1';
      elsif ( vTRANS(i) ='0') then
        vDATA_STD_VEC(i-1) := '0';
      end if;  
    end loop;
  return vDATA_STD_VEC; 	  
 end TO_STD_VECTOR; 

---------------------------------------------------------
-- Components Definition
---------------------------------------------------------

component SC_BRAM_16K_L

  generic (
 	     
         DEVICE_FAMILY : string  := "LAVA1";
         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
         MEM_INIT_FLAG : integer := 0;  
         MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 component READ_POINTER_CTRL_V2

 	generic (
                RPOINTER_WIDTH : integer := 9
		);
	port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);
                GLOBAL_RST     : in STD_LOGIC ;
                RESET_RP       : in STD_LOGIC ;
                READ_EN        : in STD_LOGIC ;
                READ_CLK       : in STD_LOGIC ;
                EMPTY_FLAG     : in STD_LOGIC ;
                READ_POINTER   : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
             );
 end component;

 component WRITE_POINTER_CTRL_V2
 	generic (
		WPOINTER_WIDTH : integer := 9;
		WDATA_WIDTH    : integer := 32
		);
	port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);
                GLOBAL_RST     : in STD_LOGIC ;
                WRITE_EN       : in STD_LOGIC ;
                WRITE_CLK      : in STD_LOGIC ;
                FULL_FLAG      : in STD_LOGIC ;
                WRITE_POINTER  : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
		);
 end component;
		
 component FLAG_LOGIC_V2
 	generic (
                WDATA_WIDTH    : integer := 32; 
                RDATA_WIDTH    : integer := 32; 
                AMFULL_X       : integer := 1;
                AMEMPTY_Y      : integer := 1
		);
	port (
                GLOBAL_RST : in STD_LOGIC ;
		FIFO_CAP   : in integer ; 	
                FIFO_PTR   : in integer ;
                FULL_D     : out STD_LOGIC ;
                EMPTY_D    : out STD_LOGIC ;
                AMFULL_D   : out STD_LOGIC ;
                AMEMPTY_D  : out STD_LOGIC 
	);
 end component;
 -- Signal Declaration
 
 signal WE_node      :  STD_LOGIC := 'X';
 signal WCLK_node    :  STD_LOGIC := 'X';
 signal RST_node     :  STD_LOGIC := 'X';
 signal RPRST_node   :  STD_LOGIC := 'X';
 signal RE_node      :  STD_LOGIC := 'X';
 signal RCLK_node    :  STD_LOGIC := 'X';
 signal FULLIN_node  :  STD_LOGIC := 'X';
 signal EMPTYIN_node :  STD_LOGIC := 'X';
 signal DI_node      :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');

 signal DI_reg       :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
 signal WE_reg       :  STD_LOGIC := 'X';  
 signal RE_reg       :  STD_LOGIC := 'X';  
 signal FULLIN_reg   :  STD_LOGIC := 'X';
 signal EMPTYIN_reg  :  STD_LOGIC := 'X';

 signal FULL_node    :  STD_LOGIC := 'X';
 signal EMPTY_node   :  STD_LOGIC := 'X';
 signal AMFULL_node  :  STD_LOGIC := 'X';
 signal AMEMPTY_node :  STD_LOGIC := 'X';
 signal DO_node      :  STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');

 signal TC_W_node      :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X'); 
 signal TC_R_node      :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X'); 

 signal FULL_reg     :  STD_LOGIC := 'X';
 signal EMPTY_reg    :  STD_LOGIC := 'X';
 signal AMFULL_reg   :  STD_LOGIC := 'X';
 signal AMEMPTY_reg  :  STD_LOGIC := 'X';

 signal RP_node      :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0)  := (others => 'X');
 signal WP_node      :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0)  := (others => 'X');
 signal GND_sig      :  STD_LOGIC := 'X';

--QQ FIFOV2
 signal FIFO_capacity : integer := 0; 	
 signal FIFO_pointer  : integer := 0;
-- architecture

 begin
  FIFO_capacity <= (TERMINAL_COUNT + 1) * WDATA_WIDTH; 	

  GND_sig      <= '0';
  WE_node      <= WE and not (FULL_node);
  WCLK_node    <= WCLK;
  RST_node     <= RST;
  RPRST_node   <= RPRST;
  RE_node      <= RE;
  RCLK_node    <= RCLK;
  FULLIN_node  <= FULLIN;
  EMPTYIN_node <= EMPTYIN;
  DI_node      <= DI;

  TC_W_node      <= CONV_STD_LOGIC_VECTOR(TERMINAL_COUNT,WADDR_WIDTH);
  TC_R_node      <= CONV_STD_LOGIC_VECTOR((TERMINAL_COUNT+1)*(WDATA_WIDTH/RDATA_WIDTH)-1,RADDR_WIDTH);


  FULL    <= FULL_node when (RE_node = '0') else FULL_reg;
  AMFULL  <= AMFULL_node when (RE_node = '0') else AMFULL_reg;
  EMPTY   <= not EMPTY_node;
  AMEMPTY <= not AMEMPTY_node;
  
  DO <= DO_node;    

-- Register Port DI inputs
  register_DI_inputs: process (RST_node, WCLK_node)
  begin
    if (RST_node = '1') then
      DI_reg <= (others =>'0');
    elsif (WCLK_node'event and WCLK_node = '1') then
      if (WE_node = '1') then
        DI_reg <= DI_node after 1 ps;
      end if;
    end if;
  end process register_DI_inputs;   

-- Register flag inputs
  register_flag_inputs: process (RST_node, WCLK_node, RCLK_node)
  begin
    if (RST_node = '1') then
      FULLIN_reg  <= '0';
      EMPTYIN_reg <= '0';
      WE_reg <= '0';  
      RE_reg <= '0';  
    else
    
      if (WCLK_node'event and WCLK_node = '1') then
          WE_reg <= WE_node and not FULL_reg;  --Fix DTS14659
          --WE_reg <= WE_node;  
        if (WE_node = '1') then
          FULLIN_reg <= FULLIN_node;
        end if;
      end if;

      if (RCLK_node'event and RCLK_node = '1') then
          RE_reg <= RE_node and EMPTY_reg;  
        if (RE_node = '1') then
          EMPTYIN_reg <= EMPTYIN_node;
        end if;
      end if;

    end if;
  end process register_flag_inputs; 
  
-- Register flag outputs
  register_flag_outputs: process (RST_node, WCLK_node, RCLK_node)
  begin
    if (RST_node = '1') then
      FULL_node    <= '0';
      AMFULL_node  <= '0';
      EMPTY_node   <= '0';
      AMEMPTY_node <= '0';
    else
      if (WCLK_node'event and WCLK_node = '1') then
        FULL_node <= FULL_reg;
        AMFULL_node <= AMFULL_reg;
      end if;
      if (RCLK_node'event and RCLK_node = '1') then
        EMPTY_node <= EMPTY_reg;
        AMEMPTY_node <= AMEMPTY_reg;
      end if; 
    end if;
  end process register_flag_outputs; 

-- Set FIFO_pointer 
  FIFO_CAP_POINTER: process ( RP_node, WP_node, RST_node, RPRST_node)
  begin
  --WP ++, FIFO_CAP --
    if (WP_node'event and RP_node'event) then
        FIFO_pointer <= FIFO_pointer + WDATA_WIDTH - RDATA_WIDTH;
    elsif(WP_node'event) then
        FIFO_pointer <= FIFO_pointer + WDATA_WIDTH; 
    end if; 
  --RPRST Active, FIFO_CAP --
  --RP ++, FIFO_CAP ++
    if (RST_node = '1') then
	FIFO_pointer <= 0;
    elsif (RPRST_node = '1') then	
	FIFO_pointer <= (CONV_INTEGER(WP_node)+1) * WDATA_WIDTH;
    elsif (RP_node'event and not(WP_node'event)) then
        FIFO_pointer <= FIFO_pointer - RDATA_WIDTH;
    end if; 
  end process FIFO_CAP_POINTER; 


-- READ_POINTER_CTRL_V2 instance for FIFO
  FIFO_RPC_INST: READ_POINTER_CTRL_V2
        generic map (
		RPOINTER_WIDTH => RADDR_WIDTH
		)
        port map (
		TERMINAL_COUNT => TC_R_node,
		GLOBAL_RST   => RST_node,
                RESET_RP     => RPRST_node,
                READ_EN      => RE_node,
                READ_CLK     => RCLK_node,
                EMPTY_FLAG   => EMPTY_reg,
                READ_POINTER => RP_node
	     );
 
-- WRITE_POINTER_CTRL_V2 instance for FIFO
  FIFO_WPC_INST: WRITE_POINTER_CTRL_V2
        generic map (
                WPOINTER_WIDTH => WADDR_WIDTH, 
                WDATA_WIDTH    => WDATA_WIDTH
		)
        port map (
		TERMINAL_COUNT => TC_W_node,
		GLOBAL_RST     => RST_node,
                WRITE_EN       => WE_node,
                WRITE_CLK      => WCLK_node,
                FULL_FLAG      => FULL_reg,
                WRITE_POINTER  => WP_node
		);
 
-- FLAG_LOGIC_V2 instance for FIFO
  FIFO_FL_INST: FLAG_LOGIC_V2
           generic map (
                WDATA_WIDTH    => WDATA_WIDTH, 
                RDATA_WIDTH    => RDATA_WIDTH, 
                AMFULL_X       => ALMOST_FULL_X, 
                AMEMPTY_Y      => ALMOST_EMPTY_Y
		)
           port map(
                GLOBAL_RST    => RST_node, 
		FIFO_CAP      => FIFO_capacity, 	
                FIFO_PTR      => FIFO_pointer,
		FULL_D        => FULL_reg, 
                EMPTY_D       => EMPTY_reg, 
                AMFULL_D      => AMFULL_reg, 
                AMEMPTY_D     => AMEMPTY_reg 
	);

-- BRAM instance for FIFO 
  FIFO_BRAM_INST: SC_BRAM_16K_L

    generic map(
         DEVICE_FAMILY  => open ,
         WADDR_WIDTH_A  => WADDR_WIDTH, 
         RADDR_WIDTH_A  => RADDR_WIDTH, 
         WADDR_WIDTH_B  => WADDR_WIDTH, 
         RADDR_WIDTH_B  => RADDR_WIDTH, 
         WDATA_WIDTH_A  => WDATA_WIDTH, 
         RDATA_WIDTH_A  => RDATA_WIDTH, 
         WDATA_WIDTH_B  => WDATA_WIDTH, 
         RDATA_WIDTH_B  => RDATA_WIDTH, 
         --ct092805 ARRAY_SIZE     => open,
         ARRAY_SIZE     => (2**WADDR_WIDTH) * WDATA_WIDTH,

    	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
         WADA => WP_node, 
         WEA  => WE_reg, 
         WDA  => DI_reg, 
         RADA => RP_node, 
         REA  => RE_reg, 
         RDA  => DO_node, 
         
         WADB => WP_node, 
         WEB  => GND_sig, 
         WDB  => DI_reg, 
         RADB => RP_node, 
         REB  => GND_sig, 
         RDB  => open 
      );

end LATTICE_BEHAV;

-- ####################################################################
-- fifo 
-- ####################################################################
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

entity fifo is
  generic (
         lpm_type         : string  := "Lattice_MEM";
	 module_type      : string  := "FIFO";
	 module_width     : integer := 1;
	 module_widthu    : integer := 1;
	 module_numwords  : integer := 2;
         module_amfull_flag : integer := 1;
         module_amempty_flag : integer := 1;
	 module_hint      : string  := "UNUSED");

  port (
	 Data          :  in  std_logic_vector (module_width-1 downto 0);
	 Clock         :  in  std_logic;
	 WrEn          :  in  std_logic;
	 RdEn          :  in  std_logic;
	 Reset          :  in  std_logic;
	 RPReset       :  in  std_logic;
	 Q             :  out std_logic_vector (module_width-1 downto 0);
	 Full          :  out std_logic;
	 Empty         :  out std_logic;
	 AlmostFull    :  out std_logic;
	 AlmostEmpty   :  out std_logic);

end fifo;

architecture fun_simulation of fifo is

  component SC_FIFO_16K_L

    generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0; 
        TERMINAL_COUNT : integer := 511; 
        MEM_INIT_FILE  : string  := "mem_init_file"

         );

    port (
        CLK    : in STD_LOGIC ;  --072104
        WE      : in STD_LOGIC ;
        --072104 WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        --072104 RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);

        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)

        ); 

end component;

     signal Rst, FullIn, EmptyIn : std_logic;


  begin

      Rst     <= '1';
      FullIn  <= '0';
      EmptyIn <= '1';


  SC_FIFO_inst : SC_FIFO_16K_L

    generic map (

        DEVICE_FAMILY   =>  open,
        WADDR_WIDTH     =>  module_widthu,
        WDATA_WIDTH     =>  module_width,
        RADDR_WIDTH     =>  module_widthu,
        RDATA_WIDTH     =>  module_width,
        ALMOST_FULL_X   =>  module_amfull_flag,
        ALMOST_EMPTY_Y  =>  module_amempty_flag,
        MEM_INIT_FLAG   =>  0,
        TERMINAL_COUNT  =>  module_numwords - 1,
        MEM_INIT_FILE   => open )

    port map (
        CLK       => Clock, --072104
        WE         => WrEn, 
        --072104 WCLK       => Clock,
        RST        => Reset, 
        RPRST      => RPReset, 
        RE         => RdEn, 
        --072104 RCLK       => Clock, 
        FULLIN     => FullIn, 
        EMPTYIN    => EmptyIn, 
        DI         => Data, 

        FULL       => Full, 
        EMPTY      => Empty, 
        AMFULL     => AlmostFull, 
        AMEMPTY    => AlmostEmpty, 
        DO         => Q
        ); 

end;

-- ####################################################################
-- fifo_dc
-- ####################################################################

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

entity fifo_dc is
  generic (
         lpm_type         : string  := "Lattice_MEM";
	 module_type      : string  := "FIFO_DC";
	 module_width     : integer := 1;
	 module_widthu    : integer := 1;
	 module_numwords  : integer := 2;
         module_amfull_flag : integer := 1;
         module_amempty_flag : integer := 1;
	 module_hint      : string  := "UNUSED");

  port (
	 Data          :  in  std_logic_vector (module_width-1 downto 0);
	 WrClock       :  in  std_logic;
	 WrEn          :  in  std_logic;
	 RdClock       :  in  std_logic;
	 RdEn          :  in  std_logic;
	 Reset          :  in  std_logic;
	 RPReset       :  in  std_logic;
	 Q             :  out std_logic_vector (module_width-1 downto 0);
	 Full          :  out std_logic;
	 Empty         :  out std_logic;
	 AlmostFull    :  out std_logic;
	 AlmostEmpty   :  out std_logic);

end fifo_dc;

architecture fun_simulation of fifo_dc is

  component SC_FIFO_DC_16K_L --071604

    generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0; 
        TERMINAL_COUNT : integer := 511; 
        MEM_INIT_FILE  : string  := "mem_init_file"

         );

    port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);

        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)

        ); 

end component;

     signal Rst, FullIn, EmptyIn : std_logic;


  begin

      Rst     <= '1';
      FullIn  <= '0';
      EmptyIn <= '1';


  SC_FIFO_DC_inst : SC_FIFO_DC_16K_L --071604

    generic map (

        DEVICE_FAMILY   =>  open,
        WADDR_WIDTH     =>  module_widthu,
        WDATA_WIDTH     =>  module_width,
        RADDR_WIDTH     =>  module_widthu,
        RDATA_WIDTH     =>  module_width,
        ALMOST_FULL_X   =>  module_amfull_flag,
        ALMOST_EMPTY_Y  =>  module_amempty_flag,
        MEM_INIT_FLAG   =>  0,
        TERMINAL_COUNT  =>  module_numwords - 1,
        MEM_INIT_FILE   => open )

    port map (
        WE         => WrEn, 
        WCLK       => WrClock,
        RST        => Reset, 
        RPRST      => RPReset, 
        RE         => RdEn, 
        RCLK       => RdClock, 
        FULLIN     => FullIn, 
        EMPTYIN    => EmptyIn, 
        DI         => Data, 

        FULL       => Full, 
        EMPTY      => Empty, 
        AMFULL     => AlmostFull, 
        AMEMPTY    => AlmostEmpty, 
        DO         => Q
        ); 

end;


-- ####################################################################
-- fifo_dcx 
-- ####################################################################

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

entity fifo_dcx is
  generic (
         lpm_type          : string  := "Lattice_MEM";
	 module_type       : string  := "FIFO_DCX";
	 module_widthw     : integer := 1;
	 module_widthr     : integer := 1;
	 module_widthuw    : integer := 1;
	 module_widthur    : integer := 1;
	 module_numwordsw  : integer := 2;
	 module_numwordsr  : integer := 2;
         module_amfull_flag : integer := 1;
         module_amempty_flag : integer := 1;
	 module_hint      : string  := "UNUSED");

  port (
	 Data          :  in  std_logic_vector (module_widthw-1 downto 0);
	 WrClock       :  in  std_logic;
	 WrEn          :  in  std_logic;
	 RdClock       :  in  std_logic;
	 RdEn          :  in  std_logic;
	 Reset          :  in  std_logic;
	 RPReset       :  in  std_logic;
	 Q             :  out std_logic_vector (module_widthr-1 downto 0);
	 Full          :  out std_logic;
	 Empty         :  out std_logic;
	 AlmostFull    :  out std_logic;
	 AlmostEmpty   :  out std_logic);

end fifo_dcx;

architecture fun_simulation of fifo_dcx is

  component SC_FIFO_V2_16K

    generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        WADDR_WIDTH    : integer :=  9;
        WDATA_WIDTH    : integer := 32;
        RADDR_WIDTH    : integer :=  9;
        RDATA_WIDTH    : integer := 32;
        ALMOST_FULL_X  : integer :=  1;
        ALMOST_EMPTY_Y  : integer := 1;
        MEM_INIT_FLAG  : integer := 0; 
        TERMINAL_COUNT : integer := 511; 
        MEM_INIT_FILE  : string  := "mem_init_file"

         );

    port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);

        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)

        ); 

end component;

     signal FullIn, EmptyIn : std_logic;


  begin

      FullIn  <= '0';
      EmptyIn <= '1';


  SC_FIFO_inst : SC_FIFO_V2_16K

    generic map (

        DEVICE_FAMILY   =>  open,
        WADDR_WIDTH     =>  module_widthuw,
        WDATA_WIDTH     =>  module_widthw,
        RADDR_WIDTH     =>  module_widthur,
        RDATA_WIDTH     =>  module_widthr,
        ALMOST_FULL_X   =>  module_amfull_flag,
        ALMOST_EMPTY_Y  =>  module_amempty_flag,
        MEM_INIT_FLAG   =>  0,
        TERMINAL_COUNT  =>  module_numwordsw - 1,
        MEM_INIT_FILE   => open )

    port map (
        WE         => WrEn, 
        WCLK       => WrClock,
        RST        => Reset, 
        RPRST      => RPReset, 
        RE         => RdEn, 
        RCLK       => RdClock, 
        FULLIN     => FullIn, 
        EMPTYIN    => EmptyIn, 
        DI         => Data, 

        FULL       => Full, 
        EMPTY      => Empty, 
        AMFULL     => AlmostFull, 
        AMEMPTY    => AlmostEmpty, 
        DO         => Q
        ); 

end;


library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lava1;
use lava1.components.all;
    
entity ram_dp is
  generic( lpm_type                : string  := "Lattice_MEM";
	   module_type             : string  := "RAM_DP";
	   module_widthw           : integer := 1;
	   module_widthr           : integer := 1;
	   module_numwordsw        : integer := 1;
	   module_widthadw         : integer := 1;
	   module_widthadr         : integer := 1;
   	   module_numwordsr        : integer := 1;
  	   module_indata           : string := "REGISTERED";
	   module_outdata          : string := "REGISTERED";
    	   module_addressw_control : string := "UNREGISTERED";
	   module_addressr_control : string := "UNREGISTERED";
	   module_hint             : string := "UNUSED";
           module_init_file        : string := "");


  port(
           Data        : in  std_logic_vector (module_widthw-1 downto 0);
           WrAddress   : in  std_logic_vector (module_widthadw-1 downto 0);
           RdAddress   : in  std_logic_vector (module_widthadr-1 downto 0);
           WrClock     : in std_logic;
           WrClockEn   : in std_logic;
           RdClock     : in std_logic;
           RdClockEn   : in std_logic;
           WE          : in std_logic;
           Q           : out std_logic_vector (module_widthr-1 downto 0));

end ram_dp;

architecture fun_simulation of ram_dp is

component SC_PDPRAM_16K_L

  generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        WADDR_WIDTH    : integer := 13;
        WDATA_WIDTH    : integer := 2;
        RADDR_WIDTH    : integer := 13;
        RDATA_WIDTH    : integer := 2;
        ARRAY_SIZE     : integer := 511; 
        MEM_INIT_FLAG  : integer := 0;  
	MEM_INIT_FILE  : string  := "mem_init_file"

        );

  port (
        WCEN : in  STD_LOGIC ;
        WCLK : in  STD_LOGIC ;
        WE   : in  STD_LOGIC ;
        WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
        RCLK : in  STD_LOGIC;
        RCEN : in  STD_LOGIC;
        RST  : in  STD_LOGIC ;

        WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
        RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);  
        RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
       ); 

end component;

component SC_PDPRAMA_16K_L

  generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        WADDR_WIDTH    : integer := 13;
        WDATA_WIDTH    : integer := 2;
        RADDR_WIDTH    : integer := 13;
        RDATA_WIDTH    : integer := 2;
        ARRAY_SIZE     : integer := 16384;
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "mem_init_file"

        );

  port (
        WCEN : in  STD_LOGIC ;
        WCLK : in  STD_LOGIC ;
        WE   : in  STD_LOGIC ;
        WCS  : in  STD_LOGIC_VECTOR (1 downto 0);
        RST  : in  STD_LOGIC ;

        WD   : in  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);
        WAD  : in  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0);
        RAD  : in  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0);  
        RD   : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)
       ); 

end component ;


     signal cs        : std_logic_vector ( 1 downto 0);
     signal Q_K       : std_logic_vector (module_widthr-1 downto 0);
     signal Q_KA      : std_logic_vector (module_widthr-1 downto 0);
     CONSTANT  module_init_flag       :  integer := init_flag(module_init_file);
     signal GND_sig   : std_logic;

  begin

     GND_sig <= '0';
     cs <= "11";

      SelectOut  : process (Q_K , Q_KA)
        begin
              if(module_addressr_control = "UNREGISTERED" and module_outdata = "UNREGISTERED") then
                     Q <= Q_KA;
              elsif(module_addressr_control = "UNREGISTERED" and module_outdata = "REGISTERED") then 
                     Q <= Q_K;
              end if;
        end process;


   PDPRAM_inst : SC_PDPRAM_16K_L

  generic map(

        DEVICE_FAMILY  => open,
        WADDR_WIDTH    => module_widthadw,
        WDATA_WIDTH    => module_widthw,
        RADDR_WIDTH    => module_widthadr,
        RDATA_WIDTH    => module_widthr,
        MEM_INIT_FLAG  => module_init_flag,  
        ARRAY_SIZE     => module_numwordsw*module_widthw,
	MEM_INIT_FILE  => module_init_file)

  port map(
        WCEN =>  WrClockEn,
        WCLK =>  WrClock,
        WE   =>  WE,
        WCS  =>  cs,
        RCLK =>  RdClock,
        RCEN =>  RdClockEn,
        RST  =>  GND_sig,

        WD   =>  Data,
        WAD  =>  WrAddress,
        RAD  =>  RdAddress,
        RD   =>  Q_K 
       ); 

   PDPRAM_instA : SC_PDPRAMA_16K_L

  generic map(

        DEVICE_FAMILY  => open,
        WADDR_WIDTH    => module_widthadw,
        WDATA_WIDTH    => module_widthw,
        RADDR_WIDTH    => module_widthadr,
        RDATA_WIDTH    => module_widthr,
        MEM_INIT_FLAG  => module_init_flag,  
        ARRAY_SIZE     => module_numwordsw*module_widthw,
	MEM_INIT_FILE  => module_init_file)

  port map(
        WCEN =>  WrClockEn,
        WCLK =>  WrClock,
        WE   =>  WE,
        WCS  =>  cs,
        RST  =>  GND_sig,

        WD   =>  Data,
        WAD  =>  WrAddress,
        RAD  =>  RdAddress,
        RD   =>  Q_KA 
       ); 
end;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lava1;
use lava1.components.all;

entity ram_dp_true is 
generic (     lpm_type         : string := "Lattice_MEM";
              module_typE      : string := "RAM_DP_TRUE";
              module_widtha    : positive;
              module_widthada  : positive;
              module_numwordsa : positive;
              module_widthb    : positive;
              module_widthadb  : positive;
              module_numwordsb : positive;
              module_indata    : string :="REGISTERED";
              module_outdata   : string :="REGISTERED";
              module_addressa_control   : string :="UNREGISTERED";
              module_addressb_control   : string :="UNREGISTERED";
              module_init_file        : string := "";
              module_hint      : string :="UNUSED");
      port (  
              DataInA       : in std_logic_vector(module_widtha-1 downto 0);
              AddressA      : in std_logic_vector(module_widthada-1 downto 0);
              DataInB       : in std_logic_vector(module_widthb-1 downto 0);
              AddressB      : in std_logic_vector(module_widthadb-1 downto 0);
              ClockA        : in std_logic := '0';
              ClockEnA      : in std_logic := '0';
              ClockB        : in std_logic := '0';
              ClockEnB      : in std_logic := '0';
              WrA           : in std_logic;
              WrB           : in std_logic;
              ResetA        : in std_logic;
              ResetB        : in std_logic;
              QA            : out std_logic_vector(module_widtha-1 downto 0);
              QB            : out std_logic_vector(module_widthb-1 downto 0));
end ram_dp_true;

architecture fun_simulation of ram_dp_true is

component SC_DPRAM_16K_L
  generic (
        DEVICE_FAMILY  : string  := "LAVA1";
        ADDR_WIDTH_A     : integer := 13;
        DATA_WIDTH_A     : integer := 2;
        ADDR_WIDTH_B     : integer := 14;
        DATA_WIDTH_B     : integer := 1;
        MEM_INIT_FLAG  : integer := 0;  
        ARRAY_SIZE     : integer := 511; 
	MEM_INIT_FILE  : string  := "module_init_file"
        );
  port (
        CENA : in  STD_LOGIC ;
        CLKA : in  STD_LOGIC ;
        WRA  : in  STD_LOGIC ;
        CSA  : in  STD_LOGIC_VECTOR (1 downto 0);
        RSTA : in  STD_LOGIC ;
        DIA  : in  STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);
        ADA  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_A -1 downto 0);
        DOA  : out STD_LOGIC_VECTOR (DATA_WIDTH_A -1 downto 0);

        CENB : in  STD_LOGIC ;
        CLKB : in  STD_LOGIC ;
        WRB  : in  STD_LOGIC ;
        CSB  : in  STD_LOGIC_VECTOR (1 downto 0);
        RSTB : in  STD_LOGIC ;
        DIB  : in  STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0);
        ADB  : in  STD_LOGIC_VECTOR (ADDR_WIDTH_B -1 downto 0);
        DOB  : out STD_LOGIC_VECTOR (DATA_WIDTH_B -1 downto 0)
        ); 

end component;

      signal CS : std_logic_vector ( 1 downto 0);
      CONSTANT  module_init_flag       :  integer := init_flag(module_init_file);

begin

      CS <= "11";

RAM_DP_INST : SC_DPRAM_16K_L

    generic map(
         DEVICE_FAMILY  => open ,
         ADDR_WIDTH_A  => module_widthada,
         DATA_WIDTH_A  => module_widtha,
         ADDR_WIDTH_B  => module_widthadb,
         DATA_WIDTH_B  => module_widthb,
  	 MEM_INIT_FLAG => module_init_flag,  
         ARRAY_SIZE    => module_numwordsa*module_widtha,
	 MEM_INIT_FILE  => module_init_file
       )
    port map (
         CENA => ClockEnA,
         CLKA => ClockA,
         WRA  => WrA,
         CSA  => CS,
         RSTA => ResetA,
         DIA  => DataInA,
         ADA  => AddressA,
         DOA  => QA,

         CENB => ClockEnB,
         CLKB => ClockB,
         WRB  => WrB,
         CSB  => CS,
         RSTB => ResetB,
         DIB  => DataInB,
         ADB  => AddressB,
         DOB  => QB
      );
end;


library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

library lava1;
use lava1.components.all;

entity ram_dq  is
  generic( lpm_type               : string  := "Lattice_MEM";
	   module_type            : string  := "RAM_DQ";
	   module_width           : integer := 1;
	   module_numwords        : integer := 1;
	   module_widthad         : integer := 1;
  	   module_indata          : string  := "REGISTERED";
	   module_outdata         : string  := "REGISTERED";
	   module_address_control : string  := "UNREGISTERED";
           module_init_file       : string := "";
	   module_hint            : string  := "UNUSED");

  port(

           Data                : in  std_logic_vector (module_width-1 downto 0);
           Address             : in  std_logic_vector (module_widthad-1 downto 0);
           Clock               : in  std_logic;
           ClockEn             : in  std_logic;
           WE                  : in  std_logic;
           Q                   : out std_logic_vector (module_width-1 downto 0));
  end ram_dq;


architecture fun_simulation of ram_dq is


  component SC_SPRAM_16K_L

  generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        MEM_INIT_FLAG  : integer := 1; 
        ARRAY_SIZE     : integer := 511; 
	MEM_INIT_FILE  : string  := "qq.dat"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end component;

component SC_SPRAMA_16K_L

  generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        ARRAY_SIZE     : integer := 16384;
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "mem_init_file"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end component ;

    signal cs   : std_logic_vector (1 downto 0);
    signal Q_K       : std_logic_vector (module_width-1 downto 0);
    signal Q_KA      : std_logic_vector (module_width-1 downto 0);
    CONSTANT  module_init_flag       :  integer := init_flag(module_init_file);
    signal GND_sig   : std_logic;

  begin

      GND_sig <= '0';
      cs <= "11";

      SelectOut  : process (Q_K , Q_KA)
        begin
              if(module_address_control = "UNREGISTERED" and module_outdata = "UNREGISTERED") then
                     Q <= Q_KA;
              elsif(module_address_control = "UNREGISTERED" and module_outdata = "REGISTERED") then
                     Q <= Q_K;
              end if;
        end process;

  SPRAM_inst : SC_SPRAM_16K_L

  generic map (

        DEVICE_FAMILY  => open,
        ADDR_WIDTH     => module_widthad,
        DATA_WIDTH     => module_width,
        MEM_INIT_FLAG  => module_init_flag,
        ARRAY_SIZE     => module_numwords * module_width,
	MEM_INIT_FILE  => module_init_file)

  port map (
        CEN  => ClockEn, 
        CLK  => Clock, 
         WR  => WE, 
         CS  => cs,
        RST  => GND_sig,
         DI  => Data,
         AD  => Address,
         DO  => Q_K
       ); 

  SPRAMA_inst : SC_SPRAMA_16K_L

  generic map (

        DEVICE_FAMILY  => open,
        ADDR_WIDTH     => module_widthad,
        DATA_WIDTH     => module_width,
        MEM_INIT_FLAG  => module_init_flag,
        ARRAY_SIZE     => module_numwords * module_width,
	MEM_INIT_FILE  => module_init_file)

  port map (
        CEN  => ClockEn, 
        CLK  => Clock, 
         WR  => WE, 
         CS  => cs,
        RST  => GND_sig,
         DI  => Data,
         AD  => Address,
         DO  => Q_KA
       ); 
end;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;

entity rom is
  generic ( lpm_type                  : string  := "Lattice_MEM";
	    module_type               : string  := "ROM";
	    module_width              : integer := 1;
	    module_numwords           : integer := 1;
	    module_widthad            : integer := 1;
	    module_outdata            : string  := "REGISTERED";
	    module_address_control    : string  := "UNREGISTERED";
            module_init_file          : string := "init_file";
	    module_hint               : string  := "UNUSED");
  port (
            Address       : in  std_logic_vector (module_widthad-1 downto 0);
            OutClock      : in  std_logic;
            OutClockEn    : in  std_logic;
            Q             : out std_logic_vector (module_width-1 downto 0));
end rom;

architecture fun_simulation of rom is

  component  SC_SPRAM_16K_L

    generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        ARRAY_SIZE     : integer := 511; 
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "qq.dat"

	);

    port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

  end component;

component SC_SPRAMA_16K_L

  generic (

        DEVICE_FAMILY  : string  := "LAVA1";
        ADDR_WIDTH     : integer := 13;
        DATA_WIDTH     : integer := 2;
        ARRAY_SIZE     : integer := 16384;
        MEM_INIT_FLAG  : integer := 1;  
	MEM_INIT_FILE  : string  := "mem_init_file"

	);

  port (
        CEN : in  STD_LOGIC ;
        CLK : in  STD_LOGIC ;
         WR : in  STD_LOGIC ;
         CS : in  STD_LOGIC_VECTOR (1 downto 0);
        RST : in  STD_LOGIC ;
         DI : in  STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
         AD : in  STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
         DO : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
       ); 

end component ;

        signal cs : std_logic_vector ( 1 downto 0);
        signal DI_sig : std_logic_vector (module_width-1 downto 0);
        signal WE_sig : std_logic;

        signal Q_K       : std_logic_vector (module_width-1 downto 0);
        signal Q_KA      : std_logic_vector (module_width-1 downto 0);
        signal GND_sig   : std_logic;

  begin

        GND_sig <= '0';
        cs <= "11";
        WE_sig <= '0';

      SelectOut  : process (Q_K, Q_KA)
        begin
              if(module_address_control = "UNREGISTERED" and module_outdata = "UNREGISTERED") then
                     Q <= Q_KA;
              elsif(module_address_control = "UNREGISTERED" and module_outdata = "REGISTERED") then
                     Q <= Q_K;
              end if;
        end process;

    SPRAM_inst :  SC_SPRAM_16K_L

      generic map(

           DEVICE_FAMILY  =>  open,
           ADDR_WIDTH     =>  module_widthad,
           DATA_WIDTH     =>  module_width, 
           MEM_INIT_FLAG  =>  1,
           ARRAY_SIZE     =>  module_numwords * module_width,
	   MEM_INIT_FILE  =>  module_init_file)

      port map(
           CEN    =>  OutClockEn,
           CLK    =>  OutClock,
           WR     =>  WE_sig,
           CS     =>  cs,
           RST    =>  GND_sig,
           DI     =>  DI_sig,
           AD     =>  Address,
           DO     =>  Q_K
       ); 

  SPRAMA_inst : SC_SPRAMA_16K_L

      generic map(

           DEVICE_FAMILY  =>  open,
           ADDR_WIDTH     =>  module_widthad,
           DATA_WIDTH     =>  module_width, 
           MEM_INIT_FLAG  =>  1,
           ARRAY_SIZE     =>  module_numwords * module_width,
	   MEM_INIT_FILE  =>  module_init_file)

      port map(
           CEN    =>  OutClockEn,
           CLK    =>  OutClock,
           WR     =>  WE_sig,
           CS     =>  cs,
           RST    =>  GND_sig,
           DI     =>  DI_sig,
           AD     =>  Address,
           DO     =>  Q_KA
       ); 
end;



---- end of library ----
